[people/ms/u-boot.git] / include / configs / trats.h

/*
 * Copyright (C) 2011 Samsung Electronics
 * Heungjun Kim <riverful.kim@samsung.com>
 *
 * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_SAMSUNG		/* in a SAMSUNG core */
#define CONFIG_S5P		/* which is in a S5P Family */
#define CONFIG_EXYNOS4210	/* which is in a EXYNOS4210 */
#define CONFIG_TRATS		/* working with TRATS */
#define CONFIG_TIZEN		/* TIZEN lib */

#include <asm/arch/cpu.h>	/* get chip and board defs */

#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE	0x10502000
#endif

#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_TEXT_BASE		0x63300000

/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
#define CONFIG_SYS_CLK_FREQ_C210	24000000
#define CONFIG_SYS_CLK_FREQ		CONFIG_SYS_CLK_FREQ_C210

#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F

/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
#define MACH_TYPE_TRATS			3928
#define CONFIG_MACH_TYPE		MACH_TYPE_TRATS

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))

/* select serial console configuration */
#define CONFIG_SERIAL2			/* use SERIAL 2 */
#define CONFIG_BAUDRATE			115200

/* MMC */
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC
#define CONFIG_S5P_SDHCI
#define CONFIG_SDHCI
#define CONFIG_MMC_SDMA

/* PWM */
#define CONFIG_PWM

/* It should define before config_cmd_default.h */
#define CONFIG_SYS_NO_FLASH

/* Command definition */
#include <config_cmd_default.h>

#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_MISC
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_XIMG
#undef CONFIG_CMD_CACHE
#undef CONFIG_CMD_ONENAND
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_MMC
#define CONFIG_CMD_DFU

/* FAT */
#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE

/* USB Composite download gadget - g_dnl */
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_DFU_FUNCTION
#define CONFIG_DFU_MMC

/* USB Samsung's IDs */
#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
#define CONFIG_G_DNL_MANUFACTURER "Samsung"

#define CONFIG_BOOTDELAY		1
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_BOOTARGS			"Please use defined boot"
#define CONFIG_BOOTCOMMAND		"run mmcboot"

#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
#define CONFIG_BOOTBLOCK		"10"
#define CONFIG_ENV_COMMON_BOOT		"${console} ${meminfo}"

#define CONFIG_DFU_ALT \
	"dfu_alt_info=" \
	"u-boot mmc 80 400;" \
	"uImage fat 0 2\0" \

#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_SYS_CONSOLE_IS_IN_ENV

#define CONFIG_EXTRA_ENV_SETTINGS \
	"bootk=" \
		"run loaduimage; bootm 0x40007FC0\0" \
	"updatemmc=" \
		"mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \
		"mmc boot 0 1 1 0\0" \
	"updatebackup=" \
		"mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \
		"mmc boot 0 1 1 0\0" \
	"updatebootb=" \
		"mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
	"lpj=lpj=3981312\0" \
	"nfsboot=" \
		"set bootargs root=/dev/nfs rw " \
		"nfsroot=${nfsroot},nolock,tcp " \
		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
		"${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
		"; run bootk\0" \
	"ramfsboot=" \
		"set bootargs root=/dev/ram0 rw rootfstype=ext2 " \
		"${console} ${meminfo} " \
		"initrd=0x43000000,8M ramdisk=8192\0" \
	"mmcboot=" \
		"set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
		"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
		"run loaduimage; bootm 0x40007FC0\0" \
	"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
	"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
	"verify=n\0" \
	"rootfstype=ext4\0" \
	"console=" CONFIG_DEFAULT_CONSOLE \
	"meminfo=crashkernel=32M@0x50000000\0" \
	"nfsroot=/nfsroot/arm\0" \
	"bootblock=" CONFIG_BOOTBLOCK "\0" \
	"loaduimage=fatload mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
	"mmcdev=0\0" \
	"mmcbootpart=2\0" \
	"mmcrootpart=3\0" \
	"opts=always_resume=1\0" \
	CONFIG_DFU_ALT

/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT		"TRATS # "
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4800000)

#define CONFIG_SYS_HZ			1000

/* TRATS has 2 banks of DRAM */
#define CONFIG_NR_DRAM_BANKS	2
#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE	/* LDDDR2 DMC 0 */
#define PHYS_SDRAM_1_SIZE	(512 << 20)		/* 512 MB in CS 0 */
#define PHYS_SDRAM_2		0x50000000		/* LPDDR2 DMC 1 */
#define PHYS_SDRAM_2_SIZE	(512 << 20)		/* 512 MB in CS 0 */

#define CONFIG_SYS_MEM_TOP_HIDE		(1 << 20)	/* ram console */

#define CONFIG_SYS_MONITOR_BASE		0x00000000
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV		0
#define CONFIG_ENV_SIZE			4096
#define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */

#define CONFIG_DOS_PARTITION

#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_CACHELINE_SIZE       32


#define CONFIG_SOFT_I2C
#define CONFIG_SOFT_I2C_READ_REPEATED_START
#define CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_SYS_I2C_SPEED	50000
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SOFT_I2C_MULTI_BUS
#define CONFIG_SYS_MAX_I2C_BUS	15

#include <asm/arch/gpio.h>

/* I2C PMIC */
#define CONFIG_SOFT_I2C_I2C5_SCL exynos4_gpio_part1_get_nr(b, 7)
#define CONFIG_SOFT_I2C_I2C5_SDA exynos4_gpio_part1_get_nr(b, 6)

/* I2C FG */
#define CONFIG_SOFT_I2C_I2C9_SCL exynos4_gpio_part2_get_nr(y4, 1)
#define CONFIG_SOFT_I2C_I2C9_SDA exynos4_gpio_part2_get_nr(y4, 0)

#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
#define I2C_INIT multi_i2c_init()

#define CONFIG_PMIC
#define CONFIG_PMIC_I2C
#define CONFIG_PMIC_MAX8997

#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_S3C_UDC_OTG
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW	2

/* LCD */
#define CONFIG_EXYNOS_FB
#define CONFIG_LCD
#define CONFIG_CMD_BMP
#define CONFIG_BMP_32BPP
#define CONFIG_FB_ADDR		0x52504000
#define CONFIG_S6E8AX0
#define CONFIG_EXYNOS_MIPI_DSIM
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 120 * 4) + (1 << 12))

#endif	/* __CONFIG_H */
Commit	Line	Data
89f95492 HK	1	/*
	2	* Copyright (C) 2011 Samsung Electronics
	3	* Heungjun Kim <riverful.kim@samsung.com>
	4	*
	5	* Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#ifndef __CONFIG_H
	27	#define __CONFIG_H
	28
	29	/*
	30	* High Level Configuration Options
	31	* (easy to change)
	32	*/
	33	#define CONFIG_SAMSUNG /* in a SAMSUNG core */
	34	#define CONFIG_S5P /* which is in a S5P Family */
	35	#define CONFIG_EXYNOS4210 /* which is in a EXYNOS4210 */
	36	#define CONFIG_TRATS /* working with TRATS */
90464971	37	#define CONFIG_TIZEN /* TIZEN lib */
89f95492 HK	38
	39	#include <asm/arch/cpu.h> /* get chip and board defs */
	40
	41	#define CONFIG_ARCH_CPU_INIT
	42	#define CONFIG_DISPLAY_CPUINFO
	43	#define CONFIG_DISPLAY_BOARDINFO
	44
d0460b01 ŁM	45	#ifndef CONFIG_SYS_L2CACHE_OFF
	46	#define CONFIG_SYS_L2_PL310
	47	#define CONFIG_SYS_PL310_BASE 0x10502000
	48	#endif
89f95492 HK	49
	50	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	51	#define CONFIG_SYS_TEXT_BASE 0x63300000
	52
	53	/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
	54	#define CONFIG_SYS_CLK_FREQ_C210 24000000
5e46f83c	55	#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210
89f95492 HK	56
	57	#define CONFIG_SETUP_MEMORY_TAGS
	58	#define CONFIG_CMDLINE_TAG
89f95492 HK	59	#define CONFIG_REVISION_TAG
	60	#define CONFIG_CMDLINE_EDITING
	61	#define CONFIG_SKIP_LOWLEVEL_INIT
	62	#define CONFIG_BOARD_EARLY_INIT_F
	63
	64	/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
	65	#define MACH_TYPE_TRATS 3928
	66	#define CONFIG_MACH_TYPE MACH_TYPE_TRATS
	67
	68	/* Size of malloc() pool */
	69	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
	70
	71	/* select serial console configuration */
89f95492 HK	72	#define CONFIG_SERIAL2 /* use SERIAL 2 */
	73	#define CONFIG_BAUDRATE 115200
	74
	75	/* MMC */
	76	#define CONFIG_GENERIC_MMC
	77	#define CONFIG_MMC
7d2d58b4 JC	78	#define CONFIG_S5P_SDHCI
7d2d58b4 JC	79	#define CONFIG_SDHCI
b09ed6e4	80	#define CONFIG_MMC_SDMA
89f95492 HK	81
	82	/* PWM */
	83	#define CONFIG_PWM
	84
	85	/* It should define before config_cmd_default.h */
	86	#define CONFIG_SYS_NO_FLASH
	87
	88	/* Command definition */
	89	#include <config_cmd_default.h>
	90
	91	#undef CONFIG_CMD_FPGA
	92	#undef CONFIG_CMD_MISC
	93	#undef CONFIG_CMD_NET
	94	#undef CONFIG_CMD_NFS
	95	#undef CONFIG_CMD_XIMG
	96	#undef CONFIG_CMD_CACHE
	97	#undef CONFIG_CMD_ONENAND
	98	#undef CONFIG_CMD_MTDPARTS
	99	#define CONFIG_CMD_MMC
93a1ab57 ŁM	100	#define CONFIG_CMD_DFU
	101
	102	/* FAT */
	103	#define CONFIG_CMD_FAT
	104	#define CONFIG_FAT_WRITE
	105
	106	/* USB Composite download gadget - g_dnl */
	107	#define CONFIG_USBDOWNLOAD_GADGET
	108	#define CONFIG_DFU_FUNCTION
	109	#define CONFIG_DFU_MMC
	110
	111	/* USB Samsung's IDs */
	112	#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
	113	#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
	114	#define CONFIG_G_DNL_MANUFACTURER "Samsung"
89f95492 HK	115
	116	#define CONFIG_BOOTDELAY 1
	117	#define CONFIG_ZERO_BOOTDELAY_CHECK
	118	#define CONFIG_BOOTARGS "Please use defined boot"
	119	#define CONFIG_BOOTCOMMAND "run mmcboot"
	120
	121	#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
	122	#define CONFIG_BOOTBLOCK "10"
	123	#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}"
	124
93a1ab57 ŁM	125	#define CONFIG_DFU_ALT \
	126	"dfu_alt_info=" \
	127	"u-boot mmc 80 400;" \
	128	"uImage fat 0 2\0" \
	129
89f95492 HK	130	#define CONFIG_ENV_OVERWRITE
	131	#define CONFIG_SYS_CONSOLE_INFO_QUIET
	132	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	133
	134	#define CONFIG_EXTRA_ENV_SETTINGS \
	135	"bootk=" \
	136	"run loaduimage; bootm 0x40007FC0\0" \
	137	"updatemmc=" \
	138	"mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \
	139	"mmc boot 0 1 1 0\0" \
	140	"updatebackup=" \
	141	"mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \
	142	"mmc boot 0 1 1 0\0" \
	143	"updatebootb=" \
	144	"mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
	145	"lpj=lpj=3981312\0" \
	146	"nfsboot=" \
	147	"set bootargs root=/dev/nfs rw " \
	148	"nfsroot=${nfsroot},nolock,tcp " \
	149	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
	150	"${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
	151	"; run bootk\0" \
	152	"ramfsboot=" \
	153	"set bootargs root=/dev/ram0 rw rootfstype=ext2 " \
	154	"${console} ${meminfo} " \
	155	"initrd=0x43000000,8M ramdisk=8192\0" \
	156	"mmcboot=" \
	157	"set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
	158	"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
	159	"run loaduimage; bootm 0x40007FC0\0" \
	160	"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
	161	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
	162	"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
	163	"verify=n\0" \
	164	"rootfstype=ext4\0" \
	165	"console=" CONFIG_DEFAULT_CONSOLE \
	166	"meminfo=crashkernel=32M@0x50000000\0" \
	167	"nfsroot=/nfsroot/arm\0" \
	168	"bootblock=" CONFIG_BOOTBLOCK "\0" \
42e14f05	169	"loaduimage=fatload mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
89f95492 HK	170	"mmcdev=0\0" \
	171	"mmcbootpart=2\0" \
	172	"mmcrootpart=3\0" \
93a1ab57 ŁM	173	"opts=always_resume=1\0" \
93a1ab57 ŁM	174	CONFIG_DFU_ALT
89f95492 HK	175
	176	/* Miscellaneous configurable options */
	177	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	178	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
89f95492 HK	179	#define CONFIG_SYS_PROMPT "TRATS # "
	180	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	181	#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
	182	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	183	/* Boot Argument Buffer Size */
	184	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	185	/* memtest works on */
	186	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	187	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
	188	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
	189
	190	#define CONFIG_SYS_HZ 1000
	191
89f95492 HK	192	/* TRATS has 2 banks of DRAM */
	193	#define CONFIG_NR_DRAM_BANKS 2
	194	#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */
e687c5a8	195	#define PHYS_SDRAM_1_SIZE (512 << 20) /* 512 MB in CS 0 */
89f95492	196	#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */
e687c5a8	197	#define PHYS_SDRAM_2_SIZE (512 << 20) /* 512 MB in CS 0 */
89f95492 HK	198
	199	#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
	200
	201	#define CONFIG_SYS_MONITOR_BASE 0x00000000
	202	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
	203
	204	#define CONFIG_ENV_IS_IN_MMC
	205	#define CONFIG_SYS_MMC_ENV_DEV 0
	206	#define CONFIG_ENV_SIZE 4096
	207	#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
	208
	209	#define CONFIG_DOS_PARTITION
	210
	211	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
	212	#define CONFIG_SYS_CACHELINE_SIZE 32
	213
89f95492 HK	214
	215	#define CONFIG_SOFT_I2C
	216	#define CONFIG_SOFT_I2C_READ_REPEATED_START
fd8dca83	217	#define CONFIG_SYS_I2C_INIT_BOARD
89f95492 HK	218	#define CONFIG_SYS_I2C_SPEED 50000
89f95492 HK	219	#define CONFIG_I2C_MULTI_BUS
fd8dca83 ŁM	220	#define CONFIG_SOFT_I2C_MULTI_BUS
	221	#define CONFIG_SYS_MAX_I2C_BUS 15
	222
	223	#include <asm/arch/gpio.h>
	224
	225	/* I2C PMIC */
	226	#define CONFIG_SOFT_I2C_I2C5_SCL exynos4_gpio_part1_get_nr(b, 7)
	227	#define CONFIG_SOFT_I2C_I2C5_SDA exynos4_gpio_part1_get_nr(b, 6)
	228
	229	/* I2C FG */
	230	#define CONFIG_SOFT_I2C_I2C9_SCL exynos4_gpio_part2_get_nr(y4, 1)
	231	#define CONFIG_SOFT_I2C_I2C9_SDA exynos4_gpio_part2_get_nr(y4, 0)
	232
	233	#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
	234	#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
	235	#define I2C_INIT multi_i2c_init()
89f95492 HK	236
	237	#define CONFIG_PMIC
	238	#define CONFIG_PMIC_I2C
04ce68ee	239	#define CONFIG_PMIC_MAX8997
89f95492 HK	240
	241	#define CONFIG_USB_GADGET
	242	#define CONFIG_USB_GADGET_S3C_UDC_OTG
	243	#define CONFIG_USB_GADGET_DUALSPEED
93a1ab57	244	#define CONFIG_USB_GADGET_VBUS_DRAW 2
89f95492	245
51b1cd6d DL	246	/* LCD */
	247	#define CONFIG_EXYNOS_FB
	248	#define CONFIG_LCD
90464971 DL	249	#define CONFIG_CMD_BMP
90464971 DL	250	#define CONFIG_BMP_32BPP
51b1cd6d DL	251	#define CONFIG_FB_ADDR 0x52504000
	252	#define CONFIG_S6E8AX0
	253	#define CONFIG_EXYNOS_MIPI_DSIM
90464971 DL	254	#define CONFIG_VIDEO_BMP_GZIP
90464971 DL	255	#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 120 * 4) + (1 << 12))
51b1cd6d	256
89f95492	257	#endif /* __CONFIG_H */