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4d6c9671 PW |
1 | /* |
2 | * Copyright (C) 2013 Samsung Electronics | |
3 | * Sanghee Kim <sh0130.kim@samsung.com> | |
4 | * Piotr Wilczek <p.wilczek@samsung.com> | |
5 | * | |
6 | * Configuation settings for the SAMSUNG TRATS2 (EXYNOS4412) board. | |
7 | * | |
8 | * SPDX-License-Identifier: GPL-2.0+ | |
9 | */ | |
10 | ||
1ecab0f3 PW |
11 | #ifndef __CONFIG_TRATS2_H |
12 | #define __CONFIG_TRATS2_H | |
4d6c9671 | 13 | |
4c7bb1d2 | 14 | #include <configs/exynos4-common.h> |
4d6c9671 | 15 | |
1ecab0f3 | 16 | #define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */ |
4d6c9671 | 17 | |
4d6c9671 | 18 | |
1ecab0f3 | 19 | #define CONFIG_TIZEN /* TIZEN lib */ |
4d6c9671 | 20 | |
c4e96dbf | 21 | #define CONFIG_SYS_L2CACHE_OFF |
4d6c9671 PW |
22 | #ifndef CONFIG_SYS_L2CACHE_OFF |
23 | #define CONFIG_SYS_L2_PL310 | |
24 | #define CONFIG_SYS_PL310_BASE 0x10502000 | |
25 | #endif | |
26 | ||
1ecab0f3 PW |
27 | /* TRATS2 has 4 banks of DRAM */ |
28 | #define CONFIG_NR_DRAM_BANKS 4 | |
29 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 | |
30 | #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE | |
31 | #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ | |
32 | /* memtest works on */ | |
33 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
34 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) | |
35 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) | |
4d6c9671 | 36 | |
00b132bf | 37 | #define CONFIG_SYS_TEXT_BASE 0x43e00000 |
4d6c9671 | 38 | |
4d6c9671 PW |
39 | /* select serial console configuration */ |
40 | #define CONFIG_SERIAL2 | |
1ecab0f3 | 41 | #define CONFIG_BAUDRATE 115200 |
4d6c9671 | 42 | |
1ecab0f3 PW |
43 | /* Console configuration */ |
44 | #define CONFIG_SYS_CONSOLE_INFO_QUIET | |
45 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
4d6c9671 | 46 | |
1ecab0f3 PW |
47 | #define CONFIG_BOOTARGS "Please use defined boot" |
48 | #define CONFIG_BOOTCOMMAND "run mmcboot" | |
2ee93246 | 49 | #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" |
4d6c9671 | 50 | |
1ecab0f3 PW |
51 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ |
52 | - GENERATED_GBL_DATA_SIZE) | |
4d6c9671 | 53 | |
1ecab0f3 PW |
54 | #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ |
55 | ||
56 | #define CONFIG_SYS_MONITOR_BASE 0x00000000 | |
57 | ||
58 | #define CONFIG_ENV_IS_IN_MMC | |
59 | #define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV | |
60 | #define CONFIG_ENV_SIZE 4096 | |
61 | #define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ | |
4d6c9671 PW |
62 | |
63 | #define CONFIG_ENV_OVERWRITE | |
4d6c9671 | 64 | |
8c57fb7d PW |
65 | #define CONFIG_ENV_VARS_UBOOT_CONFIG |
66 | #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG | |
67 | ||
4d6c9671 | 68 | /* Tizen - partitions definitions */ |
18f3e0eb | 69 | #define PARTS_CSA "csa-mmc" |
4d6c9671 | 70 | #define PARTS_BOOT "boot" |
18f3e0eb | 71 | #define PARTS_QBOOT "qboot" |
dca36684 | 72 | #define PARTS_CSC "csc" |
4d6c9671 PW |
73 | #define PARTS_ROOT "platform" |
74 | #define PARTS_DATA "data" | |
4d6c9671 PW |
75 | #define PARTS_UMS "ums" |
76 | ||
77 | #define PARTS_DEFAULT \ | |
a5e15bbb | 78 | "uuid_disk=${uuid_gpt_disk};" \ |
dca36684 | 79 | "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ |
18f3e0eb PM |
80 | "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ |
81 | "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \ | |
4d6c9671 | 82 | "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ |
dca36684 | 83 | "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ |
18f3e0eb | 84 | "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ |
4d6c9671 PW |
85 | "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ |
86 | ||
09f98010 | 87 | #define CONFIG_DFU_ALT \ |
b7d4259a | 88 | "u-boot raw 0x80 0x800;" \ |
dcb7eb66 ŁM |
89 | "/uImage ext4 0 2;" \ |
90 | "/modem.bin ext4 0 2;" \ | |
91 | "/exynos4412-trats2.dtb ext4 0 2;" \ | |
18f3e0eb | 92 | ""PARTS_CSA" part 0 1;" \ |
cdd15bce | 93 | ""PARTS_BOOT" part 0 2;" \ |
18f3e0eb PM |
94 | ""PARTS_QBOOT" part 0 3;" \ |
95 | ""PARTS_CSC" part 0 4;" \ | |
cdd15bce ŁM |
96 | ""PARTS_ROOT" part 0 5;" \ |
97 | ""PARTS_DATA" part 0 6;" \ | |
a0afc6f3 | 98 | ""PARTS_UMS" part 0 7;" \ |
b7d4259a | 99 | "params.bin raw 0x38 0x8\0" |
09f98010 | 100 | |
4d6c9671 PW |
101 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
102 | "bootk=" \ | |
425e26de PW |
103 | "run loaduimage;" \ |
104 | "if run loaddtb; then " \ | |
105 | "bootm 0x40007FC0 - ${fdtaddr};" \ | |
106 | "fi;" \ | |
107 | "bootm 0x40007FC0;\0" \ | |
4d6c9671 | 108 | "updatebackup=" \ |
188c42b3 JC |
109 | "mmc dev 0 2; mmc write 0x51000000 0 0x800;" \ |
110 | " mmc dev 0 0\0" \ | |
4d6c9671 | 111 | "updatebootb=" \ |
188c42b3 | 112 | "mmc read 0x51000000 0x80 0x800; run updatebackup\0" \ |
4d6c9671 PW |
113 | "mmcboot=" \ |
114 | "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ | |
115 | "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ | |
425e26de | 116 | "run bootk\0" \ |
4d6c9671 PW |
117 | "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ |
118 | "boottrace=setenv opts initcall_debug; run bootcmd\0" \ | |
119 | "verify=n\0" \ | |
120 | "rootfstype=ext4\0" \ | |
121 | "console=" CONFIG_DEFAULT_CONSOLE \ | |
122 | "kernelname=uImage\0" \ | |
2c8043c9 PW |
123 | "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 " \ |
124 | "${kernelname}\0" \ | |
4d6c9671 PW |
125 | "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \ |
126 | "${fdtfile}\0" \ | |
a5e15bbb | 127 | "mmcdev=" __stringify(CONFIG_MMC_DEFAULT_DEV) "\0" \ |
4d6c9671 PW |
128 | "mmcbootpart=2\0" \ |
129 | "mmcrootpart=5\0" \ | |
130 | "opts=always_resume=1\0" \ | |
131 | "partitions=" PARTS_DEFAULT \ | |
09f98010 | 132 | "dfu_alt_info=" CONFIG_DFU_ALT \ |
4d6c9671 PW |
133 | "uartpath=ap\0" \ |
134 | "usbpath=ap\0" \ | |
135 | "consoleon=set console console=ttySAC2,115200n8; save; reset\0" \ | |
136 | "consoleoff=set console console=ram; save; reset\0" \ | |
137 | "spladdr=0x40000100\0" \ | |
138 | "splsize=0x200\0" \ | |
139 | "splfile=falcon.bin\0" \ | |
140 | "spl_export=" \ | |
141 | "setexpr spl_imgsize ${splsize} + 8 ;" \ | |
142 | "setenv spl_imgsize 0x${spl_imgsize};" \ | |
143 | "setexpr spl_imgaddr ${spladdr} - 8 ;" \ | |
144 | "setexpr spl_addr_tmp ${spladdr} - 4 ;" \ | |
145 | "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \ | |
146 | "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ | |
147 | "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \ | |
148 | "spl export atags 0x40007FC0;" \ | |
149 | "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \ | |
150 | "mw.l ${spl_addr_tmp} ${splsize};" \ | |
151 | "ext4write mmc ${mmcdev}:${mmcbootpart}" \ | |
152 | " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \ | |
153 | "setenv spl_imgsize;" \ | |
154 | "setenv spl_imgaddr;" \ | |
155 | "setenv spl_addr_tmp;\0" \ | |
156 | "fdtaddr=40800000\0" \ | |
4d6c9671 | 157 | |
519fdde9 | 158 | /* GPT */ |
aafd2c5d | 159 | #define CONFIG_RANDOM_UUID |
4d6c9671 | 160 | |
4d6c9671 PW |
161 | /* I2C */ |
162 | #include <asm/arch/gpio.h> | |
163 | ||
1ecab0f3 PW |
164 | #define CONFIG_CMD_I2C |
165 | ||
4d6c9671 | 166 | #define CONFIG_SYS_I2C |
2d8f1e27 PW |
167 | #define CONFIG_SYS_I2C_S3C24X0 |
168 | #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 | |
169 | #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0 | |
170 | #define CONFIG_MAX_I2C_NUM 8 | |
171 | #define CONFIG_SYS_I2C_SOFT | |
4d6c9671 PW |
172 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 |
173 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0x00 | |
174 | #define I2C_SOFT_DECLARATIONS2 | |
175 | #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 | |
176 | #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x00 | |
4d6c9671 PW |
177 | #define CONFIG_SOFT_I2C_READ_REPEATED_START |
178 | #define CONFIG_SYS_I2C_INIT_BOARD | |
2d8f1e27 PW |
179 | |
180 | #ifndef __ASSEMBLY__ | |
181 | int get_soft_i2c_scl_pin(void); | |
182 | int get_soft_i2c_sda_pin(void); | |
183 | #endif | |
184 | #define CONFIG_SOFT_I2C_GPIO_SCL get_soft_i2c_scl_pin() | |
185 | #define CONFIG_SOFT_I2C_GPIO_SDA get_soft_i2c_sda_pin() | |
4d6c9671 PW |
186 | |
187 | /* POWER */ | |
188 | #define CONFIG_POWER | |
189 | #define CONFIG_POWER_I2C | |
190 | #define CONFIG_POWER_MAX77686 | |
191 | #define CONFIG_POWER_PMIC_MAX77693 | |
192 | #define CONFIG_POWER_MUIC_MAX77693 | |
193 | #define CONFIG_POWER_FG_MAX77693 | |
194 | #define CONFIG_POWER_BATTERY_TRATS2 | |
195 | ||
e0021706 PM |
196 | /* Security subsystem - enable hw_rand() */ |
197 | #define CONFIG_EXYNOS_ACE_SHA | |
198 | #define CONFIG_LIB_HW_RAND | |
199 | ||
679549d1 PM |
200 | /* Common misc for Samsung */ |
201 | #define CONFIG_MISC_COMMON | |
202 | ||
203 | #define CONFIG_MISC_INIT_R | |
204 | ||
f64236a9 PM |
205 | /* Download menu - Samsung common */ |
206 | #define CONFIG_LCD_MENU | |
207 | #define CONFIG_LCD_MENU_BOARD | |
208 | ||
209 | /* Download menu - definitions for check keys */ | |
210 | #ifndef __ASSEMBLY__ | |
211 | #include <power/max77686_pmic.h> | |
212 | ||
213 | #define KEY_PWR_PMIC_NAME "MAX77686_PMIC" | |
214 | #define KEY_PWR_STATUS_REG MAX77686_REG_PMIC_STATUS1 | |
215 | #define KEY_PWR_STATUS_MASK (1 << 0) | |
216 | #define KEY_PWR_INTERRUPT_REG MAX77686_REG_PMIC_INT1 | |
217 | #define KEY_PWR_INTERRUPT_MASK (1 << 1) | |
218 | ||
9b97b727 AS |
219 | #define KEY_VOL_UP_GPIO EXYNOS4X12_GPIO_X22 |
220 | #define KEY_VOL_DOWN_GPIO EXYNOS4X12_GPIO_X33 | |
f64236a9 PM |
221 | #endif /* __ASSEMBLY__ */ |
222 | ||
223 | /* LCD console */ | |
224 | #define LCD_BPP LCD_COLOR16 | |
225 | #define CONFIG_SYS_WHITE_ON_BLACK | |
226 | ||
4d6c9671 PW |
227 | /* LCD */ |
228 | #define CONFIG_EXYNOS_FB | |
229 | #define CONFIG_LCD | |
230 | #define CONFIG_CMD_BMP | |
2df21cb3 | 231 | #define CONFIG_BMP_16BPP |
4d6c9671 PW |
232 | #define CONFIG_FB_ADDR 0x52504000 |
233 | #define CONFIG_S6E8AX0 | |
234 | #define CONFIG_EXYNOS_MIPI_DSIM | |
235 | #define CONFIG_VIDEO_BMP_GZIP | |
903afe18 | 236 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) |
4d6c9671 | 237 | |
4d6c9671 | 238 | #endif /* __CONFIG_H */ |