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4d6c9671 PW |
1 | /* |
2 | * Copyright (C) 2013 Samsung Electronics | |
3 | * Sanghee Kim <sh0130.kim@samsung.com> | |
4 | * Piotr Wilczek <p.wilczek@samsung.com> | |
5 | * | |
6 | * Configuation settings for the SAMSUNG TRATS2 (EXYNOS4412) board. | |
7 | * | |
8 | * SPDX-License-Identifier: GPL-2.0+ | |
9 | */ | |
10 | ||
1ecab0f3 PW |
11 | #ifndef __CONFIG_TRATS2_H |
12 | #define __CONFIG_TRATS2_H | |
4d6c9671 | 13 | |
4c7bb1d2 | 14 | #include <configs/exynos4-common.h> |
4d6c9671 | 15 | |
1ecab0f3 | 16 | #define CONFIG_TIZEN /* TIZEN lib */ |
4d6c9671 | 17 | |
c4e96dbf | 18 | #define CONFIG_SYS_L2CACHE_OFF |
4d6c9671 PW |
19 | #ifndef CONFIG_SYS_L2CACHE_OFF |
20 | #define CONFIG_SYS_L2_PL310 | |
21 | #define CONFIG_SYS_PL310_BASE 0x10502000 | |
22 | #endif | |
23 | ||
1ecab0f3 PW |
24 | /* TRATS2 has 4 banks of DRAM */ |
25 | #define CONFIG_NR_DRAM_BANKS 4 | |
26 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 | |
27 | #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE | |
28 | #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ | |
29 | /* memtest works on */ | |
30 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
31 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) | |
32 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) | |
4d6c9671 | 33 | |
4d6c9671 PW |
34 | /* select serial console configuration */ |
35 | #define CONFIG_SERIAL2 | |
36 | ||
1ecab0f3 | 37 | /* Console configuration */ |
4d6c9671 | 38 | |
1018b0a5 | 39 | #define CONFIG_BOOTCOMMAND "run autoboot" |
232ed3ca | 40 | #define CONFIG_DEFAULT_CONSOLE "ttySAC2,115200n8" |
4d6c9671 | 41 | |
1ecab0f3 PW |
42 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ |
43 | - GENERATED_GBL_DATA_SIZE) | |
4d6c9671 | 44 | |
1ecab0f3 PW |
45 | #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ |
46 | ||
47 | #define CONFIG_SYS_MONITOR_BASE 0x00000000 | |
48 | ||
1ecab0f3 PW |
49 | #define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV |
50 | #define CONFIG_ENV_SIZE 4096 | |
51 | #define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ | |
4d6c9671 PW |
52 | |
53 | #define CONFIG_ENV_OVERWRITE | |
4d6c9671 | 54 | |
8c57fb7d PW |
55 | #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
56 | ||
4d6c9671 | 57 | /* Tizen - partitions definitions */ |
18f3e0eb | 58 | #define PARTS_CSA "csa-mmc" |
4d6c9671 | 59 | #define PARTS_BOOT "boot" |
18f3e0eb | 60 | #define PARTS_QBOOT "qboot" |
dca36684 | 61 | #define PARTS_CSC "csc" |
4d6c9671 PW |
62 | #define PARTS_ROOT "platform" |
63 | #define PARTS_DATA "data" | |
4d6c9671 PW |
64 | #define PARTS_UMS "ums" |
65 | ||
66 | #define PARTS_DEFAULT \ | |
a5e15bbb | 67 | "uuid_disk=${uuid_gpt_disk};" \ |
dca36684 | 68 | "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ |
18f3e0eb PM |
69 | "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ |
70 | "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \ | |
4d6c9671 | 71 | "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ |
dca36684 | 72 | "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ |
18f3e0eb | 73 | "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ |
4d6c9671 PW |
74 | "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ |
75 | ||
09f98010 | 76 | #define CONFIG_DFU_ALT \ |
b7d4259a | 77 | "u-boot raw 0x80 0x800;" \ |
dcb7eb66 ŁM |
78 | "/uImage ext4 0 2;" \ |
79 | "/modem.bin ext4 0 2;" \ | |
80 | "/exynos4412-trats2.dtb ext4 0 2;" \ | |
18f3e0eb | 81 | ""PARTS_CSA" part 0 1;" \ |
cdd15bce | 82 | ""PARTS_BOOT" part 0 2;" \ |
18f3e0eb PM |
83 | ""PARTS_QBOOT" part 0 3;" \ |
84 | ""PARTS_CSC" part 0 4;" \ | |
cdd15bce ŁM |
85 | ""PARTS_ROOT" part 0 5;" \ |
86 | ""PARTS_DATA" part 0 6;" \ | |
a0afc6f3 | 87 | ""PARTS_UMS" part 0 7;" \ |
1018b0a5 ŁM |
88 | "params.bin raw 0x38 0x8;" \ |
89 | "/Image.itb ext4 0 2\0" | |
09f98010 | 90 | |
4d6c9671 PW |
91 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
92 | "bootk=" \ | |
425e26de PW |
93 | "run loaduimage;" \ |
94 | "if run loaddtb; then " \ | |
95 | "bootm 0x40007FC0 - ${fdtaddr};" \ | |
96 | "fi;" \ | |
97 | "bootm 0x40007FC0;\0" \ | |
4d6c9671 | 98 | "updatebackup=" \ |
188c42b3 JC |
99 | "mmc dev 0 2; mmc write 0x51000000 0 0x800;" \ |
100 | " mmc dev 0 0\0" \ | |
4d6c9671 | 101 | "updatebootb=" \ |
188c42b3 | 102 | "mmc read 0x51000000 0x80 0x800; run updatebackup\0" \ |
4d6c9671 PW |
103 | "mmcboot=" \ |
104 | "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ | |
105 | "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ | |
425e26de | 106 | "run bootk\0" \ |
4d6c9671 PW |
107 | "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ |
108 | "boottrace=setenv opts initcall_debug; run bootcmd\0" \ | |
109 | "verify=n\0" \ | |
110 | "rootfstype=ext4\0" \ | |
232ed3ca | 111 | "console=" CONFIG_DEFAULT_CONSOLE "\0" \ |
4d6c9671 | 112 | "kernelname=uImage\0" \ |
2c8043c9 PW |
113 | "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 " \ |
114 | "${kernelname}\0" \ | |
4d6c9671 PW |
115 | "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \ |
116 | "${fdtfile}\0" \ | |
a5e15bbb | 117 | "mmcdev=" __stringify(CONFIG_MMC_DEFAULT_DEV) "\0" \ |
4d6c9671 PW |
118 | "mmcbootpart=2\0" \ |
119 | "mmcrootpart=5\0" \ | |
120 | "opts=always_resume=1\0" \ | |
121 | "partitions=" PARTS_DEFAULT \ | |
09f98010 | 122 | "dfu_alt_info=" CONFIG_DFU_ALT \ |
4d6c9671 PW |
123 | "uartpath=ap\0" \ |
124 | "usbpath=ap\0" \ | |
125 | "consoleon=set console console=ttySAC2,115200n8; save; reset\0" \ | |
126 | "consoleoff=set console console=ram; save; reset\0" \ | |
127 | "spladdr=0x40000100\0" \ | |
128 | "splsize=0x200\0" \ | |
129 | "splfile=falcon.bin\0" \ | |
130 | "spl_export=" \ | |
131 | "setexpr spl_imgsize ${splsize} + 8 ;" \ | |
132 | "setenv spl_imgsize 0x${spl_imgsize};" \ | |
133 | "setexpr spl_imgaddr ${spladdr} - 8 ;" \ | |
134 | "setexpr spl_addr_tmp ${spladdr} - 4 ;" \ | |
135 | "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \ | |
136 | "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ | |
137 | "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \ | |
138 | "spl export atags 0x40007FC0;" \ | |
139 | "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \ | |
140 | "mw.l ${spl_addr_tmp} ${splsize};" \ | |
141 | "ext4write mmc ${mmcdev}:${mmcbootpart}" \ | |
142 | " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \ | |
143 | "setenv spl_imgsize;" \ | |
144 | "setenv spl_imgaddr;" \ | |
145 | "setenv spl_addr_tmp;\0" \ | |
1018b0a5 | 146 | CONFIG_EXTRA_ENV_ITB \ |
4d6c9671 | 147 | "fdtaddr=40800000\0" \ |
4d6c9671 | 148 | |
519fdde9 | 149 | /* GPT */ |
4d6c9671 | 150 | |
e0021706 PM |
151 | /* Security subsystem - enable hw_rand() */ |
152 | #define CONFIG_EXYNOS_ACE_SHA | |
e0021706 | 153 | |
679549d1 PM |
154 | /* Common misc for Samsung */ |
155 | #define CONFIG_MISC_COMMON | |
156 | ||
157 | #define CONFIG_MISC_INIT_R | |
158 | ||
f64236a9 PM |
159 | /* Download menu - Samsung common */ |
160 | #define CONFIG_LCD_MENU | |
f64236a9 PM |
161 | |
162 | /* Download menu - definitions for check keys */ | |
163 | #ifndef __ASSEMBLY__ | |
f64236a9 PM |
164 | |
165 | #define KEY_PWR_PMIC_NAME "MAX77686_PMIC" | |
166 | #define KEY_PWR_STATUS_REG MAX77686_REG_PMIC_STATUS1 | |
167 | #define KEY_PWR_STATUS_MASK (1 << 0) | |
168 | #define KEY_PWR_INTERRUPT_REG MAX77686_REG_PMIC_INT1 | |
169 | #define KEY_PWR_INTERRUPT_MASK (1 << 1) | |
170 | ||
9b97b727 AS |
171 | #define KEY_VOL_UP_GPIO EXYNOS4X12_GPIO_X22 |
172 | #define KEY_VOL_DOWN_GPIO EXYNOS4X12_GPIO_X33 | |
f64236a9 PM |
173 | #endif /* __ASSEMBLY__ */ |
174 | ||
175 | /* LCD console */ | |
176 | #define LCD_BPP LCD_COLOR16 | |
f64236a9 | 177 | |
4d6c9671 | 178 | /* LCD */ |
2df21cb3 | 179 | #define CONFIG_BMP_16BPP |
4d6c9671 | 180 | #define CONFIG_FB_ADDR 0x52504000 |
4d6c9671 PW |
181 | #define CONFIG_EXYNOS_MIPI_DSIM |
182 | #define CONFIG_VIDEO_BMP_GZIP | |
903afe18 | 183 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) |
4d6c9671 | 184 | |
4d6c9671 | 185 | #endif /* __CONFIG_H */ |