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4d6c9671 PW |
1 | /* |
2 | * Copyright (C) 2013 Samsung Electronics | |
3 | * Sanghee Kim <sh0130.kim@samsung.com> | |
4 | * Piotr Wilczek <p.wilczek@samsung.com> | |
5 | * | |
6 | * Configuation settings for the SAMSUNG TRATS2 (EXYNOS4412) board. | |
7 | * | |
8 | * SPDX-License-Identifier: GPL-2.0+ | |
9 | */ | |
10 | ||
1ecab0f3 PW |
11 | #ifndef __CONFIG_TRATS2_H |
12 | #define __CONFIG_TRATS2_H | |
4d6c9671 | 13 | |
1ecab0f3 | 14 | #include <configs/exynos4-dt.h> |
4d6c9671 | 15 | |
1ecab0f3 | 16 | #define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */ |
4d6c9671 | 17 | |
1ecab0f3 PW |
18 | #undef CONFIG_DEFAULT_DEVICE_TREE |
19 | #define CONFIG_DEFAULT_DEVICE_TREE exynos4412-trats2 | |
4d6c9671 | 20 | |
1ecab0f3 | 21 | #define CONFIG_TIZEN /* TIZEN lib */ |
4d6c9671 | 22 | |
c4e96dbf | 23 | #define CONFIG_SYS_L2CACHE_OFF |
4d6c9671 PW |
24 | #ifndef CONFIG_SYS_L2CACHE_OFF |
25 | #define CONFIG_SYS_L2_PL310 | |
26 | #define CONFIG_SYS_PL310_BASE 0x10502000 | |
27 | #endif | |
28 | ||
1ecab0f3 PW |
29 | /* TRATS2 has 4 banks of DRAM */ |
30 | #define CONFIG_NR_DRAM_BANKS 4 | |
31 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 | |
32 | #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE | |
33 | #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ | |
34 | /* memtest works on */ | |
35 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
36 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) | |
37 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) | |
4d6c9671 | 38 | |
4d6c9671 PW |
39 | #define CONFIG_SYS_TEXT_BASE 0x78100000 |
40 | ||
1ace4022 | 41 | #include <linux/sizes.h> |
09f98010 PW |
42 | /* Size of malloc() pool */ |
43 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) | |
4d6c9671 PW |
44 | |
45 | /* select serial console configuration */ | |
46 | #define CONFIG_SERIAL2 | |
1ecab0f3 | 47 | #define CONFIG_BAUDRATE 115200 |
4d6c9671 | 48 | |
1ecab0f3 PW |
49 | /* Console configuration */ |
50 | #define CONFIG_SYS_CONSOLE_INFO_QUIET | |
51 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
4d6c9671 | 52 | |
1ecab0f3 PW |
53 | #define CONFIG_BOOTARGS "Please use defined boot" |
54 | #define CONFIG_BOOTCOMMAND "run mmcboot" | |
55 | #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" | |
4d6c9671 | 56 | |
1ecab0f3 PW |
57 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ |
58 | - GENERATED_GBL_DATA_SIZE) | |
4d6c9671 | 59 | |
1ecab0f3 PW |
60 | #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ |
61 | ||
62 | #define CONFIG_SYS_MONITOR_BASE 0x00000000 | |
63 | ||
64 | #define CONFIG_ENV_IS_IN_MMC | |
65 | #define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV | |
66 | #define CONFIG_ENV_SIZE 4096 | |
67 | #define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ | |
4d6c9671 PW |
68 | |
69 | #define CONFIG_ENV_OVERWRITE | |
4d6c9671 | 70 | |
8c57fb7d PW |
71 | #define CONFIG_ENV_VARS_UBOOT_CONFIG |
72 | #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG | |
73 | ||
4d6c9671 | 74 | /* Tizen - partitions definitions */ |
18f3e0eb | 75 | #define PARTS_CSA "csa-mmc" |
4d6c9671 | 76 | #define PARTS_BOOT "boot" |
18f3e0eb | 77 | #define PARTS_QBOOT "qboot" |
dca36684 | 78 | #define PARTS_CSC "csc" |
4d6c9671 PW |
79 | #define PARTS_ROOT "platform" |
80 | #define PARTS_DATA "data" | |
4d6c9671 PW |
81 | #define PARTS_UMS "ums" |
82 | ||
83 | #define PARTS_DEFAULT \ | |
a5e15bbb | 84 | "uuid_disk=${uuid_gpt_disk};" \ |
dca36684 | 85 | "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ |
18f3e0eb PM |
86 | "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ |
87 | "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \ | |
4d6c9671 | 88 | "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ |
dca36684 | 89 | "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ |
18f3e0eb | 90 | "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ |
4d6c9671 PW |
91 | "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ |
92 | ||
09f98010 PW |
93 | #define CONFIG_DFU_ALT \ |
94 | "u-boot mmc 80 800;" \ | |
95 | "uImage ext4 0 2;" \ | |
18f3e0eb | 96 | "modem.bin ext4 0 2;" \ |
09f98010 | 97 | "exynos4412-trats2.dtb ext4 0 2;" \ |
18f3e0eb | 98 | ""PARTS_CSA" part 0 1;" \ |
cdd15bce | 99 | ""PARTS_BOOT" part 0 2;" \ |
18f3e0eb PM |
100 | ""PARTS_QBOOT" part 0 3;" \ |
101 | ""PARTS_CSC" part 0 4;" \ | |
cdd15bce ŁM |
102 | ""PARTS_ROOT" part 0 5;" \ |
103 | ""PARTS_DATA" part 0 6;" \ | |
a0afc6f3 PM |
104 | ""PARTS_UMS" part 0 7;" \ |
105 | "params.bin mmc 0x38 0x8\0" | |
09f98010 | 106 | |
4d6c9671 PW |
107 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
108 | "bootk=" \ | |
425e26de PW |
109 | "run loaduimage;" \ |
110 | "if run loaddtb; then " \ | |
111 | "bootm 0x40007FC0 - ${fdtaddr};" \ | |
112 | "fi;" \ | |
113 | "bootm 0x40007FC0;\0" \ | |
4d6c9671 PW |
114 | "updatemmc=" \ |
115 | "mmc boot 0 1 1 1; mmc write 0x42008000 0 0x200;" \ | |
116 | "mmc boot 0 1 1 0\0" \ | |
117 | "updatebackup=" \ | |
118 | "mmc boot 0 1 1 2; mmc write 0x42100000 0 0x200;" \ | |
119 | " mmc boot 0 1 1 0\0" \ | |
120 | "updatebootb=" \ | |
121 | "mmc read 0x51000000 0x80 0x200; run updatebackup\0" \ | |
122 | "updateuboot=" \ | |
123 | "mmc write 0x50000000 0x80 0x400\0" \ | |
124 | "mmcboot=" \ | |
125 | "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ | |
126 | "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ | |
425e26de | 127 | "run bootk\0" \ |
4d6c9671 PW |
128 | "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ |
129 | "boottrace=setenv opts initcall_debug; run bootcmd\0" \ | |
130 | "verify=n\0" \ | |
131 | "rootfstype=ext4\0" \ | |
132 | "console=" CONFIG_DEFAULT_CONSOLE \ | |
133 | "kernelname=uImage\0" \ | |
2c8043c9 PW |
134 | "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 " \ |
135 | "${kernelname}\0" \ | |
4d6c9671 PW |
136 | "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \ |
137 | "${fdtfile}\0" \ | |
a5e15bbb | 138 | "mmcdev=" __stringify(CONFIG_MMC_DEFAULT_DEV) "\0" \ |
4d6c9671 PW |
139 | "mmcbootpart=2\0" \ |
140 | "mmcrootpart=5\0" \ | |
141 | "opts=always_resume=1\0" \ | |
142 | "partitions=" PARTS_DEFAULT \ | |
09f98010 | 143 | "dfu_alt_info=" CONFIG_DFU_ALT \ |
4d6c9671 PW |
144 | "uartpath=ap\0" \ |
145 | "usbpath=ap\0" \ | |
146 | "consoleon=set console console=ttySAC2,115200n8; save; reset\0" \ | |
147 | "consoleoff=set console console=ram; save; reset\0" \ | |
148 | "spladdr=0x40000100\0" \ | |
149 | "splsize=0x200\0" \ | |
150 | "splfile=falcon.bin\0" \ | |
151 | "spl_export=" \ | |
152 | "setexpr spl_imgsize ${splsize} + 8 ;" \ | |
153 | "setenv spl_imgsize 0x${spl_imgsize};" \ | |
154 | "setexpr spl_imgaddr ${spladdr} - 8 ;" \ | |
155 | "setexpr spl_addr_tmp ${spladdr} - 4 ;" \ | |
156 | "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \ | |
157 | "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ | |
158 | "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \ | |
159 | "spl export atags 0x40007FC0;" \ | |
160 | "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \ | |
161 | "mw.l ${spl_addr_tmp} ${splsize};" \ | |
162 | "ext4write mmc ${mmcdev}:${mmcbootpart}" \ | |
163 | " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \ | |
164 | "setenv spl_imgsize;" \ | |
165 | "setenv spl_imgaddr;" \ | |
166 | "setenv spl_addr_tmp;\0" \ | |
167 | "fdtaddr=40800000\0" \ | |
4d6c9671 | 168 | |
4d6c9671 PW |
169 | /* I2C */ |
170 | #include <asm/arch/gpio.h> | |
171 | ||
1ecab0f3 PW |
172 | #define CONFIG_CMD_I2C |
173 | ||
4d6c9671 | 174 | #define CONFIG_SYS_I2C |
2d8f1e27 PW |
175 | #define CONFIG_SYS_I2C_S3C24X0 |
176 | #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 | |
177 | #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0 | |
178 | #define CONFIG_MAX_I2C_NUM 8 | |
179 | #define CONFIG_SYS_I2C_SOFT | |
4d6c9671 PW |
180 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 |
181 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0x00 | |
182 | #define I2C_SOFT_DECLARATIONS2 | |
183 | #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 | |
184 | #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x00 | |
4d6c9671 PW |
185 | #define CONFIG_SOFT_I2C_READ_REPEATED_START |
186 | #define CONFIG_SYS_I2C_INIT_BOARD | |
2d8f1e27 PW |
187 | |
188 | #ifndef __ASSEMBLY__ | |
189 | int get_soft_i2c_scl_pin(void); | |
190 | int get_soft_i2c_sda_pin(void); | |
191 | #endif | |
192 | #define CONFIG_SOFT_I2C_GPIO_SCL get_soft_i2c_scl_pin() | |
193 | #define CONFIG_SOFT_I2C_GPIO_SDA get_soft_i2c_sda_pin() | |
4d6c9671 PW |
194 | |
195 | /* POWER */ | |
196 | #define CONFIG_POWER | |
197 | #define CONFIG_POWER_I2C | |
198 | #define CONFIG_POWER_MAX77686 | |
199 | #define CONFIG_POWER_PMIC_MAX77693 | |
200 | #define CONFIG_POWER_MUIC_MAX77693 | |
201 | #define CONFIG_POWER_FG_MAX77693 | |
202 | #define CONFIG_POWER_BATTERY_TRATS2 | |
203 | ||
679549d1 PM |
204 | /* Common misc for Samsung */ |
205 | #define CONFIG_MISC_COMMON | |
206 | ||
207 | #define CONFIG_MISC_INIT_R | |
208 | ||
f64236a9 PM |
209 | /* Download menu - Samsung common */ |
210 | #define CONFIG_LCD_MENU | |
211 | #define CONFIG_LCD_MENU_BOARD | |
212 | ||
213 | /* Download menu - definitions for check keys */ | |
214 | #ifndef __ASSEMBLY__ | |
215 | #include <power/max77686_pmic.h> | |
216 | ||
217 | #define KEY_PWR_PMIC_NAME "MAX77686_PMIC" | |
218 | #define KEY_PWR_STATUS_REG MAX77686_REG_PMIC_STATUS1 | |
219 | #define KEY_PWR_STATUS_MASK (1 << 0) | |
220 | #define KEY_PWR_INTERRUPT_REG MAX77686_REG_PMIC_INT1 | |
221 | #define KEY_PWR_INTERRUPT_MASK (1 << 1) | |
222 | ||
223 | #define KEY_VOL_UP_GPIO exynos4x12_gpio_get(2, x2, 2) | |
224 | #define KEY_VOL_DOWN_GPIO exynos4x12_gpio_get(2, x3, 3) | |
225 | #endif /* __ASSEMBLY__ */ | |
226 | ||
227 | /* LCD console */ | |
228 | #define LCD_BPP LCD_COLOR16 | |
229 | #define CONFIG_SYS_WHITE_ON_BLACK | |
230 | ||
4d6c9671 PW |
231 | /* LCD */ |
232 | #define CONFIG_EXYNOS_FB | |
233 | #define CONFIG_LCD | |
234 | #define CONFIG_CMD_BMP | |
2df21cb3 | 235 | #define CONFIG_BMP_16BPP |
4d6c9671 PW |
236 | #define CONFIG_FB_ADDR 0x52504000 |
237 | #define CONFIG_S6E8AX0 | |
238 | #define CONFIG_EXYNOS_MIPI_DSIM | |
239 | #define CONFIG_VIDEO_BMP_GZIP | |
903afe18 | 240 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) |
4d6c9671 | 241 | |
1ecab0f3 PW |
242 | #define LCD_XRES 720 |
243 | #define LCD_YRES 1280 | |
4d6c9671 PW |
244 | |
245 | #endif /* __CONFIG_H */ |