[people/ms/u-boot.git] / include / configs / tricorder.h

/*
 * (C) Copyright 2006-2008
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <x0khasim@ti.com>
 *
 * (C) Copyright 2012
 * Corscience GmbH & Co. KG
 * Thomas Weber <weber@corscience.de>
 *
 * Configuration settings for the Tricorder board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_SYS_CACHELINE_SIZE	64

/* High Level Configuration Options */
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_OMAP			/* in a TI OMAP core */
#define CONFIG_OMAP_COMMON
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766

#define CONFIG_MACH_TYPE		MACH_TYPE_TRICORDER
/*
 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 * 64 bytes before this address should be set aside for u-boot.img's
 * header. That is 0x800FFFC0--0x80100000 should not be used for any
 * other needs.
 */
#define CONFIG_SYS_TEXT_BASE		0x80100000

#define CONFIG_SDRC			/* The chip has SDRC controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap.h>

/* Display CPU and Board information */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_SILENT_CONSOLE

/* Clock Defines */
#define V_OSCK				26000000 /* Clock output from T2 */
#define V_SCLK				(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(1024*1024)

/* Hardware drivers */

/* GPIO support */
#define CONFIG_OMAP_GPIO

/* GPIO banks */
#define CONFIG_OMAP3_GPIO_2		/* GPIO32..63 are in GPIO bank 2 */

/* LED support */
#define CONFIG_STATUS_LED
#define CONFIG_BOARD_SPECIFIC_LED
#define CONFIG_CMD_LED			/* LED command */
#define STATUS_LED_BIT			(1 << 0)
#define STATUS_LED_STATE		STATUS_LED_ON
#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
#define STATUS_LED_BIT1			(1 << 1)
#define STATUS_LED_STATE1		STATUS_LED_ON
#define STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 2)
#define STATUS_LED_BIT2			(1 << 2)
#define STATUS_LED_STATE2		STATUS_LED_ON
#define STATUS_LED_PERIOD2		(CONFIG_SYS_HZ / 2)

/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		48000000 /* 48MHz (APLL96/2) */

/* select serial console configuration */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}

/* MMC */
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
#define CONFIG_SYS_I2C_OMAP34XX
 

/* EEPROM */
#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
#define CONFIG_SYS_EEPROM_BUS_NUM	1

/* TWL4030 */
#define CONFIG_TWL4030_POWER
#define CONFIG_TWL4030_LED

/* Board NAND Info */
#define CONFIG_SYS_NO_FLASH		/* no NOR flash */
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define MTDIDS_DEFAULT			"nand0=omap2-nand.0"
#define MTDPARTS_DEFAULT		"mtdparts=omap2-nand.0:" \
						"128k(SPL)," \
						"1m(u-boot)," \
						"384k(u-boot-env1)," \
						"1152k(mtdoops)," \
						"384k(u-boot-env2)," \
						"5m(kernel)," \
						"2m(fdt)," \
						"-(ubi)"

#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
							/* devices */
#define CONFIG_BCH
#define CONFIG_SYS_NAND_MAX_OOBFREE	2
#define CONFIG_SYS_NAND_MAX_ECCPOS	56

/* commands to include */
#define CONFIG_CMD_MTDPARTS		/* Enable MTD parts commands */
#define CONFIG_CMD_NAND			/* NAND support */
#define CONFIG_CMD_NAND_LOCK_UNLOCK	/* nand (un)lock commands */
#define CONFIG_CMD_UBI			/* UBI commands */
#define CONFIG_CMD_UBIFS		/* UBIFS commands */
#define CONFIG_LZO			/* LZO is needed for UBIFS */

#undef CONFIG_CMD_JFFS2			/* JFFS2 Support */

/* needed for ubi */
#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS

/* Environment information (this is the common part) */


/* hang() the board on panic() */
#define CONFIG_PANIC_HANG

/* environment placement (for NAND), is different for FLASHCARD but does not
 * harm there */
#define CONFIG_ENV_OFFSET		0x120000    /* env start */
#define CONFIG_ENV_OFFSET_REDUND	0x2A0000    /* redundant env start */
#define CONFIG_ENV_SIZE			(16 << 10)  /* use 16KiB for env */
#define CONFIG_ENV_RANGE		(384 << 10) /* allow badblocks in env */

/* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
 * value can not be used here! */
#define CONFIG_LOADADDR		0x82000000

#define CONFIG_COMMON_ENV_SETTINGS \
	"console=ttyO2,115200n8\0" \
	"mmcdev=0\0" \
	"vram=3M\0" \
	"defaultdisplay=lcd\0" \
	"kernelopts=mtdoops.mtddev=3\0" \
	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	"mtdids=" MTDIDS_DEFAULT "\0" \
	"commonargs=" \
		"setenv bootargs console=${console} " \
		"${mtdparts} " \
		"${kernelopts} " \
		"vt.global_cursor_default=0 " \
		"vram=${vram} " \
		"omapdss.def_disp=${defaultdisplay}\0"

#define CONFIG_BOOTCOMMAND "run autoboot"

/* specific environment settings for different use cases
 * FLASHCARD: used to run a rdimage from sdcard to program the device
 * 'NORMAL': used to boot kernel from sdcard, nand, ...
 *
 * The main aim for the FLASHCARD skin is to have an embedded environment
 * which will not be influenced by any data already on the device.
 */
#ifdef CONFIG_FLASHCARD

#define CONFIG_ENV_IS_NOWHERE

/* the rdaddr is 16 MiB before the loadaddr */
#define CONFIG_ENV_RDADDR	"rdaddr=0x81000000\0"

#define CONFIG_EXTRA_ENV_SETTINGS \
	CONFIG_COMMON_ENV_SETTINGS \
	CONFIG_ENV_RDADDR \
	"autoboot=" \
	"run commonargs; " \
	"setenv bootargs ${bootargs} " \
		"flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
		"rdinit=/sbin/init; " \
	"mmc dev ${mmcdev}; mmc rescan; " \
	"fatload mmc ${mmcdev} ${loadaddr} uImage; " \
	"fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
	"bootm ${loadaddr} ${rdaddr}\0"

#else /* CONFIG_FLASHCARD */

#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */

#define CONFIG_ENV_IS_IN_NAND

#define CONFIG_EXTRA_ENV_SETTINGS \
	CONFIG_COMMON_ENV_SETTINGS \
	"mmcargs=" \
		"run commonargs; " \
		"setenv bootargs ${bootargs} " \
		"root=/dev/mmcblk0p2 " \
		"rootwait " \
		"rw\0" \
	"nandargs=" \
		"run commonargs; " \
		"setenv bootargs ${bootargs} " \
		"root=ubi0:root " \
		"ubi.mtd=7 " \
		"rootfstype=ubifs " \
		"ro\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"loaduimage_ubi=ubi part ubi; " \
		"ubifsmount ubi:root; " \
		"ubifsload ${loadaddr} /boot/uImage\0" \
	"loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"run loaduimage_nand; " \
		"bootm ${loadaddr}\0" \
	"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
			"if run loadbootscript; then " \
				"run bootscript; " \
			"else " \
				"if run loaduimage; then " \
					"run mmcboot; " \
				"else run nandboot; " \
				"fi; " \
			"fi; " \
		"else run nandboot; fi\0"

#endif /* CONFIG_FLASHCARD */

/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_CMDLINE_EDITING		/* enable cmdline history */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */

/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0 + 0x00000000)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
					0x07000000) /* 112 MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0 + 0x02000000)

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			2 /* Divisor: 2^(PTV+1) => 8 */

/*  Physical Memory Map  */
#define CONFIG_NR_DRAM_BANKS		2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1			OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2			OMAP34XX_SDRC_CS1

/* NAND and environment organization  */
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
						CONFIG_SYS_INIT_RAM_SIZE - \
						GENERATED_GBL_DATA_SIZE)

/* SRAM config */
#define CONFIG_SYS_SRAM_START		0x40200000
#define CONFIG_SYS_SRAM_SIZE		0x10000

/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_NAND_SIMPLE

#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME        "u-boot.img"
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */

#define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_SPL_MAX_SIZE		(57 * 1024)	/* 7 KB for stack */

#define CONFIG_SPL_BSS_START_ADDR	0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
					 13, 14, 16, 17, 18, 19, 20, 21, 22, \
					 23, 24, 25, 26, 27, 28, 30, 31, 32, \
					 33, 34, 35, 36, 37, 38, 39, 40, 41, \
					 42, 44, 45, 46, 47, 48, 49, 50, 51, \
					 52, 53, 54, 55, 56}

#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	13
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW

#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x20000
#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x100000

#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000	/* 1 MB */

#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_SCRATCH	0x81000000
#endif /* __CONFIG_H */
Commit	Line	Data
8167af14 TW	1	/*
	2	* (C) Copyright 2006-2008
	3	* Texas Instruments.
	4	* Richard Woodruff <r-woodruff2@ti.com>
	5	* Syed Mohammed Khasim <x0khasim@ti.com>
	6	*
	7	* (C) Copyright 2012
	8	* Corscience GmbH & Co. KG
	9	* Thomas Weber <weber@corscience.de>
	10	*
	11	* Configuration settings for the Tricorder board.
	12	*
3765b3e7	13	* SPDX-License-Identifier: GPL-2.0+
8167af14 TW	14	*/
	15
	16	#ifndef __CONFIG_H
	17	#define __CONFIG_H
	18
3709844f AA	19	#define CONFIG_SYS_CACHELINE_SIZE 64
3709844f AA	20
8167af14	21	/* High Level Configuration Options */
44b0e47a	22	#define CONFIG_SYS_THUMB_BUILD
8167af14	23	#define CONFIG_OMAP /* in a TI OMAP core */
806d2792	24	#define CONFIG_OMAP_COMMON
c6f90e14 NM	25	/* Common ARM Erratas */
	26	#define CONFIG_ARM_ERRATA_454179
	27	#define CONFIG_ARM_ERRATA_430973
	28	#define CONFIG_ARM_ERRATA_621766
8167af14 TW	29
	30	#define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
	31	/*
	32	* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
	33	* 64 bytes before this address should be set aside for u-boot.img's
	34	* header. That is 0x800FFFC0--0x80100000 should not be used for any
	35	* other needs.
	36	*/
	37	#define CONFIG_SYS_TEXT_BASE 0x80100000
	38
	39	#define CONFIG_SDRC /* The chip has SDRC controller */
	40
	41	#include <asm/arch/cpu.h> /* get chip and board defs */
987ec585	42	#include <asm/arch/omap.h>
8167af14 TW	43
	44	/* Display CPU and Board information */
	45	#define CONFIG_DISPLAY_CPUINFO
	46	#define CONFIG_DISPLAY_BOARDINFO
	47
8ce1b82e	48	#define CONFIG_SILENT_CONSOLE
8ce1b82e	49
8167af14 TW	50	/* Clock Defines */
	51	#define V_OSCK 26000000 /* Clock output from T2 */
	52	#define V_SCLK (V_OSCK >> 1)
	53
8167af14 TW	54	#define CONFIG_MISC_INIT_R
	55
	56	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	57	#define CONFIG_SETUP_MEMORY_TAGS
	58	#define CONFIG_INITRD_TAG
	59	#define CONFIG_REVISION_TAG
	60
8167af14	61	/* Size of malloc() pool */
36f3aab2	62	#define CONFIG_SYS_MALLOC_LEN (1024*1024)
8167af14 TW	63
	64	/* Hardware drivers */
	65
89088058 AB	66	/* GPIO support */
	67	#define CONFIG_OMAP_GPIO
	68
23475344 AB	69	/* GPIO banks */
	70	#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */
	71
ad9f072c AB	72	/* LED support */
	73	#define CONFIG_STATUS_LED
	74	#define CONFIG_BOARD_SPECIFIC_LED
	75	#define CONFIG_CMD_LED /* LED command */
	76	#define STATUS_LED_BIT (1 << 0)
	77	#define STATUS_LED_STATE STATUS_LED_ON
	78	#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
	79	#define STATUS_LED_BIT1 (1 << 1)
	80	#define STATUS_LED_STATE1 STATUS_LED_ON
	81	#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
	82	#define STATUS_LED_BIT2 (1 << 2)
	83	#define STATUS_LED_STATE2 STATUS_LED_ON
	84	#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
	85
8167af14	86	/* NS16550 Configuration */
8167af14 TW	87	#define CONFIG_SYS_NS16550_SERIAL
	88	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	89	#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	90
	91	/* select serial console configuration */
	92	#define CONFIG_CONS_INDEX 3
	93	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	94	#define CONFIG_SERIAL3 3
	95	#define CONFIG_BAUDRATE 115200
	96	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	97	115200}
	98
	99	/* MMC */
	100	#define CONFIG_GENERIC_MMC
	101	#define CONFIG_MMC
	102	#define CONFIG_OMAP_HSMMC
	103	#define CONFIG_DOS_PARTITION
	104
	105	/* I2C */
6789e84e HS	106	#define CONFIG_SYS_I2C
	107	#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
	108	#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
	109	#define CONFIG_SYS_I2C_OMAP34XX
	110
459f1da8 AB	111
459f1da8 AB	112	/* EEPROM */
459f1da8 AB	113	#define CONFIG_CMD_EEPROM
	114	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	115	#define CONFIG_SYS_EEPROM_BUS_NUM 1
8167af14 TW	116
	117	/* TWL4030 */
	118	#define CONFIG_TWL4030_POWER
	119	#define CONFIG_TWL4030_LED
	120
	121	/* Board NAND Info */
	122	#define CONFIG_SYS_NO_FLASH /* no NOR flash */
	123	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
5c68f123 AB	124	#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
	125	#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \
	126	"128k(SPL)," \
	127	"1m(u-boot)," \
	128	"384k(u-boot-env1)," \
	129	"1152k(mtdoops)," \
	130	"384k(u-boot-env2)," \
	131	"5m(kernel)," \
	132	"2m(fdt)," \
	133	"-(ubi)"
8167af14 TW	134
	135	#define CONFIG_NAND_OMAP_GPMC
	136	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	137	/* to access nand */
	138	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	139	/* to access nand at */
	140	/* CS0 */
8167af14 TW	141	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
8167af14 TW	142	/* devices */
616cf60e	143	#define CONFIG_BCH
68ec9c85 PK	144	#define CONFIG_SYS_NAND_MAX_OOBFREE 2
68ec9c85 PK	145	#define CONFIG_SYS_NAND_MAX_ECCPOS 56
8167af14 TW	146
8167af14 TW	147	/* commands to include */
8167af14 TW	148	#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
	149	#define CONFIG_CMD_NAND /* NAND support */
	150	#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
36f3aab2 BW	151	#define CONFIG_CMD_UBI /* UBI commands */
	152	#define CONFIG_CMD_UBIFS /* UBIFS commands */
	153	#define CONFIG_LZO /* LZO is needed for UBIFS */
8167af14	154
8167af14 TW	155	#undef CONFIG_CMD_JFFS2 /* JFFS2 Support */
	156
	157	/* needed for ubi */
	158	#define CONFIG_RBTREE
	159	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
	160	#define CONFIG_MTD_PARTITIONS
	161
ec246452	162	/* Environment information (this is the common part) */
8167af14	163
8167af14	164
89088058 AB	165	/* hang() the board on panic() */
	166	#define CONFIG_PANIC_HANG
	167
ec246452 AB	168	/* environment placement (for NAND), is different for FLASHCARD but does not
	169	* harm there */
	170	#define CONFIG_ENV_OFFSET 0x120000 /* env start */
	171	#define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */
	172	#define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */
	173	#define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */
	174
0dff13a9 AB	175	/* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
	176	* value can not be used here! */
	177	#define CONFIG_LOADADDR 0x82000000
	178
ec246452	179	#define CONFIG_COMMON_ENV_SETTINGS \
8167af14	180	"console=ttyO2,115200n8\0" \
5605979a	181	"mmcdev=0\0" \
83976f1d	182	"vram=3M\0" \
8167af14	183	"defaultdisplay=lcd\0" \
ec246452	184	"kernelopts=mtdoops.mtddev=3\0" \
deac6d66 AB	185	"mtdparts=" MTDPARTS_DEFAULT "\0" \
deac6d66 AB	186	"mtdids=" MTDIDS_DEFAULT "\0" \
8167af14 TW	187	"commonargs=" \
8167af14 TW	188	"setenv bootargs console=${console} " \
5c68f123	189	"${mtdparts} " \
ec246452 AB	190	"${kernelopts} " \
ec246452 AB	191	"vt.global_cursor_default=0 " \
8167af14	192	"vram=${vram} " \
ec246452 AB	193	"omapdss.def_disp=${defaultdisplay}\0"
	194
	195	#define CONFIG_BOOTCOMMAND "run autoboot"
	196
	197	/* specific environment settings for different use cases
	198	* FLASHCARD: used to run a rdimage from sdcard to program the device
	199	* 'NORMAL': used to boot kernel from sdcard, nand, ...
	200	*
	201	* The main aim for the FLASHCARD skin is to have an embedded environment
	202	* which will not be influenced by any data already on the device.
	203	*/
	204	#ifdef CONFIG_FLASHCARD
	205
	206	#define CONFIG_ENV_IS_NOWHERE
	207
	208	/* the rdaddr is 16 MiB before the loadaddr */
	209	#define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0"
	210
	211	#define CONFIG_EXTRA_ENV_SETTINGS \
	212	CONFIG_COMMON_ENV_SETTINGS \
	213	CONFIG_ENV_RDADDR \
	214	"autoboot=" \
ec246452 AB	215	"run commonargs; " \
	216	"setenv bootargs ${bootargs} " \
	217	"flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
	218	"rdinit=/sbin/init; " \
	219	"mmc dev ${mmcdev}; mmc rescan; " \
	220	"fatload mmc ${mmcdev} ${loadaddr} uImage; " \
	221	"fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
	222	"bootm ${loadaddr} ${rdaddr}\0"
	223
	224	#else /* CONFIG_FLASHCARD */
	225
	226	#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
	227
	228	#define CONFIG_ENV_IS_IN_NAND
	229
	230	#define CONFIG_EXTRA_ENV_SETTINGS \
	231	CONFIG_COMMON_ENV_SETTINGS \
8167af14 TW	232	"mmcargs=" \
	233	"run commonargs; " \
	234	"setenv bootargs ${bootargs} " \
	235	"root=/dev/mmcblk0p2 " \
ec246452 AB	236	"rootwait " \
ec246452 AB	237	"rw\0" \
8167af14 TW	238	"nandargs=" \
	239	"run commonargs; " \
	240	"setenv bootargs ${bootargs} " \
008ec950	241	"root=ubi0:root " \
5c68f123	242	"ubi.mtd=7 " \
8167af14	243	"rootfstype=ubifs " \
ec246452	244	"ro\0" \
5605979a	245	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
8167af14 TW	246	"bootscript=echo Running bootscript from mmc ...; " \
8167af14 TW	247	"source ${loadaddr}\0" \
5605979a	248	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
8167af14 TW	249	"mmcboot=echo Booting from mmc ...; " \
	250	"run mmcargs; " \
	251	"bootm ${loadaddr}\0" \
deac6d66	252	"loaduimage_ubi=ubi part ubi; " \
949a7710	253	"ubifsmount ubi:root; " \
008ec950	254	"ubifsload ${loadaddr} /boot/uImage\0" \
eadbdf9e	255	"loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
8167af14 TW	256	"nandboot=echo Booting from nand ...; " \
8167af14 TW	257	"run nandargs; " \
eadbdf9e	258	"run loaduimage_nand; " \
8167af14	259	"bootm ${loadaddr}\0" \
66968110	260	"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
8167af14 TW	261	"if run loadbootscript; then " \
	262	"run bootscript; " \
	263	"else " \
	264	"if run loaduimage; then " \
	265	"run mmcboot; " \
	266	"else run nandboot; " \
	267	"fi; " \
	268	"fi; " \
	269	"else run nandboot; fi\0"
	270
ec246452	271	#endif /* CONFIG_FLASHCARD */
8167af14 TW	272
	273	/* Miscellaneous configurable options */
	274	#define CONFIG_SYS_LONGHELP /* undef to save memory */
ec246452	275	#define CONFIG_CMDLINE_EDITING /* enable cmdline history */
8167af14	276	#define CONFIG_AUTO_COMPLETE
8167af14 TW	277	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	278	/* Print Buffer Size */
	279	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	280	sizeof(CONFIG_SYS_PROMPT) + 16)
	281	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	282
	283	/* Boot Argument Buffer Size */
	284	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	285
69df69d1	286	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000)
8167af14	287	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
69df69d1	288	0x07000000) /* 112 MB */
8167af14 TW	289
	290	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
	291
	292	/*
	293	* OMAP3 has 12 GP timers, they can be driven by the system clock
	294	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	295	* This rate is divided by a local divisor.
	296	*/
	297	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
	298	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
8167af14	299
8167af14 TW	300	/* Physical Memory Map */
	301	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	302	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
8167af14 TW	303	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	304
	305	/* NAND and environment organization */
8167af14 TW	306	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
8167af14 TW	307
8167af14 TW	308	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	309	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	310	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	311	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	312	CONFIG_SYS_INIT_RAM_SIZE - \
	313	GENERATED_GBL_DATA_SIZE)
	314
	315	/* SRAM config */
	316	#define CONFIG_SYS_SRAM_START 0x40200000
	317	#define CONFIG_SYS_SRAM_SIZE 0x10000
	318
	319	/* Defines for SPL */
47f7bcae	320	#define CONFIG_SPL_FRAMEWORK
8167af14 TW	321	#define CONFIG_SPL_NAND_SIMPLE
8167af14 TW	322
49175c49	323	#define CONFIG_SPL_BOARD_INIT
89088058	324	#define CONFIG_SPL_GPIO_SUPPORT
8167af14 TW	325	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	326	#define CONFIG_SPL_LIBDISK_SUPPORT
	327	#define CONFIG_SPL_I2C_SUPPORT
	328	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	329	#define CONFIG_SPL_SERIAL_SUPPORT
	330	#define CONFIG_SPL_POWER_SUPPORT
	331	#define CONFIG_SPL_NAND_SUPPORT
6f2f01b9 SW	332	#define CONFIG_SPL_NAND_BASE
	333	#define CONFIG_SPL_NAND_DRIVERS
	334	#define CONFIG_SPL_NAND_ECC
8167af14 TW	335	#define CONFIG_SPL_MMC_SUPPORT
	336	#define CONFIG_SPL_FAT_SUPPORT
	337	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
205b4f33	338	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
e2ccdf89	339	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
8167af14 TW	340	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
	341
	342	#define CONFIG_SPL_TEXT_BASE 0x40200000 /CONFIG_SYS_SRAM_START/
01782965	343	#define CONFIG_SPL_MAX_SIZE (57 * 1024) /* 7 KB for stack */
8167af14 TW	344
	345	#define CONFIG_SPL_BSS_START_ADDR 0x80000000 /CONFIG_SYS_SDRAM_BASE/
	346	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	347
	348	/* NAND boot config */
	349	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	350	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	351	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	352	#define CONFIG_SYS_NAND_OOBSIZE 64
	353	#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
	354	#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
1b82491e AB	355	#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
	356	13, 14, 16, 17, 18, 19, 20, 21, 22, \
	357	23, 24, 25, 26, 27, 28, 30, 31, 32, \
	358	33, 34, 35, 36, 37, 38, 39, 40, 41, \
	359	42, 44, 45, 46, 47, 48, 49, 50, 51, \
	360	52, 53, 54, 55, 56}
8167af14 TW	361
8167af14 TW	362	#define CONFIG_SYS_NAND_ECCSIZE 512
616cf60e	363	#define CONFIG_SYS_NAND_ECCBYTES 13
3f719069	364	#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
8167af14	365
8167af14 TW	366	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
8167af14 TW	367
5c68f123 AB	368	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
5c68f123 AB	369	#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000
8167af14 TW	370
	371	#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
	372	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
	373
69df69d1 TW	374	#define CONFIG_SYS_ALT_MEMTEST
69df69d1 TW	375	#define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000
8167af14	376	#endif /* __CONFIG_H */