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8167af14 TW |
1 | /* |
2 | * (C) Copyright 2006-2008 | |
3 | * Texas Instruments. | |
4 | * Richard Woodruff <r-woodruff2@ti.com> | |
5 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
6 | * | |
7 | * (C) Copyright 2012 | |
8 | * Corscience GmbH & Co. KG | |
9 | * Thomas Weber <weber@corscience.de> | |
10 | * | |
11 | * Configuration settings for the Tricorder board. | |
12 | * | |
3765b3e7 | 13 | * SPDX-License-Identifier: GPL-2.0+ |
8167af14 TW |
14 | */ |
15 | ||
16 | #ifndef __CONFIG_H | |
17 | #define __CONFIG_H | |
18 | ||
94ba26f2 | 19 | #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER |
8167af14 TW |
20 | /* |
21 | * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM | |
22 | * 64 bytes before this address should be set aside for u-boot.img's | |
23 | * header. That is 0x800FFFC0--0x80100000 should not be used for any | |
24 | * other needs. | |
25 | */ | |
8167af14 | 26 | |
8167af14 | 27 | #include <asm/arch/cpu.h> /* get chip and board defs */ |
987ec585 | 28 | #include <asm/arch/omap.h> |
8167af14 | 29 | |
8167af14 TW |
30 | /* Clock Defines */ |
31 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
32 | #define V_SCLK (V_OSCK >> 1) | |
33 | ||
8167af14 TW |
34 | #define CONFIG_MISC_INIT_R |
35 | ||
36 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
37 | #define CONFIG_SETUP_MEMORY_TAGS | |
38 | #define CONFIG_INITRD_TAG | |
39 | #define CONFIG_REVISION_TAG | |
40 | ||
8167af14 | 41 | /* Size of malloc() pool */ |
36f3aab2 | 42 | #define CONFIG_SYS_MALLOC_LEN (1024*1024) |
8167af14 TW |
43 | |
44 | /* Hardware drivers */ | |
45 | ||
46 | /* NS16550 Configuration */ | |
8167af14 TW |
47 | #define CONFIG_SYS_NS16550_SERIAL |
48 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
49 | #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
50 | ||
51 | /* select serial console configuration */ | |
52 | #define CONFIG_CONS_INDEX 3 | |
53 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 | |
54 | #define CONFIG_SERIAL3 3 | |
8167af14 TW |
55 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ |
56 | 115200} | |
57 | ||
8167af14 | 58 | /* I2C */ |
6789e84e | 59 | #define CONFIG_SYS_I2C |
6789e84e | 60 | |
459f1da8 AB |
61 | |
62 | /* EEPROM */ | |
459f1da8 AB |
63 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
64 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
8167af14 TW |
65 | |
66 | /* TWL4030 */ | |
8167af14 TW |
67 | #define CONFIG_TWL4030_LED |
68 | ||
69 | /* Board NAND Info */ | |
8167af14 | 70 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
8167af14 | 71 | |
8167af14 TW |
72 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ |
73 | /* to access nand */ | |
74 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
75 | /* to access nand at */ | |
76 | /* CS0 */ | |
8167af14 TW |
77 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ |
78 | /* devices */ | |
68ec9c85 PK |
79 | #define CONFIG_SYS_NAND_MAX_OOBFREE 2 |
80 | #define CONFIG_SYS_NAND_MAX_ECCPOS 56 | |
8167af14 | 81 | |
8167af14 | 82 | /* needed for ubi */ |
8167af14 TW |
83 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
84 | #define CONFIG_MTD_PARTITIONS | |
85 | ||
ec246452 | 86 | /* Environment information (this is the common part) */ |
8167af14 | 87 | |
8167af14 | 88 | |
89088058 | 89 | /* hang() the board on panic() */ |
89088058 | 90 | |
ec246452 AB |
91 | /* environment placement (for NAND), is different for FLASHCARD but does not |
92 | * harm there */ | |
93 | #define CONFIG_ENV_OFFSET 0x120000 /* env start */ | |
94 | #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */ | |
95 | #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */ | |
96 | #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */ | |
97 | ||
0dff13a9 AB |
98 | /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend |
99 | * value can not be used here! */ | |
100 | #define CONFIG_LOADADDR 0x82000000 | |
101 | ||
ec246452 | 102 | #define CONFIG_COMMON_ENV_SETTINGS \ |
8167af14 | 103 | "console=ttyO2,115200n8\0" \ |
5605979a | 104 | "mmcdev=0\0" \ |
83976f1d | 105 | "vram=3M\0" \ |
8167af14 | 106 | "defaultdisplay=lcd\0" \ |
ec246452 | 107 | "kernelopts=mtdoops.mtddev=3\0" \ |
43ede0bc TR |
108 | "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ |
109 | "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ | |
8167af14 TW |
110 | "commonargs=" \ |
111 | "setenv bootargs console=${console} " \ | |
5c68f123 | 112 | "${mtdparts} " \ |
ec246452 AB |
113 | "${kernelopts} " \ |
114 | "vt.global_cursor_default=0 " \ | |
8167af14 | 115 | "vram=${vram} " \ |
ec246452 AB |
116 | "omapdss.def_disp=${defaultdisplay}\0" |
117 | ||
118 | #define CONFIG_BOOTCOMMAND "run autoboot" | |
119 | ||
120 | /* specific environment settings for different use cases | |
121 | * FLASHCARD: used to run a rdimage from sdcard to program the device | |
122 | * 'NORMAL': used to boot kernel from sdcard, nand, ... | |
123 | * | |
124 | * The main aim for the FLASHCARD skin is to have an embedded environment | |
125 | * which will not be influenced by any data already on the device. | |
126 | */ | |
127 | #ifdef CONFIG_FLASHCARD | |
ec246452 AB |
128 | /* the rdaddr is 16 MiB before the loadaddr */ |
129 | #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0" | |
130 | ||
131 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
132 | CONFIG_COMMON_ENV_SETTINGS \ | |
133 | CONFIG_ENV_RDADDR \ | |
134 | "autoboot=" \ | |
ec246452 AB |
135 | "run commonargs; " \ |
136 | "setenv bootargs ${bootargs} " \ | |
137 | "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \ | |
138 | "rdinit=/sbin/init; " \ | |
139 | "mmc dev ${mmcdev}; mmc rescan; " \ | |
140 | "fatload mmc ${mmcdev} ${loadaddr} uImage; " \ | |
141 | "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \ | |
142 | "bootm ${loadaddr} ${rdaddr}\0" | |
143 | ||
144 | #else /* CONFIG_FLASHCARD */ | |
145 | ||
146 | #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ | |
147 | ||
ec246452 AB |
148 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
149 | CONFIG_COMMON_ENV_SETTINGS \ | |
8167af14 TW |
150 | "mmcargs=" \ |
151 | "run commonargs; " \ | |
152 | "setenv bootargs ${bootargs} " \ | |
153 | "root=/dev/mmcblk0p2 " \ | |
ec246452 AB |
154 | "rootwait " \ |
155 | "rw\0" \ | |
8167af14 TW |
156 | "nandargs=" \ |
157 | "run commonargs; " \ | |
158 | "setenv bootargs ${bootargs} " \ | |
008ec950 | 159 | "root=ubi0:root " \ |
5c68f123 | 160 | "ubi.mtd=7 " \ |
8167af14 | 161 | "rootfstype=ubifs " \ |
ec246452 | 162 | "ro\0" \ |
5605979a | 163 | "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ |
8167af14 TW |
164 | "bootscript=echo Running bootscript from mmc ...; " \ |
165 | "source ${loadaddr}\0" \ | |
5605979a | 166 | "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ |
8167af14 TW |
167 | "mmcboot=echo Booting from mmc ...; " \ |
168 | "run mmcargs; " \ | |
169 | "bootm ${loadaddr}\0" \ | |
deac6d66 | 170 | "loaduimage_ubi=ubi part ubi; " \ |
949a7710 | 171 | "ubifsmount ubi:root; " \ |
008ec950 | 172 | "ubifsload ${loadaddr} /boot/uImage\0" \ |
eadbdf9e | 173 | "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \ |
8167af14 TW |
174 | "nandboot=echo Booting from nand ...; " \ |
175 | "run nandargs; " \ | |
eadbdf9e | 176 | "run loaduimage_nand; " \ |
8167af14 | 177 | "bootm ${loadaddr}\0" \ |
66968110 | 178 | "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ |
8167af14 TW |
179 | "if run loadbootscript; then " \ |
180 | "run bootscript; " \ | |
181 | "else " \ | |
182 | "if run loaduimage; then " \ | |
183 | "run mmcboot; " \ | |
184 | "else run nandboot; " \ | |
185 | "fi; " \ | |
186 | "fi; " \ | |
187 | "else run nandboot; fi\0" | |
188 | ||
ec246452 | 189 | #endif /* CONFIG_FLASHCARD */ |
8167af14 TW |
190 | |
191 | /* Miscellaneous configurable options */ | |
192 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
ec246452 | 193 | #define CONFIG_CMDLINE_EDITING /* enable cmdline history */ |
8167af14 | 194 | #define CONFIG_AUTO_COMPLETE |
8167af14 | 195 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
8167af14 | 196 | |
69df69d1 | 197 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000) |
8167af14 | 198 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ |
69df69d1 | 199 | 0x07000000) /* 112 MB */ |
8167af14 TW |
200 | |
201 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) | |
202 | ||
203 | /* | |
204 | * OMAP3 has 12 GP timers, they can be driven by the system clock | |
205 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
206 | * This rate is divided by a local divisor. | |
207 | */ | |
208 | #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) | |
209 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
8167af14 | 210 | |
8167af14 TW |
211 | /* Physical Memory Map */ |
212 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ | |
213 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
8167af14 TW |
214 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 |
215 | ||
216 | /* NAND and environment organization */ | |
8167af14 TW |
217 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ |
218 | ||
8167af14 TW |
219 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
220 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 | |
221 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
222 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
223 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
224 | GENERATED_GBL_DATA_SIZE) | |
225 | ||
226 | /* SRAM config */ | |
227 | #define CONFIG_SYS_SRAM_START 0x40200000 | |
228 | #define CONFIG_SYS_SRAM_SIZE 0x10000 | |
229 | ||
230 | /* Defines for SPL */ | |
8167af14 | 231 | |
6f2f01b9 SW |
232 | #define CONFIG_SPL_NAND_BASE |
233 | #define CONFIG_SPL_NAND_DRIVERS | |
234 | #define CONFIG_SPL_NAND_ECC | |
205b4f33 | 235 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
e2ccdf89 | 236 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
8167af14 TW |
237 | |
238 | #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ | |
fa2f81b0 TR |
239 | #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ |
240 | CONFIG_SPL_TEXT_BASE) | |
8167af14 TW |
241 | |
242 | #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ | |
243 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
244 | ||
245 | /* NAND boot config */ | |
246 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
247 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
248 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
249 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
250 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) | |
251 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS | |
1b82491e AB |
252 | #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ |
253 | 13, 14, 16, 17, 18, 19, 20, 21, 22, \ | |
254 | 23, 24, 25, 26, 27, 28, 30, 31, 32, \ | |
255 | 33, 34, 35, 36, 37, 38, 39, 40, 41, \ | |
256 | 42, 44, 45, 46, 47, 48, 49, 50, 51, \ | |
257 | 52, 53, 54, 55, 56} | |
8167af14 TW |
258 | |
259 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
616cf60e | 260 | #define CONFIG_SYS_NAND_ECCBYTES 13 |
3f719069 | 261 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |
8167af14 | 262 | |
8167af14 TW |
263 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE |
264 | ||
5c68f123 AB |
265 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 |
266 | #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000 | |
8167af14 TW |
267 | |
268 | #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 | |
269 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ | |
270 | ||
69df69d1 TW |
271 | #define CONFIG_SYS_ALT_MEMTEST |
272 | #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000 | |
8167af14 | 273 | #endif /* __CONFIG_H */ |