[thirdparty/u-boot.git] / include / configs / tricorder.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2006-2008
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <x0khasim@ti.com>
 *
 * (C) Copyright 2012
 * Corscience GmbH & Co. KG
 * Thomas Weber <weber@corscience.de>
 *
 * Configuration settings for the Tricorder board.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_MACH_TYPE		MACH_TYPE_TRICORDER
/*
 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 * 64 bytes before this address should be set aside for u-boot.img's
 * header. That is 0x800FFFC0--0x80100000 should not be used for any
 * other needs.
 */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap.h>

/* Clock Defines */
#define V_OSCK				26000000 /* Clock output from T2 */
#define V_SCLK				(V_OSCK >> 1)

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(1024*1024)

/* Hardware drivers */

/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		48000000 /* 48MHz (APLL96/2) */

/* select serial console configuration */
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}

/* I2C */
#define CONFIG_SYS_I2C
 

/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
#define CONFIG_SYS_EEPROM_BUS_NUM	1

/* TWL4030 */

/* Board NAND Info */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
							/* devices */
#define CONFIG_SYS_NAND_MAX_OOBFREE	2
#define CONFIG_SYS_NAND_MAX_ECCPOS	56

/* needed for ubi */

/* Environment information (this is the common part) */


/* hang() the board on panic() */

/* environment placement (for NAND), is different for FLASHCARD but does not
 * harm there */
#define CONFIG_ENV_RANGE		(384 << 10) /* allow badblocks in env */

/* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
 * value can not be used here! */
#define CONFIG_LOADADDR		0x82000000

#define CONFIG_COMMON_ENV_SETTINGS \
	"console=ttyO2,115200n8\0" \
	"mmcdev=0\0" \
	"vram=3M\0" \
	"defaultdisplay=lcd\0" \
	"kernelopts=mtdoops.mtddev=3\0" \
	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
	"commonargs=" \
		"setenv bootargs console=${console} " \
		"${mtdparts} " \
		"${kernelopts} " \
		"vt.global_cursor_default=0 " \
		"vram=${vram} " \
		"omapdss.def_disp=${defaultdisplay}\0"

#define CONFIG_BOOTCOMMAND "run autoboot"

/* specific environment settings for different use cases
 * FLASHCARD: used to run a rdimage from sdcard to program the device
 * 'NORMAL': used to boot kernel from sdcard, nand, ...
 *
 * The main aim for the FLASHCARD skin is to have an embedded environment
 * which will not be influenced by any data already on the device.
 */
#ifdef CONFIG_FLASHCARD
/* the rdaddr is 16 MiB before the loadaddr */
#define CONFIG_ENV_RDADDR	"rdaddr=0x81000000\0"

#define CONFIG_EXTRA_ENV_SETTINGS \
	CONFIG_COMMON_ENV_SETTINGS \
	CONFIG_ENV_RDADDR \
	"autoboot=" \
	"run commonargs; " \
	"setenv bootargs ${bootargs} " \
		"flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
		"rdinit=/sbin/init; " \
	"mmc dev ${mmcdev}; mmc rescan; " \
	"fatload mmc ${mmcdev} ${loadaddr} uImage; " \
	"fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
	"bootm ${loadaddr} ${rdaddr}\0"

#else /* CONFIG_FLASHCARD */

#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */

#define CONFIG_EXTRA_ENV_SETTINGS \
	CONFIG_COMMON_ENV_SETTINGS \
	"mmcargs=" \
		"run commonargs; " \
		"setenv bootargs ${bootargs} " \
		"root=/dev/mmcblk0p2 " \
		"rootwait " \
		"rw\0" \
	"nandargs=" \
		"run commonargs; " \
		"setenv bootargs ${bootargs} " \
		"root=ubi0:root " \
		"ubi.mtd=7 " \
		"rootfstype=ubifs " \
		"ro\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"loaduimage_ubi=ubi part ubi; " \
		"ubifsmount ubi:root; " \
		"ubifsload ${loadaddr} /boot/uImage\0" \
	"loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"run loaduimage_nand; " \
		"bootm ${loadaddr}\0" \
	"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
			"if run loadbootscript; then " \
				"run bootscript; " \
			"else " \
				"if run loaduimage; then " \
					"run mmcboot; " \
				"else run nandboot; " \
				"fi; " \
			"fi; " \
		"else run nandboot; fi\0"

#endif /* CONFIG_FLASHCARD */

/* Miscellaneous configurable options */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */

#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0 + 0x00000000)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
					0x07000000) /* 112 MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0 + 0x02000000)

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			2 /* Divisor: 2^(PTV+1) => 8 */

/*  Physical Memory Map  */
#define PHYS_SDRAM_1			OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2			OMAP34XX_SDRC_CS1

/* NAND and environment organization  */
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
						CONFIG_SYS_INIT_RAM_SIZE - \
						GENERATED_GBL_DATA_SIZE)

/* SRAM config */
#define CONFIG_SYS_SRAM_START		0x40200000
#define CONFIG_SYS_SRAM_SIZE		0x10000

/* Defines for SPL */

#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME        "u-boot.img"
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1

#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
					 CONFIG_SPL_TEXT_BASE)

#define CONFIG_SPL_BSS_START_ADDR	0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
					 13, 14, 16, 17, 18, 19, 20, 21, 22, \
					 23, 24, 25, 26, 27, 28, 30, 31, 32, \
					 33, 34, 35, 36, 37, 38, 39, 40, 41, \
					 42, 44, 45, 46, 47, 48, 49, 50, 51, \
					 52, 53, 54, 55, 56}

#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	13
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW

#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x20000
#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x100000

#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000	/* 1 MB */

#define CONFIG_SYS_MEMTEST_SCRATCH	0x81000000
#endif /* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
8167af14 TW	2	/*
	3	* (C) Copyright 2006-2008
	4	* Texas Instruments.
	5	* Richard Woodruff <r-woodruff2@ti.com>
	6	* Syed Mohammed Khasim <x0khasim@ti.com>
	7	*
	8	* (C) Copyright 2012
	9	* Corscience GmbH & Co. KG
	10	* Thomas Weber <weber@corscience.de>
	11	*
	12	* Configuration settings for the Tricorder board.
8167af14 TW	13	*/
	14
	15	#ifndef __CONFIG_H
	16	#define __CONFIG_H
	17
94ba26f2	18	#define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
8167af14 TW	19	/*
	20	* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
	21	* 64 bytes before this address should be set aside for u-boot.img's
	22	* header. That is 0x800FFFC0--0x80100000 should not be used for any
	23	* other needs.
	24	*/
8167af14	25
8167af14	26	#include <asm/arch/cpu.h> /* get chip and board defs */
987ec585	27	#include <asm/arch/omap.h>
8167af14	28
8167af14 TW	29	/* Clock Defines */
	30	#define V_OSCK 26000000 /* Clock output from T2 */
	31	#define V_SCLK (V_OSCK >> 1)
	32
8167af14 TW	33	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	34	#define CONFIG_SETUP_MEMORY_TAGS
	35	#define CONFIG_INITRD_TAG
	36	#define CONFIG_REVISION_TAG
	37
8167af14	38	/* Size of malloc() pool */
36f3aab2	39	#define CONFIG_SYS_MALLOC_LEN (1024*1024)
8167af14 TW	40
	41	/* Hardware drivers */
	42
	43	/* NS16550 Configuration */
8167af14 TW	44	#define CONFIG_SYS_NS16550_SERIAL
	45	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	46	#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	47
	48	/* select serial console configuration */
8167af14	49	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
8167af14 TW	50	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	51	115200}
	52
8167af14	53	/* I2C */
6789e84e	54	#define CONFIG_SYS_I2C
6789e84e	55
459f1da8 AB	56
459f1da8 AB	57	/* EEPROM */
459f1da8 AB	58	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
459f1da8 AB	59	#define CONFIG_SYS_EEPROM_BUS_NUM 1
8167af14 TW	60
8167af14 TW	61	/* TWL4030 */
8167af14 TW	62
8167af14 TW	63	/* Board NAND Info */
8167af14 TW	64	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	65	/* to access nand at */
	66	/* CS0 */
8167af14 TW	67	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
8167af14 TW	68	/* devices */
68ec9c85 PK	69	#define CONFIG_SYS_NAND_MAX_OOBFREE 2
68ec9c85 PK	70	#define CONFIG_SYS_NAND_MAX_ECCPOS 56
8167af14	71
8167af14	72	/* needed for ubi */
8167af14	73
ec246452	74	/* Environment information (this is the common part) */
8167af14	75
8167af14	76
89088058	77	/* hang() the board on panic() */
89088058	78
ec246452 AB	79	/* environment placement (for NAND), is different for FLASHCARD but does not
ec246452 AB	80	* harm there */
ec246452 AB	81	#define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */
ec246452 AB	82
0dff13a9 AB	83	/* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
	84	* value can not be used here! */
	85	#define CONFIG_LOADADDR 0x82000000
	86
ec246452	87	#define CONFIG_COMMON_ENV_SETTINGS \
8167af14	88	"console=ttyO2,115200n8\0" \
5605979a	89	"mmcdev=0\0" \
83976f1d	90	"vram=3M\0" \
8167af14	91	"defaultdisplay=lcd\0" \
ec246452	92	"kernelopts=mtdoops.mtddev=3\0" \
43ede0bc TR	93	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
43ede0bc TR	94	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
8167af14 TW	95	"commonargs=" \
8167af14 TW	96	"setenv bootargs console=${console} " \
5c68f123	97	"${mtdparts} " \
ec246452 AB	98	"${kernelopts} " \
ec246452 AB	99	"vt.global_cursor_default=0 " \
8167af14	100	"vram=${vram} " \
ec246452 AB	101	"omapdss.def_disp=${defaultdisplay}\0"
	102
	103	#define CONFIG_BOOTCOMMAND "run autoboot"
	104
	105	/* specific environment settings for different use cases
	106	* FLASHCARD: used to run a rdimage from sdcard to program the device
	107	* 'NORMAL': used to boot kernel from sdcard, nand, ...
	108	*
	109	* The main aim for the FLASHCARD skin is to have an embedded environment
	110	* which will not be influenced by any data already on the device.
	111	*/
	112	#ifdef CONFIG_FLASHCARD
ec246452 AB	113	/* the rdaddr is 16 MiB before the loadaddr */
	114	#define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0"
	115
	116	#define CONFIG_EXTRA_ENV_SETTINGS \
	117	CONFIG_COMMON_ENV_SETTINGS \
	118	CONFIG_ENV_RDADDR \
	119	"autoboot=" \
ec246452 AB	120	"run commonargs; " \
	121	"setenv bootargs ${bootargs} " \
	122	"flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
	123	"rdinit=/sbin/init; " \
	124	"mmc dev ${mmcdev}; mmc rescan; " \
	125	"fatload mmc ${mmcdev} ${loadaddr} uImage; " \
	126	"fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
	127	"bootm ${loadaddr} ${rdaddr}\0"
	128
	129	#else /* CONFIG_FLASHCARD */
	130
	131	#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
	132
ec246452 AB	133	#define CONFIG_EXTRA_ENV_SETTINGS \
ec246452 AB	134	CONFIG_COMMON_ENV_SETTINGS \
8167af14 TW	135	"mmcargs=" \
	136	"run commonargs; " \
	137	"setenv bootargs ${bootargs} " \
	138	"root=/dev/mmcblk0p2 " \
ec246452 AB	139	"rootwait " \
ec246452 AB	140	"rw\0" \
8167af14 TW	141	"nandargs=" \
	142	"run commonargs; " \
	143	"setenv bootargs ${bootargs} " \
008ec950	144	"root=ubi0:root " \
5c68f123	145	"ubi.mtd=7 " \
8167af14	146	"rootfstype=ubifs " \
ec246452	147	"ro\0" \
5605979a	148	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
8167af14 TW	149	"bootscript=echo Running bootscript from mmc ...; " \
8167af14 TW	150	"source ${loadaddr}\0" \
5605979a	151	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
8167af14 TW	152	"mmcboot=echo Booting from mmc ...; " \
	153	"run mmcargs; " \
	154	"bootm ${loadaddr}\0" \
deac6d66	155	"loaduimage_ubi=ubi part ubi; " \
949a7710	156	"ubifsmount ubi:root; " \
008ec950	157	"ubifsload ${loadaddr} /boot/uImage\0" \
eadbdf9e	158	"loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
8167af14 TW	159	"nandboot=echo Booting from nand ...; " \
8167af14 TW	160	"run nandargs; " \
eadbdf9e	161	"run loaduimage_nand; " \
8167af14	162	"bootm ${loadaddr}\0" \
66968110	163	"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
8167af14 TW	164	"if run loadbootscript; then " \
	165	"run bootscript; " \
	166	"else " \
	167	"if run loaduimage; then " \
	168	"run mmcboot; " \
	169	"else run nandboot; " \
	170	"fi; " \
	171	"fi; " \
	172	"else run nandboot; fi\0"
	173
ec246452	174	#endif /* CONFIG_FLASHCARD */
8167af14 TW	175
8167af14 TW	176	/* Miscellaneous configurable options */
8167af14	177	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
8167af14	178
69df69d1	179	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000)
8167af14	180	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
69df69d1	181	0x07000000) /* 112 MB */
8167af14 TW	182
	183	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
	184
	185	/*
	186	* OMAP3 has 12 GP timers, they can be driven by the system clock
	187	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	188	* This rate is divided by a local divisor.
	189	*/
	190	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
	191	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
8167af14	192
8167af14	193	/* Physical Memory Map */
8167af14	194	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
8167af14 TW	195	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	196
	197	/* NAND and environment organization */
8167af14 TW	198	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
8167af14 TW	199
8167af14 TW	200	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	201	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	202	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	203	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	204	CONFIG_SYS_INIT_RAM_SIZE - \
	205	GENERATED_GBL_DATA_SIZE)
	206
	207	/* SRAM config */
	208	#define CONFIG_SYS_SRAM_START 0x40200000
	209	#define CONFIG_SYS_SRAM_SIZE 0x10000
	210
	211	/* Defines for SPL */
8167af14	212
6f2f01b9 SW	213	#define CONFIG_SPL_NAND_BASE
	214	#define CONFIG_SPL_NAND_DRIVERS
	215	#define CONFIG_SPL_NAND_ECC
205b4f33	216	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
e2ccdf89	217	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
8167af14	218
fa2f81b0 TR	219	#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
fa2f81b0 TR	220	CONFIG_SPL_TEXT_BASE)
8167af14 TW	221
	222	#define CONFIG_SPL_BSS_START_ADDR 0x80000000 /CONFIG_SYS_SDRAM_BASE/
	223	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	224
	225	/* NAND boot config */
	226	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	227	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	228	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	229	#define CONFIG_SYS_NAND_OOBSIZE 64
	230	#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
	231	#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
1b82491e AB	232	#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
	233	13, 14, 16, 17, 18, 19, 20, 21, 22, \
	234	23, 24, 25, 26, 27, 28, 30, 31, 32, \
	235	33, 34, 35, 36, 37, 38, 39, 40, 41, \
	236	42, 44, 45, 46, 47, 48, 49, 50, 51, \
	237	52, 53, 54, 55, 56}
8167af14 TW	238
8167af14 TW	239	#define CONFIG_SYS_NAND_ECCSIZE 512
616cf60e	240	#define CONFIG_SYS_NAND_ECCBYTES 13
3f719069	241	#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
8167af14	242
8167af14 TW	243	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
8167af14 TW	244
5c68f123 AB	245	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
5c68f123 AB	246	#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000
8167af14 TW	247
	248	#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
	249	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
	250
69df69d1	251	#define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000
8167af14	252	#endif /* __CONFIG_H */