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5e5803e1 SB |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Stefano Babic, DENX Gmbh, sbabic@denx.de | |
4 | * | |
5 | * (C) Copyright 2004 | |
6 | * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net | |
7 | * | |
8 | * (C) Copyright 2002 | |
9 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net | |
10 | * | |
11 | * (C) Copyright 2002 | |
12 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
13 | * Marius Groeger <mgroeger@sysgo.de> | |
14 | * | |
15 | * Configuation settings for the LUBBOCK board. | |
16 | * | |
3765b3e7 | 17 | * SPDX-License-Identifier: GPL-2.0+ |
5e5803e1 SB |
18 | */ |
19 | ||
20 | #ifndef __CONFIG_H | |
21 | #define __CONFIG_H | |
22 | ||
23 | /* | |
24 | * High Level Configuration Options | |
25 | * (easy to change) | |
26 | */ | |
abc20aba | 27 | #define CONFIG_CPU_PXA27X 1 /* This is an PXA27x CPU */ |
5e5803e1 | 28 | |
5e5803e1 | 29 | #define CONFIG_MMC 1 |
9660e442 | 30 | #define CONFIG_BOARD_LATE_INIT |
cc72ac66 | 31 | #define CONFIG_SYS_TEXT_BASE 0x0 |
5e5803e1 | 32 | |
b3acb6cd | 33 | /* we will never enable dcache, because we have to setup MMU first */ |
e47f2db5 | 34 | #define CONFIG_SYS_DCACHE_OFF |
b3acb6cd | 35 | |
5e5803e1 SB |
36 | #define RTC |
37 | ||
38 | /* | |
39 | * Size of malloc() pool | |
40 | */ | |
6d0f6bcf | 41 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
5e5803e1 SB |
42 | |
43 | /* | |
44 | * Hardware drivers | |
45 | */ | |
46 | ||
47 | /* | |
48 | * select serial console configuration | |
49 | */ | |
379be585 | 50 | #define CONFIG_PXA_SERIAL |
5e5803e1 SB |
51 | #define CONFIG_FFUART 1 /* we use FFUART on Conxs */ |
52 | #define CONFIG_BTUART 1 /* we use BTUART on Conxs */ | |
53 | #define CONFIG_STUART 1 /* we use STUART on Conxs */ | |
ce6971cd | 54 | #define CONFIG_CONS_INDEX 3 |
5e5803e1 SB |
55 | |
56 | /* allow to overwrite serial and ethaddr */ | |
57 | #define CONFIG_ENV_OVERWRITE | |
58 | ||
59 | #define CONFIG_BAUDRATE 38400 | |
60 | ||
61 | #define CONFIG_DOS_PARTITION 1 | |
62 | ||
63 | /* | |
64 | * Command line configuration. | |
65 | */ | |
5e5803e1 | 66 | #define CONFIG_CMD_FAT |
5e5803e1 SB |
67 | #define CONFIG_CMD_PING |
68 | #define CONFIG_CMD_USB | |
69 | ||
70 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
71 | ||
72 | #undef CONFIG_SHOW_BOOT_PROGRESS | |
73 | ||
74 | #define CONFIG_BOOTDELAY 3 | |
75 | #define CONFIG_SERVERIP 192.168.1.99 | |
76 | #define CONFIG_BOOTCOMMAND "run boot_flash" | |
77 | #define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\ | |
78 | " rw root=/dev/ram initrd=0xa0800000,5m" | |
79 | ||
80 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
81 | "program_boot_mmc=" \ | |
82 | "mw.b 0xa0010000 0xff 0x20000; " \ | |
83 | "if mmcinit && " \ | |
84 | "fatload mmc 0 0xa0010000 u-boot.bin; " \ | |
85 | "then " \ | |
86 | "protect off 0x0 0x1ffff; " \ | |
87 | "erase 0x0 0x1ffff; " \ | |
88 | "cp.b 0xa0010000 0x0 0x20000; " \ | |
89 | "fi\0" \ | |
90 | "program_uzImage_mmc=" \ | |
91 | "mw.b 0xa0010000 0xff 0x180000; " \ | |
92 | "if mmcinit && " \ | |
93 | "fatload mmc 0 0xa0010000 uzImage; " \ | |
94 | "then " \ | |
95 | "protect off 0x40000 0x1bffff; " \ | |
96 | "erase 0x40000 0x1bffff; " \ | |
97 | "cp.b 0xa0010000 0x40000 0x180000; " \ | |
98 | "fi\0" \ | |
99 | "program_ramdisk_mmc=" \ | |
100 | "mw.b 0xa0010000 0xff 0x500000; " \ | |
101 | "if mmcinit && " \ | |
102 | "fatload mmc 0 0xa0010000 ramdisk.gz; " \ | |
103 | "then " \ | |
104 | "protect off 0x1c0000 0x6bffff; " \ | |
105 | "erase 0x1c0000 0x6bffff; " \ | |
106 | "cp.b 0xa0010000 0x1c0000 0x500000; " \ | |
107 | "fi\0" \ | |
108 | "boot_mmc=" \ | |
109 | "if mmcinit && " \ | |
110 | "fatload mmc 0 0xa0030000 uzImage && " \ | |
111 | "fatload mmc 0 0xa0800000 ramdisk.gz; " \ | |
112 | "then " \ | |
113 | "bootm 0xa0030000; " \ | |
114 | "fi\0" \ | |
115 | "boot_flash=" \ | |
116 | "cp.b 0x1c0000 0xa0800000 0x500000; " \ | |
117 | "bootm 0x40000\0" \ | |
118 | ||
119 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
120 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
121 | /* #define CONFIG_INITRD_TAG 1 */ | |
122 | ||
1b769881 | 123 | #if defined(CONFIG_CMD_KGDB) |
5e5803e1 | 124 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
5e5803e1 SB |
125 | #endif |
126 | ||
127 | /* | |
128 | * Miscellaneous configurable options | |
129 | */ | |
6d0f6bcf | 130 | #define CONFIG_SYS_HUSH_PARSER 1 |
5e5803e1 | 131 | |
6d0f6bcf | 132 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
181bd9dc | 133 | #undef CONFIG_SYS_PROMPT |
6d0f6bcf JCPV |
134 | #ifdef CONFIG_SYS_HUSH_PARSER |
135 | #define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ | |
5e5803e1 | 136 | #else |
5e5803e1 | 137 | #endif |
6d0f6bcf JCPV |
138 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
139 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
140 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
141 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
142 | #define CONFIG_SYS_DEVICE_NULLDEV 1 | |
5e5803e1 | 143 | |
6d0f6bcf JCPV |
144 | #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ |
145 | #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ | |
5e5803e1 | 146 | |
6d0f6bcf | 147 | #define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */ |
5e5803e1 | 148 | |
6d0f6bcf | 149 | #define CONFIG_SYS_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */ |
5e5803e1 | 150 | |
b03d92e5 | 151 | #ifdef CONFIG_MMC |
831f849f MV |
152 | #define CONFIG_GENERIC_MMC |
153 | #define CONFIG_PXA_MMC_GENERIC | |
b03d92e5 | 154 | #define CONFIG_CMD_MMC |
6d0f6bcf | 155 | #define CONFIG_SYS_MMC_BASE 0xF0000000 |
b03d92e5 | 156 | #endif |
5e5803e1 | 157 | |
5e5803e1 SB |
158 | /* |
159 | * Physical Memory Map | |
160 | */ | |
161 | #define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ | |
162 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ | |
163 | #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ | |
164 | #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ | |
165 | #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ | |
166 | #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ | |
167 | #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ | |
168 | #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ | |
169 | #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ | |
170 | ||
171 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
172 | ||
6d0f6bcf JCPV |
173 | #define CONFIG_SYS_DRAM_BASE 0xa0000000 |
174 | #define CONFIG_SYS_DRAM_SIZE 0x04000000 | |
5e5803e1 | 175 | |
6d0f6bcf | 176 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
5e5803e1 | 177 | |
6ef6eb91 | 178 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
25ddd1fb | 179 | #define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) |
6ef6eb91 | 180 | |
5e5803e1 SB |
181 | /* |
182 | * GPIO settings | |
183 | */ | |
6d0f6bcf JCPV |
184 | #define CONFIG_SYS_GPSR0_VAL 0x00018000 |
185 | #define CONFIG_SYS_GPSR1_VAL 0x00000000 | |
186 | #define CONFIG_SYS_GPSR2_VAL 0x400dc000 | |
187 | #define CONFIG_SYS_GPSR3_VAL 0x00000000 | |
188 | #define CONFIG_SYS_GPCR0_VAL 0x00000000 | |
189 | #define CONFIG_SYS_GPCR1_VAL 0x00000000 | |
190 | #define CONFIG_SYS_GPCR2_VAL 0x00000000 | |
191 | #define CONFIG_SYS_GPCR3_VAL 0x00000000 | |
192 | #define CONFIG_SYS_GPDR0_VAL 0x00018000 | |
193 | #define CONFIG_SYS_GPDR1_VAL 0x00028801 | |
194 | #define CONFIG_SYS_GPDR2_VAL 0x520dc000 | |
195 | #define CONFIG_SYS_GPDR3_VAL 0x0001E000 | |
196 | #define CONFIG_SYS_GAFR0_L_VAL 0x801c0000 | |
197 | #define CONFIG_SYS_GAFR0_U_VAL 0x00000013 | |
198 | #define CONFIG_SYS_GAFR1_L_VAL 0x6990100A | |
199 | #define CONFIG_SYS_GAFR1_U_VAL 0x00000008 | |
200 | #define CONFIG_SYS_GAFR2_L_VAL 0xA0000000 | |
201 | #define CONFIG_SYS_GAFR2_U_VAL 0x010900F2 | |
202 | #define CONFIG_SYS_GAFR3_L_VAL 0x54000003 | |
203 | #define CONFIG_SYS_GAFR3_U_VAL 0x00002401 | |
204 | #define CONFIG_SYS_GRER0_VAL 0x00000000 | |
205 | #define CONFIG_SYS_GRER1_VAL 0x00000000 | |
206 | #define CONFIG_SYS_GRER2_VAL 0x00000000 | |
207 | #define CONFIG_SYS_GRER3_VAL 0x00000000 | |
040f8f63 | 208 | |
6d0f6bcf | 209 | #define CONFIG_SYS_GFER1_VAL 0x00000000 |
6d0f6bcf JCPV |
210 | #define CONFIG_SYS_GFER3_VAL 0x00000020 |
211 | ||
040f8f63 SB |
212 | #if CONFIG_POLARIS |
213 | #define CONFIG_SYS_GFER0_VAL 0x00000001 | |
214 | #define CONFIG_SYS_GFER2_VAL 0x00200000 | |
215 | #else | |
216 | #define CONFIG_SYS_GFER0_VAL 0x00000000 | |
217 | #define CONFIG_SYS_GFER2_VAL 0x00000000 | |
218 | #endif | |
6d0f6bcf JCPV |
219 | |
220 | #define CONFIG_SYS_PSSR_VAL 0x20 /* CHECK */ | |
5e5803e1 SB |
221 | |
222 | /* | |
223 | * Clock settings | |
224 | */ | |
6d0f6bcf JCPV |
225 | #define CONFIG_SYS_CKEN 0x01FFFFFF /* CHECK */ |
226 | #define CONFIG_SYS_CCCR 0x02000290 /* 520Mhz */ | |
5e5803e1 SB |
227 | |
228 | /* | |
229 | * Memory settings | |
230 | */ | |
231 | ||
6d0f6bcf JCPV |
232 | #define CONFIG_SYS_MSC0_VAL 0x4df84df0 |
233 | #define CONFIG_SYS_MSC1_VAL 0x7ff87ff4 | |
040f8f63 SB |
234 | #if CONFIG_POLARIS |
235 | #define CONFIG_SYS_MSC2_VAL 0xa2697ff8 | |
236 | #else | |
6d0f6bcf | 237 | #define CONFIG_SYS_MSC2_VAL 0xa26936d4 |
040f8f63 | 238 | #endif |
6d0f6bcf JCPV |
239 | #define CONFIG_SYS_MDCNFG_VAL 0x880009C9 |
240 | #define CONFIG_SYS_MDREFR_VAL 0x20ca201e | |
241 | #define CONFIG_SYS_MDMRS_VAL 0x00220022 | |
5e5803e1 | 242 | |
6d0f6bcf JCPV |
243 | #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 |
244 | #define CONFIG_SYS_SXCNFG_VAL 0x40044004 | |
5e5803e1 SB |
245 | |
246 | /* | |
247 | * PCMCIA and CF Interfaces | |
248 | */ | |
6d0f6bcf JCPV |
249 | #define CONFIG_SYS_MECR_VAL 0x00000001 |
250 | #define CONFIG_SYS_MCMEM0_VAL 0x00004204 | |
251 | #define CONFIG_SYS_MCMEM1_VAL 0x00010204 | |
252 | #define CONFIG_SYS_MCATT0_VAL 0x00010504 | |
253 | #define CONFIG_SYS_MCATT1_VAL 0x00010504 | |
254 | #define CONFIG_SYS_MCIO0_VAL 0x00008407 | |
255 | #define CONFIG_SYS_MCIO1_VAL 0x0000c108 | |
5e5803e1 | 256 | |
5e5803e1 | 257 | #define CONFIG_DRIVER_DM9000 1 |
040f8f63 SB |
258 | |
259 | #if CONFIG_POLARIS | |
260 | #define CONFIG_DM9000_BASE 0x0C800000 | |
261 | #else | |
262 | #define CONFIG_DM9000_BASE 0x08000000 | |
263 | #endif | |
264 | ||
5e5803e1 SB |
265 | #define DM9000_IO CONFIG_DM9000_BASE |
266 | #define DM9000_DATA (CONFIG_DM9000_BASE+0x8004) | |
5e5803e1 SB |
267 | |
268 | #define CONFIG_USB_OHCI_NEW 1 | |
6d0f6bcf JCPV |
269 | #define CONFIG_SYS_USB_OHCI_BOARD_INIT 1 |
270 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 | |
271 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 | |
272 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "trizepsiv" | |
5e5803e1 | 273 | #define CONFIG_USB_STORAGE 1 |
6d0f6bcf | 274 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 |
5e5803e1 SB |
275 | |
276 | /* | |
277 | * FLASH and environment organization | |
278 | */ | |
279 | ||
6d0f6bcf | 280 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 281 | #define CONFIG_FLASH_CFI_DRIVER 1 |
5e5803e1 | 282 | |
6d0f6bcf JCPV |
283 | #define CONFIG_SYS_MONITOR_BASE 0 |
284 | #define CONFIG_SYS_MONITOR_LEN 0x40000 | |
5e5803e1 | 285 | |
6d0f6bcf JCPV |
286 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
287 | #define CONFIG_SYS_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */ | |
5e5803e1 SB |
288 | |
289 | /* timeout values are in ticks */ | |
6d0f6bcf JCPV |
290 | #define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
291 | #define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ | |
5e5803e1 SB |
292 | |
293 | /* write flash less slowly */ | |
6d0f6bcf | 294 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
5e5803e1 | 295 | |
040f8f63 SB |
296 | /* Unlock to be used with Intel chips */ |
297 | #define CONFIG_SYS_FLASH_PROTECTION 1 | |
298 | ||
5e5803e1 | 299 | /* Flash environment locations */ |
5a1aceb0 | 300 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 301 | #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) /* Addr of Environment Sector */ |
0e8d1586 JCPV |
302 | #define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment */ |
303 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ | |
5e5803e1 SB |
304 | |
305 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
306 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE) |
307 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
5e5803e1 SB |
308 | |
309 | #endif /* __CONFIG_H */ |