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1 | /* |
2 | * Copyright (C) 2015, Savoir-faire Linux Inc. | |
3 | * | |
4 | * Derived from MX51EVK code by | |
5 | * Guennadi Liakhovetski <lg@denx.de> | |
6 | * Freescale Semiconductor, Inc. | |
7 | * | |
8 | * Configuration settings for the TS4800 Board | |
9 | * | |
10 | * SPDX-License-Identifier: GPL-2.0+ | |
11 | */ | |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
16 | /* High Level Configuration Options */ | |
9ee16897 | 17 | |
a187559e | 18 | #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage bootloader */ |
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19 | |
20 | #define CONFIG_HW_WATCHDOG | |
21 | ||
94ba26f2 TR |
22 | #define CONFIG_MACH_TYPE MACH_TYPE_TS48XX |
23 | ||
9ee16897 | 24 | /* text base address used when linking */ |
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25 | |
26 | #include <asm/arch/imx-regs.h> | |
27 | ||
28 | /* enable passing of ATAGs */ | |
29 | #define CONFIG_CMDLINE_TAG | |
30 | #define CONFIG_SETUP_MEMORY_TAGS | |
31 | #define CONFIG_INITRD_TAG | |
32 | #define CONFIG_REVISION_TAG | |
33 | ||
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34 | /* |
35 | * Size of malloc() pool | |
36 | */ | |
37 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) | |
38 | ||
39 | /* | |
40 | * Hardware drivers | |
41 | */ | |
42 | ||
43 | #define CONFIG_MXC_UART | |
44 | #define CONFIG_MXC_UART_BASE UART1_BASE | |
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45 | |
46 | /* | |
47 | * SPI Configs | |
48 | * */ | |
49 | #define CONFIG_HARD_SPI /* puts SPI: ready */ | |
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50 | |
51 | /* | |
52 | * MMC Configs | |
53 | * */ | |
54 | #define CONFIG_FSL_ESDHC | |
55 | #define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR | |
56 | ||
f3488bb3 DR |
57 | /* |
58 | * Eth Configs | |
59 | */ | |
60 | #define CONFIG_MII | |
f3488bb3 DR |
61 | #define CONFIG_PHY_SMSC |
62 | ||
63 | #define CONFIG_FEC_MXC | |
64 | #define IMX_FEC_BASE FEC_BASE_ADDR | |
65 | #define CONFIG_ETHPRIME "FEC" | |
66 | #define CONFIG_FEC_MXC_PHYADDR 0 | |
67 | ||
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68 | /* allow to overwrite serial and ethaddr */ |
69 | #define CONFIG_ENV_OVERWRITE /* disable vendor parameters protection (serial#, ethaddr) */ | |
70 | #define CONFIG_CONS_INDEX 1 /* use UART0 : used by serial driver */ | |
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71 | |
72 | /*********************************************************** | |
73 | * Command definition | |
74 | ***********************************************************/ | |
75 | ||
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76 | /* Environment variables */ |
77 | ||
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78 | |
79 | #define CONFIG_LOADADDR 0x91000000 /* loadaddr env var */ | |
80 | ||
81 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
82 | "script=boot.scr\0" \ | |
e453794f DR |
83 | "image=zImage\0" \ |
84 | "fdt_file=imx51-ts4800.dtb\0" \ | |
85 | "fdt_addr=0x90fe0000\0" \ | |
9ee16897 | 86 | "mmcdev=0\0" \ |
e453794f DR |
87 | "mmcpart=2\0" \ |
88 | "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \ | |
89 | "mmcargs=setenv bootargs root=${mmcroot}\0" \ | |
9ee16897 LQ |
90 | "addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \ |
91 | "loadbootscript=" \ | |
92 | "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ | |
93 | "bootscript=echo Running bootscript from mmc ...; " \ | |
94 | "source\0" \ | |
95 | "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \ | |
e453794f | 96 | "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ |
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97 | "mmcboot=echo Booting from mmc ...; " \ |
98 | "run mmcargs addtty; " \ | |
e453794f DR |
99 | "if run loadfdt; then " \ |
100 | "bootz ${loadaddr} - ${fdt_addr}; " \ | |
101 | "else " \ | |
102 | "echo ERR: cannot load FDT; " \ | |
103 | "fi; " | |
104 | ||
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105 | |
106 | #define CONFIG_BOOTCOMMAND \ | |
107 | "mmc dev ${mmcdev}; if mmc rescan; then " \ | |
108 | "if run loadbootscript; then " \ | |
109 | "run bootscript; " \ | |
110 | "else " \ | |
111 | "if run loadimage; then " \ | |
112 | "run mmcboot; " \ | |
113 | "fi; " \ | |
114 | "fi; " \ | |
115 | "fi; " | |
116 | ||
117 | /* | |
118 | * Miscellaneous configurable options | |
119 | */ | |
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120 | |
121 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
122 | ||
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123 | /*----------------------------------------------------------------------- |
124 | * Physical Memory Map | |
125 | */ | |
126 | #define CONFIG_NR_DRAM_BANKS 1 | |
127 | #define PHYS_SDRAM_1 CSD0_BASE_ADDR | |
128 | #define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) | |
129 | ||
130 | #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) | |
131 | #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) | |
132 | #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) | |
133 | ||
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134 | #define CONFIG_SYS_INIT_SP_OFFSET \ |
135 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
136 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
137 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
138 | ||
139 | /* Low level init */ | |
140 | #define CONFIG_SYS_DDR_CLKSEL 0 | |
141 | #define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 | |
142 | #define CONFIG_SYS_MAIN_PWR_ON | |
143 | ||
144 | /*----------------------------------------------------------------------- | |
145 | * Environment organization | |
146 | */ | |
147 | ||
148 | #define CONFIG_ENV_OFFSET (6 * 64 * 1024) | |
149 | #define CONFIG_ENV_SIZE (8 * 1024) | |
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150 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
151 | ||
152 | #endif |