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4d86dd02 HR |
1 | /* |
2 | * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at> | |
3 | * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> | |
4 | * | |
5 | * Configuration settings for the HALE TT-01 board. | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
4d86dd02 HR |
8 | */ |
9 | ||
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
13 | #include <asm/arch/imx-regs.h> | |
14 | ||
15 | /* High Level Configuration Options */ | |
4d86dd02 | 16 | #define CONFIG_MX31 |
4d86dd02 HR |
17 | |
18 | #define CONFIG_DISPLAY_CPUINFO | |
19 | #define CONFIG_DISPLAY_BOARDINFO | |
20 | ||
21 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
22 | #define CONFIG_SETUP_MEMORY_TAGS | |
23 | #define CONFIG_INITRD_TAG | |
24 | ||
25 | #define CONFIG_MACH_TYPE 3726 /* not yet in mach-types.h */ | |
26 | #define CONFIG_SYS_TEXT_BASE 0xA0000000 | |
27 | ||
28 | ||
29 | /* | |
30 | * Physical Memory Map: | |
31 | * CS settings are defined by i.MX31: | |
32 | * - CSD0 and CDS1 are 256MB each, starting at 0x80000000 and 0x9000000 | |
33 | * - CS0 and CS1 are 128MB each, at A0000000 and A8000000 | |
34 | * - CS2 to CS5 are 32MB each, at B0.., B2.., B4.., B6.. | |
35 | * | |
36 | * HALE set-up of the bluetechnix board for now is: | |
37 | * - 128MB DDR (2x64MB, 2x16bit), connected to 32bit DDR ram interface | |
38 | * - NOR-Flash (Spansion 32MB MCP, Flash+16MB PSRAM), 16bit interface at CS0 | |
39 | * - S71WS256ND0BFWYM (and CS1 for 64MB S71WS512ND0 without PSRAM) | |
40 | * the flash chip is a mirrorbit S29WS256N ! | |
41 | * - the PSRAM is hooked to CS5 (0xB6000000) | |
42 | * - Intel Strata Flash PF48F2000P0ZB00, 16bit interface at (CS0 or) CS1 | |
43 | * - 64Mbit = 8MByte (will go away in the production set-up) | |
44 | * - NAND-Flash NAND01GR3B2BZA6 at NAND-FC: | |
45 | * 1Gbit=128MB, 2048+64 bytes/page, 64pages x 1024 blocks | |
46 | * - Ethernet controller SMC9118 at CS4 via FPGA, 16bit interface | |
47 | * | |
48 | * u-boot will support the 32MB nor flash and the 128MB NAND flash, the PSRAM | |
49 | * is not used right now. We should be able to reduce the SOM to NAND flash | |
50 | * only and boot from there. | |
51 | */ | |
52 | #define CONFIG_NR_DRAM_BANKS 1 | |
53 | #define PHYS_SDRAM_1 CSD0_BASE | |
54 | #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) | |
55 | ||
56 | #define CONFIG_BOARD_EARLY_INIT_F | |
57 | #define CONFIG_BOARD_LATE_INIT | |
58 | ||
59 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
60 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
61 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
62 | #define CONFIG_SYS_GBL_DATA_OFFSET \ | |
63 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
64 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
65 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) | |
66 | ||
67 | /* default load address, 1MB up the road */ | |
68 | #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1+0x100000) | |
69 | ||
4d86dd02 HR |
70 | /* Size of malloc() pool, make sure possible frame buffer fits */ |
71 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 10*1024*1024) | |
72 | ||
73 | /* memtest works on all but the last 1MB (u-boot) and malloc area */ | |
74 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 | |
75 | #define CONFIG_SYS_MEMTEST_END \ | |
76 | (PHYS_SDRAM_1+(PHYS_SDRAM_1_SIZE-CONFIG_SYS_MALLOC_LEN-0x100000)) | |
77 | ||
78 | /* CFI FLASH driver setup */ | |
79 | #define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ | |
80 | #define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ | |
81 | #define CONFIG_FLASH_SPANSION_S29WS_N | |
82 | /* | |
83 | * TODO: Bluetechnix (the supplier of the SOM) did define these values | |
84 | * in their original version of u-boot (1.2 or so). This should be | |
85 | * reviewed. | |
86 | * | |
87 | * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
88 | * #define CONFIG_SYS_FLASH_PROTECTION | |
89 | */ | |
90 | #define CONFIG_SYS_FLASH_BASE CS0_BASE | |
91 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
92 | #define CONFIG_SYS_MAX_FLASH_SECT (254+8) /* max number of sectors per chip */ | |
93 | ||
94 | /* | |
95 | * FLASH and environment organization, only the Spansion chip is supported: | |
96 | * - it has 254 * 128kB + 8 * 32kB blocks | |
97 | * - this setup uses 4*32k+3*128k as monitor space = 0xA000 0000 to 0xA00F FFFF | |
98 | * and 2 sectors with 128k as environment = | |
99 | * A010 0000 to 0xA011 FFFF and 0xA012 0000 to 0xA013 FFFF | |
100 | * - this could be less, but this is only for developer versions of the board | |
101 | * and no-one is going to use the NOR flash anyway. | |
102 | * | |
103 | * Monitor is at the beginning of the NOR-Flash, 1MB reserved. Again this is | |
104 | * way to large, but it avoids ENV overwrite (when updating u-boot) in case | |
105 | * size breaks the next boundary (as it has with 128k). | |
106 | */ | |
107 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
108 | #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) | |
109 | ||
110 | #define CONFIG_ENV_IS_IN_FLASH | |
111 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) | |
0b87e010 | 112 | #define CONFIG_ENV_SIZE (128 * 1024) |
4d86dd02 HR |
113 | |
114 | /* Address and size of Redundant Environment Sector */ | |
115 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) | |
116 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
117 | ||
118 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
119 | ||
120 | /* Hardware drivers */ | |
121 | ||
122 | /* | |
123 | * on TT-01 UART1 pins are used by Audio, so we use UART2 | |
124 | * TT-01 implements a hardware that turns off components depending on | |
125 | * the power level. In PL=1 the RS232 transceiver is usually off, | |
126 | * make sure that the transceiver is enabled during PL=1 for testing! | |
127 | */ | |
128 | #define CONFIG_MXC_UART | |
40f6fffe | 129 | #define CONFIG_MXC_UART_BASE UART2_BASE |
4d86dd02 HR |
130 | |
131 | #define CONFIG_MXC_SPI | |
132 | #define CONFIG_MXC_GPIO | |
133 | ||
134 | /* MC13783 connected to CSPI3 and SS0 */ | |
be3b51aa ŁM |
135 | #define CONFIG_POWER |
136 | #define CONFIG_POWER_SPI | |
137 | #define CONFIG_POWER_FSL | |
4d86dd02 HR |
138 | |
139 | #define CONFIG_FSL_PMIC_BUS 2 | |
140 | #define CONFIG_FSL_PMIC_CS 0 | |
141 | #define CONFIG_FSL_PMIC_CLK 1000000 | |
142 | #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) | |
143 | #define CONFIG_FSL_PMIC_BITLEN 32 | |
144 | ||
145 | #define CONFIG_RTC_MC13XXX | |
146 | ||
147 | /* allow to overwrite serial and ethaddr */ | |
148 | #define CONFIG_ENV_OVERWRITE | |
149 | /* console is UART2 on TT-01 */ | |
150 | #define CONFIG_CONS_INDEX 1 | |
151 | #define CONFIG_BAUDRATE 115200 | |
4d86dd02 HR |
152 | |
153 | /* ethernet setup for the onboard smc9118 */ | |
154 | #define CONFIG_MII | |
155 | #define CONFIG_SMC911X | |
156 | /* 16 bit, onboard ethernet, decoded via MACH-MX0 FPGA at 0x84200000 */ | |
157 | #define CONFIG_SMC911X_BASE (CS4_BASE+0x200000) | |
158 | #define CONFIG_SMC911X_16_BIT | |
159 | ||
f353518f HR |
160 | /* mmc driver */ |
161 | #define CONFIG_MMC | |
162 | #define CONFIG_GENERIC_MMC | |
163 | #define CONFIG_MXC_MMC | |
164 | #define CONFIG_MXC_MCI_REGS_BASE SDHC1_BASE_ADDR | |
d1300f76 HR |
165 | |
166 | /* video support */ | |
167 | #define CONFIG_VIDEO | |
168 | #define CONFIG_VIDEO_MX3 | |
169 | #define CONFIG_CFB_CONSOLE | |
170 | #define CONFIG_VIDEO_LOGO | |
07c80bc2 | 171 | /* splash image won't work with NAND boot, use preboot script */ |
d1300f76 HR |
172 | #define CONFIG_VIDEO_SW_CURSOR |
173 | #define CONFIG_CONSOLE_EXTRA_INFO /* display additional board info */ | |
174 | #define CONFIG_VGA_AS_SINGLE_DEVICE /* display is an output only device */ | |
07c80bc2 | 175 | |
d1300f76 HR |
176 | /* allow stdin, stdout and stderr variables to redirect output */ |
177 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
07c80bc2 HR |
178 | #define CONFIG_SILENT_CONSOLE /* UARTs used externally (release) */ |
179 | #define CONFIG_SYS_DEVICE_NULLDEV /* allow console to be turned off */ | |
180 | #define CONFIG_PREBOOT | |
d1300f76 HR |
181 | |
182 | /* allow decompressing max. 4MB */ | |
183 | #define CONFIG_VIDEO_BMP_GZIP | |
184 | /* this is not only used by cfb_console.c for the logo, but also in cmd_bmp.c */ | |
185 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4*1024*1024) | |
186 | ||
4d86dd02 HR |
187 | /* |
188 | * Command definition | |
189 | */ | |
4d86dd02 HR |
190 | #define CONFIG_CMD_DATE |
191 | #define CONFIG_CMD_PING | |
192 | #define CONFIG_CMD_DHCP | |
4d86dd02 HR |
193 | #define CONFIG_CMD_NAND |
194 | /* | |
195 | * #define CONFIG_CMD_NAND_LOCK_UNLOCK the NAND01... chip does not support | |
196 | * the NAND_CMD_LOCK_STATUS command, however the NFC of i.MX31 supports | |
197 | * a software locking scheme. | |
198 | */ | |
d1300f76 | 199 | #define CONFIG_CMD_BMP |
4d86dd02 HR |
200 | |
201 | #define CONFIG_BOOTDELAY 3 | |
202 | ||
203 | /* | |
204 | * currently a default setting for booting via script is implemented | |
205 | * set user to login name and serverip to tftp host, define your | |
206 | * boot behaviour in bootscript.loginname | |
d1300f76 HR |
207 | * |
208 | * TT-01 board specific TFT setup (used by drivers/video/mx3fb.c) | |
209 | * | |
210 | * This set-up is for the L5F30947T04 by Epson, which is | |
211 | * 800x480, 33MHz pixel clock, 60Hz vsync, 31.6kHz hsync | |
212 | * sync must be set to: DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL | |
4d86dd02 HR |
213 | */ |
214 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
d1300f76 HR |
215 | "videomode=epson\0" \ |
216 | "epson=video=ctfb:x:800,y:480,depth:16,mode:0,pclk:30076," \ | |
217 | "le:215,ri:1,up:32,lo:13,hs:7,vs:10,sync:100663296,vmode:0\0" \ | |
07c80bc2 | 218 | "bootcmd=dhcp bootscript.${user}; source\0" |
4d86dd02 HR |
219 | |
220 | #define CONFIG_BOOTP_SERVERIP /* tftp serverip not overruled by dhcp server */ | |
221 | #define CONFIG_BOOTP_SEND_HOSTNAME /* if env-var 'hostname' is set, send it */ | |
222 | ||
223 | /* Miscellaneous configurable options */ | |
07c80bc2 | 224 | #define CONFIG_SYS_HUSH_PARSER |
4d86dd02 HR |
225 | |
226 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
4d86dd02 HR |
227 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
228 | /* Print Buffer Size */ | |
229 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
230 | sizeof(CONFIG_SYS_PROMPT)+16) | |
231 | /* max number of command args */ | |
232 | #define CONFIG_SYS_MAXARGS 16 | |
233 | /* Boot Argument Buffer Size */ | |
234 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
235 | ||
4d86dd02 HR |
236 | #define CONFIG_CMDLINE_EDITING |
237 | ||
f353518f HR |
238 | /* MMC boot support */ |
239 | #define CONFIG_CMD_MMC | |
240 | #define CONFIG_DOS_PARTITION | |
241 | #define CONFIG_EFI_PARTITION | |
242 | #define CONFIG_CMD_EXT2 | |
243 | #define CONFIG_CMD_FAT | |
244 | ||
4d86dd02 HR |
245 | #define CONFIG_NAND_MXC |
246 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
4d86dd02 HR |
247 | |
248 | /* | |
249 | * actually this is nothing someone wants to configure! | |
250 | * CONFIG_SYS_NAND_BASE despite being passed to board_nand_init() | |
251 | * is not used by the driver. | |
252 | */ | |
253 | #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR | |
254 | #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR | |
255 | #define CONFIG_MXC_NAND_HWECC | |
256 | ||
257 | /* the current u-boot driver does not use the nand flash setup! */ | |
258 | #define CONFIG_SYS_NAND_LARGEPAGE | |
259 | /* | |
260 | * it's not 16 bit: | |
261 | * #define CONFIG_SYS_NAND_BUSWIDTH_16BIT | |
262 | * the current u-boot mxc_nand.c tries to auto-detect, but this only | |
263 | * reads the boot settings during reset (which might be wrong) | |
264 | */ | |
265 | ||
266 | #endif /* __CONFIG_H */ |