[people/ms/u-boot.git] / include / configs / uc100.h

/*
 * (C) Copyright 2000-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC860		1
#define CONFIG_MPC860T		1
#define CONFIG_MPC862		1       /* enable 862 since the         */
#define CONFIG_MPC857		1       /* 857 is a variant of the 862  */

#define CONFIG_UC100		1	/* ...on a UC100 module	        */

#define	CONFIG_SYS_TEXT_BASE	0x40700000

#define MPC8XX_FACT		4		/* Multiply by 4	*/
#define MPC8XX_XIN		25000000	/* 25.0 MHz in		*/
#define CONFIG_8xx_GCLK_FREQ	(MPC8XX_FACT * MPC8XX_XIN)
				    /* define if cant' use get_gclk_freq */

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE

#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/

#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/

#define	CONFIG_BOOTCOUNT_LIMIT

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define CONFIG_BOARD_TYPES	1	/* support board types		*/

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
		"bootm\0"						\
	"rootpath=/opt/eldk/ppc_8xx\0"					\
	"bootfile=/tftpboot/uc100/uImage\0"				\
	"kernel_addr=40000000\0"					\
	"ramdisk_addr=40100000\0"					\
	"load=tftp 100000 /tftpboot/uc100/u-boot.bin\0"			\
	"update=protect off 40700000 4073ffff;era 40700000 4073ffff;"	\
		"cp.b 100000 40700000 ${filesize};"			\
		"setenv filesize;saveenv\0"				\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#undef CONFIG_STATUS_LED                /* no status-led                */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#undef CONFIG_RTC_MPC8xx
#define CONFIG_SYS_I2C_RTC_ADDR	0x51	/* PCF8563 RTC			*/
#define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/

/*
 * Power On Self Test support
 */
#define CONFIG_POST	      ( CONFIG_SYS_POST_CACHE		| \
				CONFIG_SYS_POST_MEMORY		| \
				CONFIG_SYS_POST_CPU		| \
				CONFIG_SYS_POST_UART		| \
				CONFIG_SYS_POST_SPR )
#undef  CONFIG_POST


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_MII
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_SNTP

#ifdef CONFIG_POST
#define CONFIG_CMD_DIAG
#endif


#define CONFIG_NETCONSOLE

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/

#if 0
#define	CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
#endif

#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xF0000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x40000000
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE+0x00700000) /* resetvec fff00100*/
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*-----------------------------------------------------------------------
 * Address accessed to reset the board - must not be mapped/assigned
 */
#define CONFIG_SYS_RESET_ADDRESS       0x90000000

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible  */
#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1		/* AMD RESET for STM 29W320DB!  */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#define	CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector		*/
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_FRC | SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 */
#define CONFIG_SYS_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	0x00000000
#define CONFIG_SYS_SCCR        (SCCR_EBDF11)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER	0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xFF800000	/* OR addr mask */

/*
 * FLASH timing:
 */
#define CONFIG_SYS_OR_TIMING_FLASH	(0x00000d24)

#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )

#define CONFIG_SYS_BR1_PRELIM  0x00000081  /* Chip select for SDRAM (32 Bit, UPMA) */
#define CONFIG_SYS_OR1_PRELIM  0xfc000a00
#define CONFIG_SYS_BR2_PRELIM  0x80000001  /* Chip select for SRAM (32 Bit, GPCM) */
#define CONFIG_SYS_OR2_PRELIM  0xfff00d24
#define CONFIG_SYS_BR3_PRELIM  0x80600401  /* Chip select for Display (8 Bit, GPCM) */
#define CONFIG_SYS_OR3_PRELIM  0xffff8f44
#define CONFIG_SYS_BR4_PRELIM  0xc05108c1  /* Chip select for Interbus MPM (16 Bit, UPMB) */
#define CONFIG_SYS_OR4_PRELIM  0xffff0300
#define CONFIG_SYS_BR5_PRELIM  0xc0500401  /* Chip select for Interbus Status (8 Bit, GPCM) */
#define CONFIG_SYS_OR5_PRELIM  0xffff8db0

/*
 * Memory Periodic Timer Prescaler
 *
 * The Divider for PTA (refresh timer) configuration is based on an
 * example SDRAM configuration (64 MBit, one bank). The adjustment to
 * the number of chip selects (NCS) and the actually needed refresh
 * rate is done by setting MPTPR.
 *
 * PTA is calculated from
 *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 *
 *	gclk	  CPU clock (not bus clock!)
 *	Trefresh  Refresh cycle * 4 (four word bursts used)
 *
 * 4096  Rows from SDRAM example configuration
 * 1000  factor s -> ms
 *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 *    4  Number of refresh cycles per period
 *   64  Refresh cycle in ms per number of rows
 * --------------------------------------------
 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 *
 *  50 MHz =>  50.000.000 / Divider =  98
 *  66 Mhz =>  66.000.000 / Divider = 129
 *  80 Mhz =>  80.000.000 / Divider = 156
 * 100 Mhz => 100.000.000 / Divider = 195
 */

#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
#define CONFIG_SYS_MAMR_PTA	98

/*
 * For 16 MBit, refresh rates could be 31.3 us
 * (= 64 ms / 2K = 125 / quad bursts).
 * For a simpler initialization, 15.6 us is used instead.
 *
 * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
 * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
 */
#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

#define	CONFIG_SYS_MAMR_VAL	0x30904114	/* for SDRAM */
#define	CONFIG_SYS_MBMR_VAL	0xff001111	/* for Interbus-MPM */

/*-----------------------------------------------------------------------
 * I2C stuff
 */

/* enable I2C and select the hardware/software driver */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED	93000 /* 93 kHz is supposed to work */
#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
/*
 * Software (bit-bang) I2C driver configuration
 */
#define PB_SCL		0x00000020	/* PB 26 */
#define PB_SDA		0x00000010	/* PB 27 */

#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */

/*-----------------------------------------------------------------------
 * I2C EEPROM (24C164)
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x58	/* EEPROM AT24C164		*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec	*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4

#define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
#define FEC_ENET
#define CONFIG_MII
#define CONFIG_MII_INIT		1
#define CONFIG_SYS_DISCOVER_PHY	1

#endif	/* __CONFIG_H */
Commit	Line	Data
f7d1572b	1	/*
414eec35	2	* (C) Copyright 2000-2005
f7d1572b WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
f7d1572b WD	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
f7d1572b WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	* (easy to change)
	18	*/
	19
	20	#define CONFIG_MPC860 1
	21	#define CONFIG_MPC860T 1
	22	#define CONFIG_MPC862 1 /* enable 862 since the */
	23	#define CONFIG_MPC857 1 /* 857 is a variant of the 862 */
	24
	25	#define CONFIG_UC100 1 /* ...on a UC100 module */
	26
2ae18241 WD	27	#define CONFIG_SYS_TEXT_BASE 0x40700000
2ae18241 WD	28
f7d1572b WD	29	#define MPC8XX_FACT 4 /* Multiply by 4 */
	30	#define MPC8XX_XIN 25000000 /* 25.0 MHz in */
	31	#define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN)
	32	/* define if cant' use get_gclk_freq */
	33
	34	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	35	#undef CONFIG_8xx_CONS_SMC2
	36	#undef CONFIG_8xx_CONS_NONE
	37
	38	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
	39
	40	#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
	41
	42	#define CONFIG_BOOTCOUNT_LIMIT
	43
	44	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	45
	46	#define CONFIG_BOARD_TYPES 1 /* support board types */
	47
	48	#define CONFIG_PREBOOT "echo;" \
32bf3d14	49	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
f7d1572b WD	50	"echo"
	51
	52	#undef CONFIG_BOOTARGS
	53
	54	#define CONFIG_EXTRA_ENV_SETTINGS \
	55	"netdev=eth0\0" \
	56	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	57	"nfsroot=${serverip}:${rootpath}\0" \
f7d1572b	58	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	59	"addip=setenv bootargs ${bootargs} " \
	60	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	61	":${hostname}:${netdev}:off panic=1\0" \
	62	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
f7d1572b	63	"flash_nfs=run nfsargs addip addtty;" \
fe126d8b	64	"bootm ${kernel_addr}\0" \
f7d1572b	65	"flash_self=run ramargs addip addtty;" \
fe126d8b WD	66	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	67	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
93e14596	68	"bootm\0" \
f7d1572b WD	69	"rootpath=/opt/eldk/ppc_8xx\0" \
	70	"bootfile=/tftpboot/uc100/uImage\0" \
	71	"kernel_addr=40000000\0" \
	72	"ramdisk_addr=40100000\0" \
	73	"load=tftp 100000 /tftpboot/uc100/u-boot.bin\0" \
	74	"update=protect off 40700000 4073ffff;era 40700000 4073ffff;" \
fe126d8b	75	"cp.b 100000 40700000 ${filesize};" \
f7d1572b WD	76	"setenv filesize;saveenv\0" \
	77	""
	78	#define CONFIG_BOOTCOMMAND "run flash_self"
	79
	80	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	81	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
f7d1572b WD	82
	83	#undef CONFIG_WATCHDOG /* watchdog disabled */
	84
	85	#undef CONFIG_STATUS_LED /* no status-led */
	86
d3b8c1a7 JL	87	/*
	88	* BOOTP options
	89	*/
	90	#define CONFIG_BOOTP_SUBNETMASK
	91	#define CONFIG_BOOTP_GATEWAY
	92	#define CONFIG_BOOTP_HOSTNAME
	93	#define CONFIG_BOOTP_BOOTPATH
	94	#define CONFIG_BOOTP_BOOTFILESIZE
	95
f7d1572b WD	96
	97	#define CONFIG_MAC_PARTITION
	98	#define CONFIG_DOS_PARTITION
	99
	100	#undef CONFIG_RTC_MPC8xx
6d0f6bcf	101	#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
f7d1572b WD	102	#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
	103
	104	/*
	105	* Power On Self Test support
	106	*/
6d0f6bcf JCPV	107	#define CONFIG_POST ( CONFIG_SYS_POST_CACHE \| \
	108	CONFIG_SYS_POST_MEMORY \| \
	109	CONFIG_SYS_POST_CPU \| \
	110	CONFIG_SYS_POST_UART \| \
	111	CONFIG_SYS_POST_SPR )
f7d1572b WD	112	#undef CONFIG_POST
f7d1572b WD	113
f7d1572b	114
6c18eb98 JL	115	/*
	116	* Command line configuration.
	117	*/
	118	#include <config_cmd_default.h>
	119
	120	#define CONFIG_CMD_ASKENV
	121	#define CONFIG_CMD_DATE
	122	#define CONFIG_CMD_DHCP
	123	#define CONFIG_CMD_EEPROM
	124	#define CONFIG_CMD_ELF
	125	#define CONFIG_CMD_FAT
	126	#define CONFIG_CMD_I2C
	127	#define CONFIG_CMD_IDE
	128	#define CONFIG_CMD_MII
	129	#define CONFIG_CMD_NFS
	130	#define CONFIG_CMD_PING
6c18eb98	131	#define CONFIG_CMD_SNTP
f7d1572b	132
af075ee9 JL	133	#ifdef CONFIG_POST
	134	#define CONFIG_CMD_DIAG
	135	#endif
	136
6c18eb98 JL	137
6c18eb98 JL	138	#define CONFIG_NETCONSOLE
f7d1572b WD	139
	140	/*
	141	* Miscellaneous configurable options
	142	*/
6d0f6bcf	143	#define CONFIG_SYS_LONGHELP /* undef to save memory */
f7d1572b WD	144
f7d1572b WD	145	#if 0
6d0f6bcf	146	#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
f7d1572b	147	#endif
f7d1572b	148
6c18eb98	149	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	150	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
f7d1572b	151	#else
6d0f6bcf	152	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
f7d1572b	153	#endif
6d0f6bcf JCPV	154	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	155	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	156	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
f7d1572b	157
6d0f6bcf JCPV	158	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	159	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
f7d1572b	160
6d0f6bcf	161	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
f7d1572b	162
f7d1572b WD	163	#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
	164
	165	/*
	166	* Low Level Configuration Settings
	167	* (address mappings, register initial values, etc.)
	168	* You should know what you are doing if you make changes here.
	169	*/
	170	/*-----------------------------------------------------------------------
	171	* Internal Memory Mapped Register
	172	*/
6d0f6bcf	173	#define CONFIG_SYS_IMMR 0xF0000000
f7d1572b WD	174
	175	/*-----------------------------------------------------------------------
	176	* Definitions for initial stack pointer and data area (in DPRAM)
	177	*/
6d0f6bcf	178	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	179	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	180	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	181	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
f7d1572b WD	182
	183	/*-----------------------------------------------------------------------
	184	* Start addresses for the final memory configuration
	185	* (Set up by the startup code)
6d0f6bcf	186	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
f7d1572b	187	*/
6d0f6bcf JCPV	188	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	189	#define CONFIG_SYS_FLASH_BASE 0x40000000
	190	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	191	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE+0x00700000) /* resetvec fff00100*/
	192	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
f7d1572b WD	193
	194	/*-----------------------------------------------------------------------
	195	* Address accessed to reset the board - must not be mapped/assigned
	196	*/
6d0f6bcf	197	#define CONFIG_SYS_RESET_ADDRESS 0x90000000
f7d1572b WD	198
	199	/*
	200	* For booting Linux, the board info and command line data
	201	* have to be in the first 8 MB of memory, since this is
	202	* the maximum mapped by the Linux kernel during initialization.
	203	*/
6d0f6bcf	204	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
f7d1572b WD	205
	206	/*-----------------------------------------------------------------------
	207	* FLASH organization
	208	*/
6d0f6bcf	209	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
00b1883a	210	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
6d0f6bcf	211	#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
f7d1572b	212
6d0f6bcf JCPV	213	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	214	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
f7d1572b	215
6d0f6bcf JCPV	216	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	217	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
f7d1572b	218
6d0f6bcf	219	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
f7d1572b	220
5a1aceb0	221	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	222	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
0e8d1586 JCPV	223	#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
0e8d1586 JCPV	224	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
f7d1572b WD	225
f7d1572b WD	226	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	227	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	228	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
f7d1572b WD	229
	230	/*-----------------------------------------------------------------------
	231	* Cache Configuration
	232	*/
6d0f6bcf	233	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
6c18eb98	234	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	235	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
f7d1572b WD	236	#endif
	237
	238	/*-----------------------------------------------------------------------
	239	* SYPCR - System Protection Control 11-9
	240	* SYPCR can only be written once after reset!
	241	*-----------------------------------------------------------------------
	242	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	243	*/
	244	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	245	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
f7d1572b WD	246	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
f7d1572b WD	247	#else
6d0f6bcf	248	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
f7d1572b WD	249	#endif
	250
	251	/*-----------------------------------------------------------------------
	252	* SIUMCR - SIU Module Configuration 11-6
	253	*-----------------------------------------------------------------------
	254	* PCMCIA config., multi-function pin tri-state
	255	*/
6d0f6bcf	256	#define CONFIG_SYS_SIUMCR (SIUMCR_FRC \| SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
f7d1572b WD	257
	258	/*-----------------------------------------------------------------------
	259	* TBSCR - Time Base Status and Control 11-26
	260	*-----------------------------------------------------------------------
	261	* Clear Reference Interrupt Status, Timebase freezing enabled
	262	*/
6d0f6bcf	263	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
f7d1572b WD	264
	265	/*-----------------------------------------------------------------------
	266	* RTCSC - Real-Time Clock Status and Control Register 11-27
	267	*-----------------------------------------------------------------------
	268	*/
6d0f6bcf	269	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
f7d1572b WD	270
	271	/*-----------------------------------------------------------------------
	272	* PISCR - Periodic Interrupt Status and Control 11-31
	273	*-----------------------------------------------------------------------
	274	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	275	*/
6d0f6bcf	276	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
f7d1572b WD	277
	278	/*-----------------------------------------------------------------------
	279	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	280	*-----------------------------------------------------------------------
	281	* Reset PLL lock status sticky bit, timer expired status bit and timer
	282	* interrupt status bit
	283	*/
6d0f6bcf	284	#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) \| \
f7d1572b WD	285	PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
	286
	287	/*-----------------------------------------------------------------------
	288	* SCCR - System Clock and reset Control Register 15-27
	289	*-----------------------------------------------------------------------
	290	* Set clock output, timebase and RTC source and divider,
	291	* power management and some other internal clocks
	292	*/
	293	#define SCCR_MASK 0x00000000
6d0f6bcf	294	#define CONFIG_SYS_SCCR (SCCR_EBDF11)
f7d1572b WD	295
	296	/*-----------------------------------------------------------------------
	297	* PCMCIA stuff
	298	*-----------------------------------------------------------------------
	299	*
	300	*/
6d0f6bcf JCPV	301	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	302	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	303	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	304	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	305	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	306	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	307	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	308	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
f7d1572b WD	309
	310	/*-----------------------------------------------------------------------
	311	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	312	*-----------------------------------------------------------------------
	313	*/
	314
8d1165e1	315	#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
f7d1572b WD	316	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
	317
	318	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	319	#undef CONFIG_IDE_LED /* LED for ide not supported */
	320	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	321
6d0f6bcf JCPV	322	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	323	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
f7d1572b	324
6d0f6bcf	325	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
f7d1572b	326
6d0f6bcf	327	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
f7d1572b WD	328
f7d1572b WD	329	/* Offset for data I/O */
6d0f6bcf	330	#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
f7d1572b WD	331
f7d1572b WD	332	/* Offset for normal register accesses */
6d0f6bcf	333	#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
f7d1572b WD	334
f7d1572b WD	335	/* Offset for alternate registers */
6d0f6bcf	336	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
f7d1572b WD	337
	338	/*-----------------------------------------------------------------------
	339	*
	340	*-----------------------------------------------------------------------
	341	*
	342	*/
6d0f6bcf	343	#define CONFIG_SYS_DER 0
f7d1572b WD	344
	345	/*
	346	* Init Memory Controller:
	347	*
	348	* BR0/1 and OR0/1 (FLASH)
	349	*/
	350
	351	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	352	#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
	353
	354	/* used to re-map FLASH both when starting from SRAM or FLASH:
	355	* restrict access enough to keep SRAM working (if any)
	356	* but not too much to meddle with FLASH accesses
	357	*/
6d0f6bcf JCPV	358	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	359	#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
f7d1572b WD	360
	361	/*
	362	* FLASH timing:
	363	*/
6d0f6bcf	364	#define CONFIG_SYS_OR_TIMING_FLASH (0x00000d24)
f7d1572b	365
6d0f6bcf JCPV	366	#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	367	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	368	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V )
f7d1572b	369
6d0f6bcf JCPV	370	#define CONFIG_SYS_BR1_PRELIM 0x00000081 /* Chip select for SDRAM (32 Bit, UPMA) */
	371	#define CONFIG_SYS_OR1_PRELIM 0xfc000a00
	372	#define CONFIG_SYS_BR2_PRELIM 0x80000001 /* Chip select for SRAM (32 Bit, GPCM) */
	373	#define CONFIG_SYS_OR2_PRELIM 0xfff00d24
	374	#define CONFIG_SYS_BR3_PRELIM 0x80600401 /* Chip select for Display (8 Bit, GPCM) */
	375	#define CONFIG_SYS_OR3_PRELIM 0xffff8f44
	376	#define CONFIG_SYS_BR4_PRELIM 0xc05108c1 /* Chip select for Interbus MPM (16 Bit, UPMB) */
	377	#define CONFIG_SYS_OR4_PRELIM 0xffff0300
	378	#define CONFIG_SYS_BR5_PRELIM 0xc0500401 /* Chip select for Interbus Status (8 Bit, GPCM) */
	379	#define CONFIG_SYS_OR5_PRELIM 0xffff8db0
f7d1572b WD	380
	381	/*
	382	* Memory Periodic Timer Prescaler
	383	*
	384	* The Divider for PTA (refresh timer) configuration is based on an
	385	* example SDRAM configuration (64 MBit, one bank). The adjustment to
	386	* the number of chip selects (NCS) and the actually needed refresh
	387	* rate is done by setting MPTPR.
	388	*
	389	* PTA is calculated from
	390	* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
	391	*
	392	* gclk CPU clock (not bus clock!)
	393	* Trefresh Refresh cycle * 4 (four word bursts used)
	394	*
	395	* 4096 Rows from SDRAM example configuration
	396	* 1000 factor s -> ms
	397	* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
	398	* 4 Number of refresh cycles per period
	399	* 64 Refresh cycle in ms per number of rows
	400	* --------------------------------------------
	401	* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
	402	*
	403	* 50 MHz => 50.000.000 / Divider = 98
	404	* 66 Mhz => 66.000.000 / Divider = 129
	405	* 80 Mhz => 80.000.000 / Divider = 156
	406	* 100 Mhz => 100.000.000 / Divider = 195
	407	*/
	408
6d0f6bcf JCPV	409	#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
6d0f6bcf JCPV	410	#define CONFIG_SYS_MAMR_PTA 98
f7d1572b WD	411
	412	/*
	413	* For 16 MBit, refresh rates could be 31.3 us
	414	* (= 64 ms / 2K = 125 / quad bursts).
	415	* For a simpler initialization, 15.6 us is used instead.
	416	*
6d0f6bcf JCPV	417	* #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
6d0f6bcf JCPV	418	* #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
f7d1572b	419	*/
6d0f6bcf JCPV	420	#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
6d0f6bcf JCPV	421	#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
f7d1572b WD	422
f7d1572b WD	423	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
6d0f6bcf JCPV	424	#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
6d0f6bcf JCPV	425	#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
f7d1572b WD	426
	427	/*
	428	* MAMR settings for SDRAM
	429	*/
	430
	431	/* 8 column SDRAM */
6d0f6bcf	432	#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
f7d1572b WD	433	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	434	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	435	/* 9 column SDRAM */
6d0f6bcf	436	#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
f7d1572b WD	437	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	438	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	439
6d0f6bcf JCPV	440	#define CONFIG_SYS_MAMR_VAL 0x30904114 /* for SDRAM */
6d0f6bcf JCPV	441	#define CONFIG_SYS_MBMR_VAL 0xff001111 /* for Interbus-MPM */
f7d1572b WD	442
	443	/*-----------------------------------------------------------------------
	444	* I2C stuff
	445	*/
	446
	447	/* enable I2C and select the hardware/software driver */
ea818dbb HS	448	#define CONFIG_SYS_I2C
	449	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
	450	#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
	451	#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
f7d1572b WD	452	/*
	453	* Software (bit-bang) I2C driver configuration
	454	*/
	455	#define PB_SCL 0x00000020 /* PB 26 */
	456	#define PB_SDA 0x00000010 /* PB 27 */
	457
	458	#define I2C_INIT (immr->im_cpm.cp_pbdir \|= PB_SCL)
	459	#define I2C_ACTIVE (immr->im_cpm.cp_pbdir \|= PB_SDA)
	460	#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
	461	#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
	462	#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SDA; \
	463	else immr->im_cpm.cp_pbdat &= ~PB_SDA
	464	#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SCL; \
	465	else immr->im_cpm.cp_pbdat &= ~PB_SCL
	466	#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
f7d1572b WD	467
	468	/*-----------------------------------------------------------------------
	469	* I2C EEPROM (24C164)
	470	*/
6d0f6bcf JCPV	471	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */
	472	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	473	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
	474	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
f7d1572b	475
f7d1572b WD	476	#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
	477	#define FEC_ENET
	478	#define CONFIG_MII
0f3ba7e9	479	#define CONFIG_MII_INIT 1
6d0f6bcf	480	#define CONFIG_SYS_DISCOVER_PHY 1
f7d1572b WD	481
f7d1572b WD	482	#endif /* __CONFIG_H */