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5894ca00 | 1 | /* |
e8a92932 MY |
2 | * Copyright (C) 2012-2015 Panasonic Corporation |
3 | * Copyright (C) 2015-2016 Socionext Inc. | |
4 | * Author: Masahiro Yamada <yamada.masahiro@socionext.com> | |
5894ca00 MY |
5 | * |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
a187559e | 9 | /* U-Boot - Common settings for UniPhier Family */ |
5894ca00 MY |
10 | |
11 | #ifndef __CONFIG_UNIPHIER_COMMON_H__ | |
12 | #define __CONFIG_UNIPHIER_COMMON_H__ | |
13 | ||
928f3248 | 14 | #define CONFIG_ARMV7_PSCI_1_0 |
e8a92932 | 15 | |
233e42a9 MY |
16 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
17 | ||
f5d0b9b2 MY |
18 | #define CONFIG_SMC911X |
19 | ||
d7728aa4 MY |
20 | /* dummy: referenced by examples/standalone/smc911x_eeprom.c */ |
21 | #define CONFIG_SMC911X_BASE 0 | |
5894ca00 MY |
22 | #define CONFIG_SMC911X_32_BIT |
23 | ||
5894ca00 MY |
24 | /*----------------------------------------------------------------------- |
25 | * MMU and Cache Setting | |
26 | *----------------------------------------------------------------------*/ | |
27 | ||
28 | /* Comment out the following to enable L1 cache */ | |
29 | /* #define CONFIG_SYS_ICACHE_OFF */ | |
30 | /* #define CONFIG_SYS_DCACHE_OFF */ | |
31 | ||
5894ca00 MY |
32 | #define CONFIG_DISPLAY_CPUINFO |
33 | #define CONFIG_DISPLAY_BOARDINFO | |
08fda258 | 34 | #define CONFIG_MISC_INIT_F |
84ccd791 | 35 | #define CONFIG_BOARD_EARLY_INIT_F |
7a3620b2 | 36 | #define CONFIG_BOARD_EARLY_INIT_R |
5894ca00 MY |
37 | #define CONFIG_BOARD_LATE_INIT |
38 | ||
39 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) | |
40 | ||
41 | #define CONFIG_TIMESTAMP | |
42 | ||
43 | /* FLASH related */ | |
44 | #define CONFIG_MTD_DEVICE | |
45 | ||
46 | /* | |
47 | * uncomment the following to disable FLASH related code. | |
48 | */ | |
49 | /* #define CONFIG_SYS_NO_FLASH */ | |
50 | ||
51 | #define CONFIG_FLASH_CFI_DRIVER | |
52 | #define CONFIG_SYS_FLASH_CFI | |
53 | ||
54 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
55 | #define CONFIG_SYS_MONITOR_BASE 0 | |
d085ecd6 | 56 | #define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */ |
5894ca00 MY |
57 | #define CONFIG_SYS_FLASH_BASE 0 |
58 | ||
59 | /* | |
60 | * flash_toggle does not work for out supoort card. | |
61 | * We need to use flash_status_poll. | |
62 | */ | |
63 | #define CONFIG_SYS_CFI_FLASH_STATUS_POLL | |
64 | ||
65 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
66 | ||
9879842c | 67 | #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 |
5894ca00 MY |
68 | |
69 | /* serial console configuration */ | |
70 | #define CONFIG_BAUDRATE 115200 | |
71 | ||
9d0c2ceb | 72 | #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64) |
5894ca00 MY |
73 | #define CONFIG_USE_ARCH_MEMSET |
74 | #define CONFIG_USE_ARCH_MEMCPY | |
75 | #endif | |
76 | ||
77 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
78 | ||
79 | #define CONFIG_CMDLINE_EDITING /* add command line history */ | |
5894ca00 MY |
80 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
81 | /* Print Buffer Size */ | |
82 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
83 | #define CONFIG_SYS_MAXARGS 16 /* max number of command */ | |
84 | /* Boot Argument Buffer Size */ | |
85 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
86 | ||
87 | #define CONFIG_CONS_INDEX 1 | |
88 | ||
aa8a9348 | 89 | /* #define CONFIG_ENV_IS_NOWHERE */ |
5894ca00 | 90 | /* #define CONFIG_ENV_IS_IN_NAND */ |
aa8a9348 MY |
91 | #define CONFIG_ENV_IS_IN_MMC |
92 | #define CONFIG_ENV_OFFSET 0x80000 | |
5894ca00 | 93 | #define CONFIG_ENV_SIZE 0x2000 |
5894ca00 MY |
94 | /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ |
95 | ||
aa8a9348 MY |
96 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
97 | #define CONFIG_SYS_MMC_ENV_PART 1 | |
98 | ||
9d0c2ceb | 99 | #ifdef CONFIG_ARM64 |
50862a51 | 100 | #define CPU_RELEASE_ADDR 0x80000000 |
9d0c2ceb MY |
101 | #define COUNTER_FREQUENCY 50000000 |
102 | #define CONFIG_GICV3 | |
103 | #define GICD_BASE 0x5fe00000 | |
667dbcd0 MY |
104 | #if defined(CONFIG_ARCH_UNIPHIER_LD11) |
105 | #define GICR_BASE 0x5fe40000 | |
106 | #elif defined(CONFIG_ARCH_UNIPHIER_LD20) | |
9d0c2ceb | 107 | #define GICR_BASE 0x5fe80000 |
667dbcd0 | 108 | #endif |
9d0c2ceb | 109 | #else |
5894ca00 MY |
110 | /* Time clock 1MHz */ |
111 | #define CONFIG_SYS_TIMER_RATE 1000000 | |
9d0c2ceb MY |
112 | #endif |
113 | ||
5894ca00 | 114 | |
5894ca00 MY |
115 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
116 | #define CONFIG_SYS_NAND_MAX_CHIPS 2 | |
117 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
118 | ||
119 | #define CONFIG_NAND_DENALI_ECC_SIZE 1024 | |
120 | ||
ea65c980 | 121 | #ifdef CONFIG_ARCH_UNIPHIER_SLD3 |
3365b4eb MY |
122 | #define CONFIG_SYS_NAND_REGS_BASE 0xf8100000 |
123 | #define CONFIG_SYS_NAND_DATA_BASE 0xf8000000 | |
124 | #else | |
5894ca00 MY |
125 | #define CONFIG_SYS_NAND_REGS_BASE 0x68100000 |
126 | #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 | |
3365b4eb | 127 | #endif |
5894ca00 MY |
128 | |
129 | #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) | |
130 | ||
131 | #define CONFIG_SYS_NAND_USE_FLASH_BBT | |
132 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
133 | ||
495deb44 | 134 | /* USB */ |
495deb44 | 135 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
53c45d4e | 136 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4 |
495deb44 MY |
137 | #define CONFIG_FAT_WRITE |
138 | #define CONFIG_DOS_PARTITION | |
139 | ||
4aceb3f8 | 140 | /* SD/MMC */ |
a55d9fee | 141 | #define CONFIG_SUPPORT_EMMC_BOOT |
4aceb3f8 MY |
142 | #define CONFIG_GENERIC_MMC |
143 | ||
5894ca00 MY |
144 | /* memtest works on */ |
145 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
146 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) | |
147 | ||
5894ca00 MY |
148 | /* |
149 | * Network Configuration | |
150 | */ | |
5894ca00 MY |
151 | #define CONFIG_SERVERIP 192.168.11.1 |
152 | #define CONFIG_IPADDR 192.168.11.10 | |
153 | #define CONFIG_GATEWAYIP 192.168.11.1 | |
154 | #define CONFIG_NETMASK 255.255.255.0 | |
155 | ||
156 | #define CONFIG_LOADADDR 0x84000000 | |
157 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
5894ca00 MY |
158 | |
159 | #define CONFIG_CMDLINE_EDITING /* add command line history */ | |
160 | ||
161 | #define CONFIG_BOOTCOMMAND "run $bootmode" | |
162 | ||
163 | #define CONFIG_ROOTPATH "/nfs/root/path" | |
164 | #define CONFIG_NFSBOOTCOMMAND \ | |
165 | "setenv bootargs $bootargs root=/dev/nfs rw " \ | |
166 | "nfsroot=$serverip:$rootpath " \ | |
167 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ | |
d566f754 | 168 | "run __nfsboot" |
5894ca00 | 169 | |
421376ae MY |
170 | #ifdef CONFIG_FIT |
171 | #define CONFIG_BOOTFILE "fitImage" | |
172 | #define LINUXBOOT_ENV_SETTINGS \ | |
173 | "fit_addr=0x00100000\0" \ | |
174 | "fit_addr_r=0x84100000\0" \ | |
175 | "fit_size=0x00f00000\0" \ | |
5451b777 | 176 | "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \ |
421376ae | 177 | "bootm $fit_addr\0" \ |
5451b777 | 178 | "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \ |
e037db0c | 179 | "bootm $fit_addr_r\0" \ |
5451b777 | 180 | "tftpboot=tftpboot $fit_addr_r $bootfile &&" \ |
d566f754 MY |
181 | "bootm $fit_addr_r\0" \ |
182 | "__nfsboot=run tftpboot\0" | |
421376ae | 183 | #else |
9d0c2ceb | 184 | #ifdef CONFIG_ARM64 |
9d0c2ceb MY |
185 | #define CONFIG_BOOTFILE "Image" |
186 | #define LINUXBOOT_CMD "booti" | |
187 | #define KERNEL_ADDR_R "kernel_addr_r=0x80080000\0" | |
188 | #define KERNEL_SIZE "kernel_size=0x00c00000\0" | |
189 | #define RAMDISK_ADDR "ramdisk_addr=0x00e00000\0" | |
190 | #else | |
89835b35 | 191 | #define CONFIG_BOOTFILE "zImage" |
9d0c2ceb MY |
192 | #define LINUXBOOT_CMD "bootz" |
193 | #define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0" | |
194 | #define KERNEL_SIZE "kernel_size=0x00800000\0" | |
195 | #define RAMDISK_ADDR "ramdisk_addr=0x00a00000\0" | |
196 | #endif | |
421376ae MY |
197 | #define LINUXBOOT_ENV_SETTINGS \ |
198 | "fdt_addr=0x00100000\0" \ | |
199 | "fdt_addr_r=0x84100000\0" \ | |
200 | "fdt_size=0x00008000\0" \ | |
201 | "kernel_addr=0x00200000\0" \ | |
9d0c2ceb MY |
202 | KERNEL_ADDR_R \ |
203 | KERNEL_SIZE \ | |
204 | RAMDISK_ADDR \ | |
421376ae MY |
205 | "ramdisk_addr_r=0x84a00000\0" \ |
206 | "ramdisk_size=0x00600000\0" \ | |
e037db0c | 207 | "ramdisk_file=rootfs.cpio.uboot\0" \ |
cd5d9565 | 208 | "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \ |
9d0c2ceb | 209 | LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ |
cd5d9565 | 210 | "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \ |
b75e072c MY |
211 | "setexpr kernel_size $kernel_size / 4 &&" \ |
212 | "cp $kernel_addr $kernel_addr_r $kernel_size &&" \ | |
cd5d9565 MY |
213 | "setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \ |
214 | "setexpr fdt_addr_r $nor_base + $fdt_addr &&" \ | |
215 | "run boot_common\0" \ | |
216 | "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ | |
421376ae MY |
217 | "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \ |
218 | "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \ | |
cd5d9565 MY |
219 | "run boot_common\0" \ |
220 | "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \ | |
e037db0c MY |
221 | "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ |
222 | "tftpboot $fdt_addr_r $fdt_file &&" \ | |
d566f754 MY |
223 | "run boot_common\0" \ |
224 | "__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \ | |
d566f754 MY |
225 | "tftpboot $fdt_addr_r $fdt_file &&" \ |
226 | "setenv ramdisk_addr_r - &&" \ | |
cd5d9565 | 227 | "run boot_common\0" |
421376ae MY |
228 | #endif |
229 | ||
230 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
231 | "netdev=eth0\0" \ | |
232 | "verify=n\0" \ | |
90a6e929 | 233 | "nor_base=0x42000000\0" \ |
61a4f5bd MY |
234 | "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \ |
235 | "tftpboot $tmp_addr u-boot-spl.bin &&" \ | |
236 | "setexpr tmp_addr $nor_base + 0x60000 &&" \ | |
237 | "tftpboot $tmp_addr u-boot.bin\0" \ | |
c231c436 MY |
238 | "emmcupdate=mmcsetn &&" \ |
239 | "mmc partconf $mmc_first_dev 0 1 1 &&" \ | |
c231c436 MY |
240 | "tftpboot u-boot-spl.bin &&" \ |
241 | "mmc write $loadaddr 0 80 &&" \ | |
d085ecd6 | 242 | "tftpboot u-boot.bin &&" \ |
c231c436 | 243 | "mmc write $loadaddr 80 780\0" \ |
421376ae | 244 | "nandupdate=nand erase 0 0x00100000 &&" \ |
3cb9abc9 | 245 | "tftpboot u-boot-spl.bin &&" \ |
421376ae | 246 | "nand write $loadaddr 0 0x00010000 &&" \ |
d085ecd6 | 247 | "tftpboot u-boot.bin &&" \ |
421376ae | 248 | "nand write $loadaddr 0x00010000 0x000f0000\0" \ |
421376ae | 249 | LINUXBOOT_ENV_SETTINGS |
5894ca00 | 250 | |
17bd4a21 MY |
251 | #define CONFIG_SYS_BOOTMAPSZ 0x20000000 |
252 | ||
cf88affa | 253 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
5894ca00 | 254 | #define CONFIG_NR_DRAM_BANKS 2 |
23869698 MY |
255 | /* for LD20; the last 64 byte is used for dynamic DDR PHY training */ |
256 | #define CONFIG_SYS_MEM_TOP_HIDE 64 | |
5894ca00 | 257 | |
9d0c2ceb MY |
258 | #if defined(CONFIG_ARM64) |
259 | #define CONFIG_SPL_TEXT_BASE 0x30000000 | |
260 | #elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \ | |
261 | defined(CONFIG_ARCH_UNIPHIER_LD4) || \ | |
ea65c980 | 262 | defined(CONFIG_ARCH_UNIPHIER_SLD8) |
f5d0b9b2 | 263 | #define CONFIG_SPL_TEXT_BASE 0x00040000 |
323d1f9d | 264 | #else |
f5d0b9b2 MY |
265 | #define CONFIG_SPL_TEXT_BASE 0x00100000 |
266 | #endif | |
267 | ||
667dbcd0 MY |
268 | #if defined(CONFIG_ARCH_UNIPHIER_LD11) |
269 | #define CONFIG_SPL_STACK (0x30014c00) | |
270 | #elif defined(CONFIG_ARCH_UNIPHIER_LD20) | |
9d0c2ceb MY |
271 | #define CONFIG_SPL_STACK (0x3001c000) |
272 | #else | |
755c7d9a | 273 | #define CONFIG_SPL_STACK (0x00100000) |
9d0c2ceb | 274 | #endif |
8cddc279 | 275 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) |
5894ca00 | 276 | |
a286039b MY |
277 | #define CONFIG_PANIC_HANG |
278 | ||
5894ca00 | 279 | #define CONFIG_SPL_FRAMEWORK |
499785b9 | 280 | #define CONFIG_SPL_SERIAL_SUPPORT |
cbbc2d80 | 281 | #define CONFIG_SPL_NOR_SUPPORT |
adb3928f MY |
282 | #ifdef CONFIG_ARM64 |
283 | #define CONFIG_SPL_BOARD_LOAD_IMAGE | |
284 | #else | |
5894ca00 | 285 | #define CONFIG_SPL_NAND_SUPPORT |
a55d9fee | 286 | #define CONFIG_SPL_MMC_SUPPORT |
9d0c2ceb | 287 | #endif |
5894ca00 | 288 | |
5894ca00 MY |
289 | #define CONFIG_SPL_BOARD_INIT |
290 | ||
291 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000 | |
cbbc2d80 | 292 | |
d085ecd6 MY |
293 | /* subtract sizeof(struct image_header) */ |
294 | #define CONFIG_SYS_UBOOT_BASE (0x60000 - 0x40) | |
a55d9fee | 295 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 |
5894ca00 | 296 | |
d085ecd6 | 297 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" |
6a3cffe8 | 298 | #define CONFIG_SPL_MAX_FOOTPRINT 0x10000 |
86c3345a | 299 | #define CONFIG_SPL_MAX_SIZE 0x10000 |
667dbcd0 MY |
300 | #if defined(CONFIG_ARCH_UNIPHIER_LD11) |
301 | #define CONFIG_SPL_BSS_START_ADDR 0x30012000 | |
302 | #elif defined(CONFIG_ARCH_UNIPHIER_LD20) | |
9d0c2ceb | 303 | #define CONFIG_SPL_BSS_START_ADDR 0x30016000 |
667dbcd0 | 304 | #endif |
9d0c2ceb | 305 | #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 |
6a3cffe8 | 306 | |
5894ca00 | 307 | #endif /* __CONFIG_UNIPHIER_COMMON_H__ */ |