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c609719b WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * (C) Copyright 2002 | |
6 | * Gregory E. Allen, gallen@arlut.utexas.edu | |
7 | * Matthew E. Karger, karger@arlut.utexas.edu | |
8 | * Applied Research Laboratories, The University of Texas at Austin | |
9 | * | |
10 | * See file CREDITS for list of people who contributed to this | |
11 | * project. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | /* | |
30 | * | |
31 | * Configuration settings for the utx8245 board. | |
32 | * | |
33 | */ | |
34 | ||
35 | /* ------------------------------------------------------------------------- */ | |
36 | ||
37 | /* | |
38 | * board/config.h - configuration options, board specific | |
39 | */ | |
40 | ||
41 | #ifndef __CONFIG_H | |
42 | #define __CONFIG_H | |
43 | ||
44 | /* | |
45 | * High Level Configuration Options | |
46 | * (easy to change) | |
47 | */ | |
48 | ||
49 | #define CONFIG_MPC824X 1 | |
50 | #define CONFIG_MPC8245 1 | |
51 | #define CONFIG_UTX8245 1 | |
52 | #define DEBUG 1 | |
53 | ||
7a8e9bed WD |
54 | #define CONFIG_IDENT_STRING " [UTX5] " |
55 | ||
c609719b WD |
56 | #define CONFIG_CONS_INDEX 1 |
57 | #define CONFIG_BAUDRATE 57600 | |
58 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
59 | ||
7a8e9bed | 60 | #define CONFIG_BOOTDELAY 2 |
c37207d7 | 61 | #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay |
7a8e9bed | 62 | #define CONFIG_BOOTCOMMAND "run nfsboot" /* autoboot command */ |
c609719b | 63 | #define CONFIG_BOOTARGS "root=/dev/ram console=ttyS0,57600" /* RAMdisk */ |
7a8e9bed WD |
64 | #define CONFIG_ETHADDR 00:AA:00:14:00:05 /* UTX5 */ |
65 | #define CONFIG_SERVERIP 10.8.17.105 /* Spree */ | |
66 | #define CFG_TFTP_LOADADDR 10000 | |
67 | ||
68 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
69 | "kernel_addr=FFA00000\0" \ | |
70 | "ramdisk_addr=FF800000\0" \ | |
71 | "u-boot_startaddr=FFB00000\0" \ | |
72 | "u-boot_endaddr=FFB2FFFF\0" \ | |
fe126d8b WD |
73 | "nfsargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/nfs rw \ |
74 | nfsroot=${nfsrootip}:${rootpath} ip=dhcp\0" \ | |
75 | "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram0\0" \ | |
76 | "smargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/mtdblock1 ro\0" \ | |
77 | "fwargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/sda2 ro\0" \ | |
78 | "nfsboot=run nfsargs;bootm ${kernel_addr}\0" \ | |
79 | "ramboot=run ramargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
80 | "smboot=run smargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
81 | "fwboot=run fwargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
82 | "update_u-boot=tftp ${loadaddr} /bdi2000/u-boot.bin;protect off \ | |
83 | ${u-boot_startaddr} ${u-boot_endaddr};era ${u-boot_startaddr} \ | |
84 | ${u-boot_endaddr};cp.b ${loadaddr} ${u-boot_startaddr} ${filesize};\ | |
85 | protect on ${u-boot_startaddr} ${u-boot_endaddr}" | |
7a8e9bed | 86 | |
c609719b WD |
87 | #define CONFIG_ENV_OVERWRITE |
88 | ||
6c18eb98 | 89 | |
079a136c JL |
90 | /* |
91 | * BOOTP options | |
92 | */ | |
93 | #define CONFIG_BOOTP_BOOTFILESIZE | |
94 | #define CONFIG_BOOTP_BOOTPATH | |
95 | #define CONFIG_BOOTP_GATEWAY | |
96 | #define CONFIG_BOOTP_HOSTNAME | |
97 | ||
98 | ||
6c18eb98 JL |
99 | /* |
100 | * Command line configuration. | |
c609719b | 101 | */ |
6c18eb98 JL |
102 | #include <config_cmd_default.h> |
103 | ||
104 | #define CONFIG_CMD_BDI | |
105 | #define CONFIG_CMD_PCI | |
106 | #define CONFIG_CMD_FLASH | |
107 | #define CONFIG_CMD_MEMORY | |
108 | #define CONFIG_CMD_ENV | |
109 | #define CONFIG_CMD_CONSOLE | |
110 | #define CONFIG_CMD_LOADS | |
111 | #define CONFIG_CMD_LOADB | |
112 | #define CONFIG_CMD_IMI | |
113 | #define CONFIG_CMD_CACHE | |
114 | #define CONFIG_CMD_REGINFO | |
115 | #define CONFIG_CMD_NET | |
116 | #define CONFIG_CMD_DHCP | |
117 | #define CONFIG_CMD_I2C | |
118 | #define CONFIG_CMD_DATE | |
c609719b WD |
119 | |
120 | ||
121 | /* | |
122 | * Miscellaneous configurable options | |
123 | */ | |
7a8e9bed WD |
124 | #define CFG_LONGHELP /* undef to save memory */ |
125 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
126 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
c609719b WD |
127 | |
128 | /* Print Buffer Size */ | |
129 | #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) | |
130 | ||
131 | #define CFG_MAXARGS 16 /* max number of command args */ | |
132 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
133 | #define CFG_LOAD_ADDR 0x00100000 /* Default load address */ | |
134 | ||
135 | ||
136 | /*----------------------------------------------------------------------- | |
137 | * PCI configuration | |
138 | *----------------------------------------------------------------------- | |
139 | */ | |
140 | #define CONFIG_PCI /* include pci support */ | |
141 | #undef CONFIG_PCI_PNP | |
142 | #define CONFIG_PCI_SCAN_SHOW | |
143 | #define CONFIG_NET_MULTI | |
144 | #define CONFIG_EEPRO100 | |
53cf9435 | 145 | #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
7a8e9bed WD |
146 | #define CONFIG_EEPRO100_SROM_WRITE |
147 | ||
148 | #define PCI_ENET0_IOADDR 0xF0000000 | |
149 | #define PCI_ENET0_MEMADDR 0xF0000000 | |
c609719b | 150 | |
7a8e9bed WD |
151 | #define PCI_FIREWIRE_IOADDR 0xF1000000 |
152 | #define PCI_FIREWIRE_MEMADDR 0xF1000000 | |
153 | /* | |
154 | #define PCI_ENET0_IOADDR 0xFE000000 | |
c609719b | 155 | #define PCI_ENET0_MEMADDR 0x80000000 |
7a8e9bed | 156 | |
c609719b WD |
157 | #define PCI_FIREWIRE_IOADDR 0x81000000 |
158 | #define PCI_FIREWIRE_MEMADDR 0x81000000 | |
7a8e9bed | 159 | */ |
c609719b WD |
160 | |
161 | /*----------------------------------------------------------------------- | |
162 | * Start addresses for the final memory configuration | |
163 | * (Set up by the startup code) | |
164 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
165 | */ | |
166 | #define CFG_SDRAM_BASE 0x00000000 | |
7a8e9bed WD |
167 | #define CFG_MAX_RAM_SIZE 0x10000000 /* 256MB */ |
168 | /*#define CFG_VERY_BIG_RAM 1 */ | |
c609719b | 169 | |
7a8e9bed WD |
170 | /* FLASH_BASE is FF800000, with 4MB on RCS0, but the reset vector |
171 | * is actually located at FFF00100. Therefore, U-Boot is | |
172 | * physically located at 0xFFB0_0000, but is also mirrored at | |
173 | * 0xFFF0_0000. | |
c609719b WD |
174 | */ |
175 | #define CFG_RESET_ADDRESS 0xFFF00100 | |
176 | ||
177 | #define CFG_EUMB_ADDR 0xFC000000 | |
178 | ||
179 | #define CFG_MONITOR_BASE TEXT_BASE | |
180 | ||
181 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
182 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
183 | ||
184 | /*#define CFG_DRAM_TEST 1 */ | |
185 | #define CFG_MEMTEST_START 0x00003000 /* memtest works on 0...256 MB */ | |
7a8e9bed | 186 | #define CFG_MEMTEST_END 0x0ff8ffa7 /* in SDRAM, skips exception */ |
c609719b WD |
187 | /* vectors and U-Boot */ |
188 | ||
189 | ||
190 | /*-------------------------------------------------------------------- | |
191 | * Definitions for initial stack pointer and data area | |
192 | *------------------------------------------------------------------*/ | |
7a8e9bed | 193 | #define CFG_INIT_DATA_SIZE 128 /* Size in bytes reserved for */ |
c609719b WD |
194 | /* initial data */ |
195 | #define CFG_INIT_RAM_ADDR 0x40000000 | |
196 | #define CFG_INIT_RAM_END 0x1000 | |
7a8e9bed WD |
197 | #define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) |
198 | #define CFG_GBL_DATA_SIZE 128 | |
c609719b WD |
199 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
200 | ||
201 | /*-------------------------------------------------------------------- | |
202 | * NS16550 Configuration | |
203 | *------------------------------------------------------------------*/ | |
204 | #define CFG_NS16550 | |
205 | #define CFG_NS16550_SERIAL | |
206 | ||
207 | #define CFG_NS16550_REG_SIZE 1 | |
208 | ||
7a8e9bed WD |
209 | #if (CONFIG_CONS_INDEX == 1 || CONFIG_CONS_INDEX == 2) |
210 | # define CFG_NS16550_CLK get_bus_freq(0) | |
211 | #else | |
212 | # define CFG_NS16550_CLK 33000000 | |
213 | #endif | |
c609719b WD |
214 | |
215 | #define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) | |
216 | #define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600) | |
7a8e9bed WD |
217 | #define CFG_NS16550_COM3 0xFF000000 |
218 | #define CFG_NS16550_COM4 0xFF000008 | |
c609719b WD |
219 | |
220 | /*-------------------------------------------------------------------- | |
221 | * Low Level Configuration Settings | |
222 | * (address mappings, register initial values, etc.) | |
223 | * You should know what you are doing if you make changes here. | |
224 | * For the detail description refer to the MPC8240 user's manual. | |
225 | *------------------------------------------------------------------*/ | |
226 | ||
227 | #define CONFIG_SYS_CLK_FREQ 33000000 | |
228 | #define CFG_HZ 1000 | |
229 | ||
7a8e9bed WD |
230 | /*#define CFG_ETH_DEV_FN 0x7800 */ |
231 | /*#define CFG_ETH_IOBASE 0x00104000 */ | |
232 | ||
233 | /*-------------------------------------------------------------------- | |
234 | * I2C Configuration | |
235 | *------------------------------------------------------------------*/ | |
236 | #if 1 | |
237 | #define CONFIG_HARD_I2C 1 /* To enable I2C support */ | |
238 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
239 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
240 | #define CFG_I2C_SLAVE 0x7F | |
241 | #endif | |
c609719b | 242 | |
7a8e9bed WD |
243 | #define CONFIG_RTC_PCF8563 1 /* enable I2C support for */ |
244 | /* Philips PCF8563 RTC */ | |
245 | #define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ | |
c609719b WD |
246 | |
247 | /*-------------------------------------------------------------------- | |
248 | * Memory Control Configuration Register values | |
249 | * - see sec. 4.12 of MPC8245 UM | |
250 | *------------------------------------------------------------------*/ | |
251 | ||
7a8e9bed | 252 | /**** MCCR1 ****/ |
c609719b | 253 | #define CFG_ROMNAL 0 |
7a8e9bed WD |
254 | #define CFG_ROMFAL 10 /* (tacc=70ns)*mem_freq - 2, |
255 | mem_freq = 100MHz */ | |
256 | ||
257 | #define CFG_BANK7_ROW 0 /* SDRAM bank 7-0 row address */ | |
53677ef1 | 258 | #define CFG_BANK6_ROW 0 /* bit count */ |
c609719b | 259 | #define CFG_BANK5_ROW 0 |
7a8e9bed WD |
260 | #define CFG_BANK4_ROW 0 |
261 | #define CFG_BANK3_ROW 0 | |
262 | #define CFG_BANK2_ROW 0 | |
263 | #define CFG_BANK1_ROW 2 | |
264 | #define CFG_BANK0_ROW 2 | |
c609719b | 265 | |
7a8e9bed | 266 | /**** MCCR2, refresh interval clock cycles ****/ |
c609719b WD |
267 | #define CFG_REFINT 480 /* 33 MHz SDRAM clock was 480 */ |
268 | ||
7a8e9bed | 269 | /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ |
c609719b WD |
270 | #define CFG_BSTOPRE 1023 /* burst to precharge[0..9], */ |
271 | /* sets open page interval */ | |
272 | ||
7a8e9bed WD |
273 | /**** MCCR3 ****/ |
274 | #define CFG_REFREC 7 /* Refresh to activate interval, trc */ | |
c609719b | 275 | |
7a8e9bed | 276 | /**** MCCR4 ****/ |
c609719b | 277 | #define CFG_PRETOACT 2 /* trp */ |
7a8e9bed | 278 | #define CFG_ACTTOPRE 7 /* trcd + (burst length - 1) + trdl */ |
c609719b WD |
279 | #define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ |
280 | #define CFG_SDMODE_WRAP 0 /* SDMODE wrap type, sequential */ | |
53677ef1 | 281 | #define CFG_ACTORW 2 /* trcd min */ |
c609719b WD |
282 | #define CFG_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */ |
283 | #define CFG_REGISTERD_TYPE_BUFFER 1 | |
7a8e9bed | 284 | #define CFG_EXTROM 0 /* we don't need extended ROM space */ |
c609719b WD |
285 | #define CFG_REGDIMM 0 |
286 | ||
287 | /* calculate according to formula in sec. 6-22 of 8245 UM */ | |
288 | #define CFG_PGMAX 50 /* how long the 8245 retains the */ | |
289 | /* currently accessed page in memory */ | |
290 | /* was 45 */ | |
291 | ||
292 | #define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note */ | |
7a8e9bed | 293 | /* bits 7,6, and 3-0 MUST be 0 */ |
c609719b | 294 | |
7a8e9bed | 295 | #if 0 |
c609719b | 296 | #define CFG_DLL_MAX_DELAY 0x04 |
7a8e9bed WD |
297 | #else |
298 | #define CFG_DLL_MAX_DELAY 0 | |
299 | #endif | |
300 | #if 0 /* need for 33MHz SDRAM */ | |
c609719b | 301 | #define CFG_DLL_EXTEND 0x80 |
7a8e9bed WD |
302 | #else |
303 | #define CFG_DLL_EXTEND 0 | |
304 | #endif | |
c609719b WD |
305 | #define CFG_PCI_HOLD_DEL 0x20 |
306 | ||
307 | ||
308 | /* Memory bank settings. | |
309 | * Only bits 20-29 are actually used from these values to set the | |
310 | * start/end addresses. The upper two bits will always be 0, and the lower | |
311 | * 20 bits will be 0x00000 for a start address, or 0xfffff for an end | |
312 | * address. Refer to the MPC8245 user manual. | |
313 | */ | |
314 | ||
315 | #define CFG_BANK0_START 0x00000000 | |
316 | #define CFG_BANK0_END (CFG_MAX_RAM_SIZE/2 - 1) | |
317 | #define CFG_BANK0_ENABLE 1 | |
318 | #define CFG_BANK1_START CFG_MAX_RAM_SIZE/2 | |
319 | #define CFG_BANK1_END (CFG_MAX_RAM_SIZE - 1) | |
320 | #define CFG_BANK1_ENABLE 1 | |
321 | #define CFG_BANK2_START 0x3ff00000 /* not available in this design */ | |
322 | #define CFG_BANK2_END 0x3fffffff | |
323 | #define CFG_BANK2_ENABLE 0 | |
324 | #define CFG_BANK3_START 0x3ff00000 | |
325 | #define CFG_BANK3_END 0x3fffffff | |
326 | #define CFG_BANK3_ENABLE 0 | |
327 | #define CFG_BANK4_START 0x3ff00000 | |
328 | #define CFG_BANK4_END 0x3fffffff | |
329 | #define CFG_BANK4_ENABLE 0 | |
330 | #define CFG_BANK5_START 0x3ff00000 | |
331 | #define CFG_BANK5_END 0x3fffffff | |
332 | #define CFG_BANK5_ENABLE 0 | |
333 | #define CFG_BANK6_START 0x3ff00000 | |
334 | #define CFG_BANK6_END 0x3fffffff | |
335 | #define CFG_BANK6_ENABLE 0 | |
336 | #define CFG_BANK7_START 0x3ff00000 | |
337 | #define CFG_BANK7_END 0x3fffffff | |
338 | #define CFG_BANK7_ENABLE 0 | |
339 | ||
7a8e9bed WD |
340 | /*--------------------------------------------------------------------*/ |
341 | /* 4.4 - Output Driver Control Register */ | |
342 | /*--------------------------------------------------------------------*/ | |
c609719b WD |
343 | #define CFG_ODCR 0xe5 |
344 | ||
7a8e9bed WD |
345 | /*--------------------------------------------------------------------*/ |
346 | /* 4.8 - Error Handling Registers */ | |
347 | /*-------------------------------CFG_SDMODE_BURSTLEN-------------------------------------*/ | |
c609719b WD |
348 | #define CFG_ERRENR1 0x11 /* enable SDRAM refresh overflow error */ |
349 | ||
350 | /* SDRAM 0-256 MB */ | |
351 | #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
7a8e9bed | 352 | /*#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) */ |
c609719b WD |
353 | #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
354 | ||
355 | /* stack in dcache */ | |
356 | #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) | |
357 | #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
358 | ||
7a8e9bed WD |
359 | |
360 | #define CFG_IBAT2L (CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) | |
361 | #define CFG_IBAT2U (CFG_SDRAM_BASE + 0x10000000| BATU_BL_256M | BATU_VS | BATU_VP) | |
362 | ||
c609719b | 363 | /* PCI memory */ |
7a8e9bed WD |
364 | /*#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) */ |
365 | /*#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) */ | |
c609719b | 366 | |
7a8e9bed | 367 | /*Flash, config addrs, etc. */ |
c609719b WD |
368 | #define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
369 | #define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
370 | ||
371 | #define CFG_DBAT0L CFG_IBAT0L | |
372 | #define CFG_DBAT0U CFG_IBAT0U | |
373 | #define CFG_DBAT1L CFG_IBAT1L | |
374 | #define CFG_DBAT1U CFG_IBAT1U | |
375 | #define CFG_DBAT2L CFG_IBAT2L | |
376 | #define CFG_DBAT2U CFG_IBAT2U | |
377 | #define CFG_DBAT3L CFG_IBAT3L | |
378 | #define CFG_DBAT3U CFG_IBAT3U | |
379 | ||
380 | /* | |
381 | * For booting Linux, the board info and command line data | |
382 | * have to be in the first 8 MB of memory, since this is | |
383 | * the maximum mapped by the Linux kernel during initialization. | |
384 | */ | |
385 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
386 | ||
387 | /*----------------------------------------------------------------------- | |
7a8e9bed WD |
388 | * FLASH organization |
389 | *----------------------------------------------------------------------*/ | |
c609719b | 390 | #define CFG_FLASH_BASE 0xFF800000 |
7a8e9bed | 391 | #define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ |
c609719b | 392 | |
7a8e9bed WD |
393 | /* NOTE: environment is not EMBEDDED in the u-boot code. |
394 | It's stored in flash in its own separate sector. */ | |
c609719b WD |
395 | #define CFG_ENV_IS_IN_FLASH 1 |
396 | ||
7a8e9bed WD |
397 | #if 1 /* AMD AM29LV033C */ |
398 | #define CFG_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */ | |
399 | #define CFG_ENV_ADDR 0xFFBF0000 /* flash sector SA63 */ | |
400 | #define CFG_ENV_SECT_SIZE (64*1024) /* Size of the Environment Sector */ | |
401 | #else /* AMD AM29LV116D */ | |
402 | #define CFG_MAX_FLASH_SECT 35 /* Max number of sectors in one bank */ | |
c609719b | 403 | #define CFG_ENV_ADDR 0xFF9FA000 /* flash sector SA33 */ |
7a8e9bed WD |
404 | #define CFG_ENV_SECT_SIZE (8*1024) /* Size of the Environment Sector */ |
405 | #endif /* #if */ | |
406 | ||
407 | #define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* Size of the Environment */ | |
c609719b | 408 | #define CFG_ENV_OFFSET 0 /* starting right at the beginning */ |
c609719b | 409 | |
7a8e9bed WD |
410 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
411 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
c609719b WD |
412 | |
413 | #if CFG_MONITOR_BASE >= CFG_FLASH_BASE | |
414 | #undef CFG_RAMBOOT | |
415 | #else | |
416 | #define CFG_RAMBOOT | |
417 | #endif | |
418 | ||
419 | ||
420 | /*----------------------------------------------------------------------- | |
421 | * Cache Configuration | |
422 | */ | |
423 | #define CFG_CACHELINE_SIZE 32 | |
6c18eb98 | 424 | #if defined(CONFIG_CMD_KGDB) |
c609719b WD |
425 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
426 | #endif | |
427 | ||
428 | /* | |
429 | * Internal Definitions | |
430 | * | |
431 | * Boot Flags | |
432 | */ | |
433 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
434 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
435 | ||
436 | ||
437 | #endif /* __CONFIG_H */ |