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608c9146 WD |
1 | /* |
2 | * (C) Copyright 2000, 2001 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
608c9146 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | * (easy to change) | |
18 | */ | |
19 | ||
20 | #define CONFIG_MPC823 1 /* This is a MPC823 CPU */ | |
53677ef1 | 21 | #define CONFIG_V37 1 /* ...on a Marel V37 board */ |
608c9146 | 22 | |
2ae18241 WD |
23 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
24 | ||
608c9146 | 25 | #define CONFIG_LCD |
59155f4c | 26 | #define CONFIG_MPC8XX_LCD |
608c9146 WD |
27 | #define CONFIG_SHARP_LQ084V1DG21 |
28 | #undef CONFIG_LCD_LOGO | |
29 | ||
30 | /*----------------------------------------------------------------------------- | |
31 | * I2C Configuration | |
32 | *----------------------------------------------------------------------------- | |
33 | */ | |
34 | #define CONFIG_I2C 1 | |
6d0f6bcf | 35 | #define CONFIG_SYS_I2C_SLAVE 0x2 |
608c9146 WD |
36 | |
37 | #define CONFIG_8xx_CONS_SMC1 1 | |
38 | #undef CONFIG_8xx_CONS_SMC2 /* Console is on SMC2 */ | |
39 | #undef CONFIG_8xx_CONS_NONE | |
40 | #define CONFIG_BAUDRATE 9600 /* console baudrate = 115kbps */ | |
41 | #if 0 | |
42 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
43 | #else | |
44 | #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ | |
45 | #endif | |
46 | ||
47 | #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ | |
32bf3d14 | 48 | #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
608c9146 WD |
49 | |
50 | #undef CONFIG_BOOTARGS | |
51 | ||
52 | #define CONFIG_BOOTCOMMAND \ | |
53677ef1 | 53 | "tftpboot; " \ |
608c9146 | 54 | "setenv bootargs console=tty0 " \ |
53677ef1 WD |
55 | "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ |
56 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ | |
608c9146 WD |
57 | "bootm" |
58 | ||
59 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 60 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
608c9146 WD |
61 | |
62 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
63 | ||
64 | #define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */ | |
65 | ||
d3b8c1a7 JL |
66 | /* |
67 | * BOOTP options | |
68 | */ | |
69 | #define CONFIG_BOOTP_SUBNETMASK | |
70 | #define CONFIG_BOOTP_GATEWAY | |
71 | #define CONFIG_BOOTP_HOSTNAME | |
72 | #define CONFIG_BOOTP_BOOTPATH | |
73 | #define CONFIG_BOOTP_BOOTFILESIZE | |
74 | ||
608c9146 WD |
75 | |
76 | #define CONFIG_MAC_PARTITION | |
77 | #define CONFIG_DOS_PARTITION | |
78 | ||
79 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
80 | ||
dca3b3d6 JL |
81 | |
82 | /* | |
83 | * Command line configuration. | |
84 | */ | |
85 | #include <config_cmd_default.h> | |
86 | ||
87 | #define CONFIG_CMD_JFFS2 | |
88 | #define CONFIG_CMD_DATE | |
89 | ||
608c9146 | 90 | |
700a0c64 WD |
91 | /* |
92 | * JFFS2 partitions | |
93 | * | |
94 | */ | |
95 | /* No command line, one static partition, whole device */ | |
68d7d651 | 96 | #undef CONFIG_CMD_MTDPARTS |
700a0c64 WD |
97 | #define CONFIG_JFFS2_DEV "nor1" |
98 | #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF | |
99 | #define CONFIG_JFFS2_PART_OFFSET 0x00000000 | |
100 | ||
101 | /* mtdparts command line support */ | |
102 | /* Note: fake mtd_id used, no linux mtd map file */ | |
103 | /* | |
68d7d651 | 104 | #define CONFIG_CMD_MTDPARTS |
700a0c64 WD |
105 | #define MTDIDS_DEFAULT "nor1=v37-1" |
106 | #define MTDPARTS_DEFAULT "mtdparts=v37-1:-(jffs2)" | |
107 | */ | |
608c9146 | 108 | |
608c9146 WD |
109 | /* |
110 | * Miscellaneous configurable options | |
111 | */ | |
6d0f6bcf JCPV |
112 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
113 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
dca3b3d6 | 114 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 115 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
608c9146 | 116 | #else |
6d0f6bcf | 117 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
608c9146 | 118 | #endif |
6d0f6bcf JCPV |
119 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
120 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
121 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
608c9146 | 122 | |
6d0f6bcf JCPV |
123 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
124 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
608c9146 | 125 | |
6d0f6bcf | 126 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
608c9146 | 127 | |
6d0f6bcf | 128 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
608c9146 | 129 | |
608c9146 WD |
130 | /* |
131 | * Low Level Configuration Settings | |
132 | * (address mappings, register initial values, etc.) | |
133 | * You should know what you are doing if you make changes here. | |
134 | */ | |
135 | /*----------------------------------------------------------------------- | |
136 | * Internal Memory Mapped Register | |
137 | */ | |
6d0f6bcf | 138 | #define CONFIG_SYS_IMMR 0xF0000000 |
608c9146 WD |
139 | |
140 | /*----------------------------------------------------------------------- | |
141 | * Definitions for initial stack pointer and data area (in DPRAM) | |
142 | */ | |
6d0f6bcf | 143 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 144 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
25ddd1fb | 145 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 146 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
608c9146 WD |
147 | |
148 | /*----------------------------------------------------------------------- | |
149 | * Start addresses for the final memory configuration | |
150 | * (Set up by the startup code) | |
6d0f6bcf | 151 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
608c9146 | 152 | */ |
6d0f6bcf JCPV |
153 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
154 | #define CONFIG_SYS_FLASH_BASE0 0x40000000 | |
155 | #define CONFIG_SYS_FLASH_BASE1 0x60000000 | |
156 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH_BASE1 | |
608c9146 WD |
157 | |
158 | #if defined(DEBUG) | |
6d0f6bcf | 159 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
608c9146 | 160 | #else |
6d0f6bcf | 161 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
608c9146 | 162 | #endif |
6d0f6bcf JCPV |
163 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE0 |
164 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
608c9146 WD |
165 | |
166 | /* | |
167 | * For booting Linux, the board info and command line data | |
168 | * have to be in the first 8 MB of memory, since this is | |
169 | * the maximum mapped by the Linux kernel during initialization. | |
170 | */ | |
6d0f6bcf | 171 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
608c9146 WD |
172 | |
173 | /*----------------------------------------------------------------------- | |
174 | * FLASH organization | |
175 | */ | |
6d0f6bcf JCPV |
176 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
177 | #define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ | |
608c9146 | 178 | |
6d0f6bcf JCPV |
179 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
180 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
608c9146 | 181 | |
9314cee6 | 182 | #define CONFIG_ENV_IS_IN_NVRAM 1 |
0e8d1586 JCPV |
183 | #define CONFIG_ENV_ADDR 0x80000000/* Address of Environment */ |
184 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
608c9146 | 185 | |
0e8d1586 | 186 | #define CONFIG_ENV_OFFSET 0 |
608c9146 WD |
187 | |
188 | /*----------------------------------------------------------------------- | |
189 | * Cache Configuration | |
190 | */ | |
6d0f6bcf | 191 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
dca3b3d6 | 192 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 193 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
608c9146 WD |
194 | #endif |
195 | ||
196 | /*----------------------------------------------------------------------- | |
197 | * SYPCR - System Protection Control 11-9 | |
198 | * SYPCR can only be written once after reset! | |
199 | *----------------------------------------------------------------------- | |
200 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
201 | */ | |
202 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 203 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
608c9146 WD |
204 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
205 | #else | |
6d0f6bcf | 206 | #define CONFIG_SYS_SYPCR 0xFFFFFF88 |
608c9146 WD |
207 | #endif |
208 | ||
209 | /*----------------------------------------------------------------------- | |
210 | * SIUMCR - SIU Module Configuration 11-6 | |
211 | *----------------------------------------------------------------------- | |
212 | * PCMCIA config., multi-function pin tri-state | |
213 | */ | |
6d0f6bcf | 214 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_FRC | SIUMCR_GB5E) |
608c9146 WD |
215 | |
216 | /*----------------------------------------------------------------------- | |
217 | * TBSCR - Time Base Status and Control 11-26 | |
218 | *----------------------------------------------------------------------- | |
219 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
220 | */ | |
6d0f6bcf | 221 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) |
608c9146 WD |
222 | |
223 | /*----------------------------------------------------------------------- | |
224 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
225 | *----------------------------------------------------------------------- | |
226 | */ | |
6d0f6bcf JCPV |
227 | /*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ |
228 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE) | |
608c9146 WD |
229 | |
230 | /*----------------------------------------------------------------------- | |
231 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
232 | *----------------------------------------------------------------------- | |
233 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
234 | */ | |
6d0f6bcf | 235 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
608c9146 | 236 | /* |
6d0f6bcf | 237 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
608c9146 WD |
238 | */ |
239 | ||
240 | /*----------------------------------------------------------------------- | |
241 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
242 | *----------------------------------------------------------------------- | |
243 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
244 | * interrupt status bit | |
245 | * | |
246 | * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! | |
247 | */ | |
248 | /* up to 50 MHz we use a 1:1 clock */ | |
6d0f6bcf | 249 | #define CONFIG_SYS_PLPRCR ( (1524 << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TMIST | PLPRCR_TEXPS ) |
608c9146 WD |
250 | |
251 | /*----------------------------------------------------------------------- | |
252 | * SCCR - System Clock and reset Control Register 15-27 | |
253 | *----------------------------------------------------------------------- | |
254 | * Set clock output, timebase and RTC source and divider, | |
255 | * power management and some other internal clocks | |
256 | */ | |
257 | #define SCCR_MASK SCCR_EBDF11 | |
258 | /* up to 50 MHz we use a 1:1 clock */ | |
6d0f6bcf | 259 | #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS) |
608c9146 WD |
260 | |
261 | /*----------------------------------------------------------------------- | |
262 | * PCMCIA stuff | |
263 | *----------------------------------------------------------------------- | |
264 | * | |
265 | */ | |
6d0f6bcf JCPV |
266 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
267 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
268 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
269 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
270 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
271 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
272 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
273 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
608c9146 WD |
274 | |
275 | /*----------------------------------------------------------------------- | |
276 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
277 | *----------------------------------------------------------------------- | |
278 | */ | |
279 | ||
280 | #undef CONFIG_IDE_PCCARD /* Use IDE with PC Card Adapter */ | |
281 | ||
282 | #undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */ | |
283 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
284 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
285 | ||
6d0f6bcf JCPV |
286 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
287 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
608c9146 | 288 | |
6d0f6bcf | 289 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
608c9146 | 290 | |
6d0f6bcf | 291 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
608c9146 WD |
292 | |
293 | /* Offset for data I/O */ | |
6d0f6bcf | 294 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
608c9146 WD |
295 | |
296 | /* Offset for normal register accesses */ | |
6d0f6bcf | 297 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
608c9146 WD |
298 | |
299 | /* Offset for alternate registers */ | |
6d0f6bcf | 300 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
608c9146 WD |
301 | |
302 | /*----------------------------------------------------------------------- | |
303 | * | |
304 | *----------------------------------------------------------------------- | |
305 | * | |
306 | */ | |
6d0f6bcf | 307 | #define CONFIG_SYS_DER 0 |
608c9146 WD |
308 | |
309 | /* | |
310 | * Init Memory Controller: | |
311 | * | |
312 | * BR0 and OR0 (FLASH) | |
313 | */ | |
314 | ||
315 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
316 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ | |
317 | ||
6d0f6bcf | 318 | #define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ |
608c9146 | 319 | |
6d0f6bcf | 320 | #define CONFIG_SYS_OR_TIMING_FLASH 0xF56 |
608c9146 | 321 | |
6d0f6bcf JCPV |
322 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
323 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V) | |
608c9146 | 324 | |
6d0f6bcf JCPV |
325 | #define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
326 | #define CONFIG_SYS_BR5_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V) | |
608c9146 WD |
327 | |
328 | /* | |
329 | * BR1 and OR1 (Battery backed SRAM) | |
330 | */ | |
6d0f6bcf JCPV |
331 | #define CONFIG_SYS_BR1_PRELIM 0x80000401 |
332 | #define CONFIG_SYS_OR1_PRELIM 0xFFC00736 | |
608c9146 WD |
333 | |
334 | /* | |
335 | * BR2 and OR2 (SDRAM) | |
336 | */ | |
337 | #define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ | |
338 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB */ | |
339 | ||
6d0f6bcf | 340 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
608c9146 | 341 | |
6d0f6bcf JCPV |
342 | #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
343 | #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
608c9146 WD |
344 | |
345 | /* Marel V37 mem setting */ | |
346 | ||
6d0f6bcf JCPV |
347 | #define CONFIG_SYS_BR3_CAN 0xC0000401 |
348 | #define CONFIG_SYS_OR3_CAN 0xFFFF0724 | |
608c9146 WD |
349 | |
350 | /* | |
6d0f6bcf JCPV |
351 | #define CONFIG_SYS_BR3_PRELIM 0xFA400001 |
352 | #define CONFIG_SYS_OR3_PRELIM 0xFFFF8910 | |
353 | #define CONFIG_SYS_BR4_PRELIM 0xFA000401 | |
354 | #define CONFIG_SYS_OR4_PRELIM 0xFFFE0970 | |
608c9146 WD |
355 | */ |
356 | ||
357 | /* | |
358 | * Memory Periodic Timer Prescaler | |
359 | */ | |
360 | ||
361 | /* periodic timer for refresh */ | |
6d0f6bcf | 362 | #define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ |
608c9146 WD |
363 | |
364 | /* | |
365 | * Refresh clock Prescalar | |
366 | */ | |
6d0f6bcf | 367 | #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV16 |
608c9146 WD |
368 | |
369 | /* | |
370 | * MAMR settings for SDRAM | |
371 | */ | |
372 | ||
373 | /* 10 column SDRAM */ | |
6d0f6bcf | 374 | #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
608c9146 WD |
375 | MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \ |
376 | MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X) | |
377 | ||
608c9146 | 378 | #endif /* __CONFIG_H */ |