[people/ms/u-boot.git] / include / configs / v37.h

/*
 * (C) Copyright 2000, 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
#define CONFIG_V37		1	/* ...on a Marel V37 board	*/

#define	CONFIG_SYS_TEXT_BASE	0x40000000

#define CONFIG_LCD
#define CONFIG_SHARP_LQ084V1DG21
#undef CONFIG_LCD_LOGO

/*-----------------------------------------------------------------------------
 * I2C Configuration
 *-----------------------------------------------------------------------------
 */
#define CONFIG_I2C              1
#define CONFIG_SYS_I2C_SLAVE           0x2

#define	CONFIG_8xx_CONS_SMC1	1
#undef	CONFIG_8xx_CONS_SMC2		/* Console is on SMC2		*/
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		9600	/* console baudrate = 115kbps	*/
#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/
#endif

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"

#undef	CONFIG_BOOTARGS

#define CONFIG_BOOTCOMMAND							\
	"tftpboot; "								\
	"setenv bootargs console=tty0 "                                   \
	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "			\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
	"bootm"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define	CONFIG_CAN_DRIVER	1	/* CAN Driver support enabled	*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_DATE


/*
 * JFFS2 partitions
 *
 */
/* No command line, one static partition, whole device */
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV		"nor1"
#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET	0x00000000

/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT		"nor1=v37-1"
#define MTDPARTS_DEFAULT	"mtdparts=v37-1:-(jffs2)"
*/

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xF0000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE0		0x40000000
#define CONFIG_SYS_FLASH_BASE1		0x60000000
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH_BASE1

#if defined(DEBUG)
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#endif
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE0
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	35	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CONFIG_ENV_IS_IN_NVRAM	1
#define	CONFIG_ENV_ADDR		0x80000000/* Address of Environment */
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

#define CONFIG_ENV_OFFSET		0

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	0xFFFFFF88
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_FRC | SIUMCR_GB5E)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
/*%%%#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
/*
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
*/

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 *
 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 */
/* up to 50 MHz we use a 1:1 clock */
#define CONFIG_SYS_PLPRCR	( (1524 << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TMIST | PLPRCR_TEXPS )

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
/* up to 50 MHz we use a 1:1 clock */
#define CONFIG_SYS_SCCR	(SCCR_COM00 | SCCR_TBS)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#undef	CONFIG_IDE_PCCARD		/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_PCMCIA		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER	0

/*
 * Init Memory Controller:
 *
 * BR0 and OR0 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #1	*/

#define CONFIG_SYS_PRELIM_OR_AM	0xFE000000	/* OR addr mask */

#define CONFIG_SYS_OR_TIMING_FLASH	0xF56

#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V)

#define CONFIG_SYS_OR5_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR5_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V)

/*
 * BR1 and OR1 (Battery backed SRAM)
 */
#define	CONFIG_SYS_BR1_PRELIM	0x80000401
#define CONFIG_SYS_OR1_PRELIM	0xFFC00736

/*
 * BR2 and OR2 (SDRAM)
 */
#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/
#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB */

#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00

#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

/* Marel V37 mem setting */

#define	CONFIG_SYS_BR3_CAN	0xC0000401
#define CONFIG_SYS_OR3_CAN	0xFFFF0724

/*
#define	CONFIG_SYS_BR3_PRELIM	0xFA400001
#define CONFIG_SYS_OR3_PRELIM	0xFFFF8910
#define	CONFIG_SYS_BR4_PRELIM	0xFA000401
#define CONFIG_SYS_OR4_PRELIM	0xFFFE0970
*/

/*
 * Memory Periodic Timer Prescaler
 */

/* periodic timer for refresh */
#define CONFIG_SYS_MAMR_PTA	97		/* start with divider for 100 MHz	*/

/*
 * Refresh clock Prescalar
 */
#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV16

/*
 * MAMR settings for SDRAM
 */

/* 10 column SDRAM */
#define CONFIG_SYS_MAMR_10COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 |	\
			 MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)

#endif	/* __CONFIG_H */
Commit	Line	Data
608c9146 WD	1	/*
	2	* (C) Copyright 2000, 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
53677ef1	37	#define CONFIG_V37 1 /* ...on a Marel V37 board */
608c9146	38
2ae18241 WD	39	#define CONFIG_SYS_TEXT_BASE 0x40000000
2ae18241 WD	40
608c9146 WD	41	#define CONFIG_LCD
	42	#define CONFIG_SHARP_LQ084V1DG21
	43	#undef CONFIG_LCD_LOGO
	44
	45	/*-----------------------------------------------------------------------------
	46	* I2C Configuration
	47	*-----------------------------------------------------------------------------
	48	*/
	49	#define CONFIG_I2C 1
6d0f6bcf	50	#define CONFIG_SYS_I2C_SLAVE 0x2
608c9146 WD	51
	52	#define CONFIG_8xx_CONS_SMC1 1
	53	#undef CONFIG_8xx_CONS_SMC2 /* Console is on SMC2 */
	54	#undef CONFIG_8xx_CONS_NONE
	55	#define CONFIG_BAUDRATE 9600 /* console baudrate = 115kbps */
	56	#if 0
	57	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	58	#else
	59	#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
	60	#endif
	61
	62	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
32bf3d14	63	#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
608c9146 WD	64
	65	#undef CONFIG_BOOTARGS
	66
	67	#define CONFIG_BOOTCOMMAND \
53677ef1	68	"tftpboot; " \
608c9146	69	"setenv bootargs console=tty0 " \
53677ef1 WD	70	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
53677ef1 WD	71	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
608c9146 WD	72	"bootm"
	73
	74	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	75	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
608c9146 WD	76
	77	#undef CONFIG_WATCHDOG /* watchdog disabled */
	78
	79	#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */
	80
d3b8c1a7 JL	81	/*
	82	* BOOTP options
	83	*/
	84	#define CONFIG_BOOTP_SUBNETMASK
	85	#define CONFIG_BOOTP_GATEWAY
	86	#define CONFIG_BOOTP_HOSTNAME
	87	#define CONFIG_BOOTP_BOOTPATH
	88	#define CONFIG_BOOTP_BOOTFILESIZE
	89
608c9146 WD	90
	91	#define CONFIG_MAC_PARTITION
	92	#define CONFIG_DOS_PARTITION
	93
	94	#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
	95
dca3b3d6 JL	96
	97	/*
	98	* Command line configuration.
	99	*/
	100	#include <config_cmd_default.h>
	101
	102	#define CONFIG_CMD_JFFS2
	103	#define CONFIG_CMD_DATE
	104
608c9146	105
700a0c64 WD	106	/*
	107	* JFFS2 partitions
	108	*
	109	*/
	110	/* No command line, one static partition, whole device */
68d7d651	111	#undef CONFIG_CMD_MTDPARTS
700a0c64 WD	112	#define CONFIG_JFFS2_DEV "nor1"
	113	#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
	114	#define CONFIG_JFFS2_PART_OFFSET 0x00000000
	115
	116	/* mtdparts command line support */
	117	/* Note: fake mtd_id used, no linux mtd map file */
	118	/*
68d7d651	119	#define CONFIG_CMD_MTDPARTS
700a0c64 WD	120	#define MTDIDS_DEFAULT "nor1=v37-1"
	121	#define MTDPARTS_DEFAULT "mtdparts=v37-1:-(jffs2)"
	122	*/
608c9146	123
608c9146 WD	124	/*
	125	* Miscellaneous configurable options
	126	*/
6d0f6bcf JCPV	127	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	128	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
dca3b3d6	129	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	130	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
608c9146	131	#else
6d0f6bcf	132	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
608c9146	133	#endif
6d0f6bcf JCPV	134	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	135	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	136	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
608c9146	137
6d0f6bcf JCPV	138	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	139	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
608c9146	140
6d0f6bcf	141	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
608c9146	142
6d0f6bcf	143	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
608c9146	144
6d0f6bcf	145	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
608c9146 WD	146
	147	/*
	148	* Low Level Configuration Settings
	149	* (address mappings, register initial values, etc.)
	150	* You should know what you are doing if you make changes here.
	151	*/
	152	/*-----------------------------------------------------------------------
	153	* Internal Memory Mapped Register
	154	*/
6d0f6bcf	155	#define CONFIG_SYS_IMMR 0xF0000000
608c9146 WD	156
	157	/*-----------------------------------------------------------------------
	158	* Definitions for initial stack pointer and data area (in DPRAM)
	159	*/
6d0f6bcf	160	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	161	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	162	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	163	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
608c9146 WD	164
	165	/*-----------------------------------------------------------------------
	166	* Start addresses for the final memory configuration
	167	* (Set up by the startup code)
6d0f6bcf	168	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
608c9146	169	*/
6d0f6bcf JCPV	170	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	171	#define CONFIG_SYS_FLASH_BASE0 0x40000000
	172	#define CONFIG_SYS_FLASH_BASE1 0x60000000
	173	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH_BASE1
608c9146 WD	174
608c9146 WD	175	#if defined(DEBUG)
6d0f6bcf	176	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
608c9146	177	#else
6d0f6bcf	178	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
608c9146	179	#endif
6d0f6bcf JCPV	180	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE0
6d0f6bcf JCPV	181	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
608c9146 WD	182
	183	/*
	184	* For booting Linux, the board info and command line data
	185	* have to be in the first 8 MB of memory, since this is
	186	* the maximum mapped by the Linux kernel during initialization.
	187	*/
6d0f6bcf	188	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
608c9146 WD	189
	190	/*-----------------------------------------------------------------------
	191	* FLASH organization
	192	*/
6d0f6bcf JCPV	193	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6d0f6bcf JCPV	194	#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
608c9146	195
6d0f6bcf JCPV	196	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	197	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
608c9146	198
9314cee6	199	#define CONFIG_ENV_IS_IN_NVRAM 1
0e8d1586 JCPV	200	#define CONFIG_ENV_ADDR 0x80000000/* Address of Environment */
0e8d1586 JCPV	201	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
608c9146	202
0e8d1586	203	#define CONFIG_ENV_OFFSET 0
608c9146 WD	204
	205	/*-----------------------------------------------------------------------
	206	* Cache Configuration
	207	*/
6d0f6bcf	208	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
dca3b3d6	209	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	210	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
608c9146 WD	211	#endif
	212
	213	/*-----------------------------------------------------------------------
	214	* SYPCR - System Protection Control 11-9
	215	* SYPCR can only be written once after reset!
	216	*-----------------------------------------------------------------------
	217	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	218	*/
	219	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	220	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
608c9146 WD	221	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
608c9146 WD	222	#else
6d0f6bcf	223	#define CONFIG_SYS_SYPCR 0xFFFFFF88
608c9146 WD	224	#endif
	225
	226	/*-----------------------------------------------------------------------
	227	* SIUMCR - SIU Module Configuration 11-6
	228	*-----------------------------------------------------------------------
	229	* PCMCIA config., multi-function pin tri-state
	230	*/
6d0f6bcf	231	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_FRC \| SIUMCR_GB5E)
608c9146 WD	232
	233	/*-----------------------------------------------------------------------
	234	* TBSCR - Time Base Status and Control 11-26
	235	*-----------------------------------------------------------------------
	236	* Clear Reference Interrupt Status, Timebase freezing enabled
	237	*/
6d0f6bcf	238	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBE)
608c9146 WD	239
	240	/*-----------------------------------------------------------------------
	241	* RTCSC - Real-Time Clock Status and Control Register 11-27
	242	*-----------------------------------------------------------------------
	243	*/
6d0f6bcf JCPV	244	/%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE) /
6d0f6bcf JCPV	245	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_RTE)
608c9146 WD	246
	247	/*-----------------------------------------------------------------------
	248	* PISCR - Periodic Interrupt Status and Control 11-31
	249	*-----------------------------------------------------------------------
	250	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	251	*/
6d0f6bcf	252	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
608c9146	253	/*
6d0f6bcf	254	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
608c9146 WD	255	*/
	256
	257	/*-----------------------------------------------------------------------
	258	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	259	*-----------------------------------------------------------------------
	260	* Reset PLL lock status sticky bit, timer expired status bit and timer
	261	* interrupt status bit
	262	*
	263	* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
	264	*/
	265	/* up to 50 MHz we use a 1:1 clock */
6d0f6bcf	266	#define CONFIG_SYS_PLPRCR ( (1524 << PLPRCR_MF_SHIFT) \| PLPRCR_SPLSS \| PLPRCR_TMIST \| PLPRCR_TEXPS )
608c9146 WD	267
	268	/*-----------------------------------------------------------------------
	269	* SCCR - System Clock and reset Control Register 15-27
	270	*-----------------------------------------------------------------------
	271	* Set clock output, timebase and RTC source and divider,
	272	* power management and some other internal clocks
	273	*/
	274	#define SCCR_MASK SCCR_EBDF11
	275	/* up to 50 MHz we use a 1:1 clock */
6d0f6bcf	276	#define CONFIG_SYS_SCCR (SCCR_COM00 \| SCCR_TBS)
608c9146 WD	277
	278	/*-----------------------------------------------------------------------
	279	* PCMCIA stuff
	280	*-----------------------------------------------------------------------
	281	*
	282	*/
6d0f6bcf JCPV	283	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	284	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	285	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	286	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	287	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	288	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	289	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	290	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
608c9146 WD	291
	292	/*-----------------------------------------------------------------------
	293	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	294	*-----------------------------------------------------------------------
	295	*/
	296
	297	#undef CONFIG_IDE_PCCARD /* Use IDE with PC Card Adapter */
	298
	299	#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
	300	#undef CONFIG_IDE_LED /* LED for ide not supported */
	301	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	302
6d0f6bcf JCPV	303	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	304	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
608c9146	305
6d0f6bcf	306	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
608c9146	307
6d0f6bcf	308	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
608c9146 WD	309
608c9146 WD	310	/* Offset for data I/O */
6d0f6bcf	311	#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
608c9146 WD	312
608c9146 WD	313	/* Offset for normal register accesses */
6d0f6bcf	314	#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
608c9146 WD	315
608c9146 WD	316	/* Offset for alternate registers */
6d0f6bcf	317	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
608c9146 WD	318
	319	/*-----------------------------------------------------------------------
	320	*
	321	*-----------------------------------------------------------------------
	322	*
	323	*/
6d0f6bcf	324	#define CONFIG_SYS_DER 0
608c9146 WD	325
	326	/*
	327	* Init Memory Controller:
	328	*
	329	* BR0 and OR0 (FLASH)
	330	*/
	331
	332	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	333	#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */
	334
6d0f6bcf	335	#define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
608c9146	336
6d0f6bcf	337	#define CONFIG_SYS_OR_TIMING_FLASH 0xF56
608c9146	338
6d0f6bcf JCPV	339	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
6d0f6bcf JCPV	340	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_PS_16 \| BR_V)
608c9146	341
6d0f6bcf JCPV	342	#define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
6d0f6bcf JCPV	343	#define CONFIG_SYS_BR5_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) \| BR_PS_32 \| BR_V)
608c9146 WD	344
	345	/*
	346	* BR1 and OR1 (Battery backed SRAM)
	347	*/
6d0f6bcf JCPV	348	#define CONFIG_SYS_BR1_PRELIM 0x80000401
6d0f6bcf JCPV	349	#define CONFIG_SYS_OR1_PRELIM 0xFFC00736
608c9146 WD	350
	351	/*
	352	* BR2 and OR2 (SDRAM)
	353	*/
	354	#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
	355	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB */
	356
6d0f6bcf	357	#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
608c9146	358
6d0f6bcf JCPV	359	#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_SDRAM )
6d0f6bcf JCPV	360	#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
608c9146 WD	361
	362	/* Marel V37 mem setting */
	363
6d0f6bcf JCPV	364	#define CONFIG_SYS_BR3_CAN 0xC0000401
6d0f6bcf JCPV	365	#define CONFIG_SYS_OR3_CAN 0xFFFF0724
608c9146 WD	366
608c9146 WD	367	/*
6d0f6bcf JCPV	368	#define CONFIG_SYS_BR3_PRELIM 0xFA400001
	369	#define CONFIG_SYS_OR3_PRELIM 0xFFFF8910
	370	#define CONFIG_SYS_BR4_PRELIM 0xFA000401
	371	#define CONFIG_SYS_OR4_PRELIM 0xFFFE0970
608c9146 WD	372	*/
	373
	374	/*
	375	* Memory Periodic Timer Prescaler
	376	*/
	377
	378	/* periodic timer for refresh */
6d0f6bcf	379	#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
608c9146 WD	380
	381	/*
	382	* Refresh clock Prescalar
	383	*/
6d0f6bcf	384	#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV16
608c9146 WD	385
	386	/*
	387	* MAMR settings for SDRAM
	388	*/
	389
	390	/* 10 column SDRAM */
6d0f6bcf	391	#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
608c9146 WD	392	MAMR_AMA_TYPE_2 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A12 \| \
	393	MAMR_GPL_A4DIS \| MAMR_RLFA_4X \| MAMR_WLFA_3X \| MAMR_TLFA_16X)
	394
608c9146	395	#endif /* __CONFIG_H */