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4707fb50 | 1 | /* |
82d9c9ec | 2 | * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering, |
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3 | * wd@denx.de. |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
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6 | */ |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
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11 | /* |
12 | * High Level Configuration Options | |
13 | * (easy to change) | |
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14 | */ |
15 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
16 | #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ | |
17 | #define CONFIG_V38B 1 /* ...on V38B board */ | |
2ae18241 WD |
18 | |
19 | #define CONFIG_SYS_TEXT_BASE 0xFF000000 | |
20 | ||
6d0f6bcf | 21 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */ |
4707fb50 | 22 | |
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23 | #define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ |
24 | #define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ | |
4707fb50 | 25 | |
ce3f1a40 | 26 | #undef CONFIG_HW_WATCHDOG /* don't use watchdog */ |
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27 | |
28 | #define CONFIG_NETCONSOLE 1 | |
29 | ||
82d9c9ec | 30 | #define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */ |
cce4acbb | 31 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* do board-specific init */ |
d8d21e69 | 32 | #define CONFIG_MISC_INIT_R |
4707fb50 | 33 | |
6d0f6bcf | 34 | #define CONFIG_SYS_XLB_PIPELINING 1 /* gives better performance */ |
4707fb50 | 35 | |
31d82672 BB |
36 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
37 | ||
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38 | /* |
39 | * Serial console configuration | |
40 | */ | |
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41 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ |
42 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
6d0f6bcf | 43 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
4707fb50 | 44 | |
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45 | /* |
46 | * DDR | |
47 | */ | |
48 | #define SDRAM_DDR 1 /* is DDR */ | |
49 | /* Settings for XLB = 132 MHz */ | |
50 | #define SDRAM_MODE 0x018D0000 | |
51 | #define SDRAM_EMODE 0x40090000 | |
52 | #define SDRAM_CONTROL 0x704f0f00 | |
53 | #define SDRAM_CONFIG1 0x73722930 | |
54 | #define SDRAM_CONFIG2 0x47770000 | |
55 | #define SDRAM_TAPDELAY 0x10000000 | |
56 | ||
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57 | /* |
58 | * PCI - no suport | |
59 | */ | |
60 | #undef CONFIG_PCI | |
61 | ||
62 | /* | |
63 | * Partitions | |
64 | */ | |
65 | #define CONFIG_MAC_PARTITION 1 | |
66 | #define CONFIG_DOS_PARTITION 1 | |
67 | ||
68 | /* | |
69 | * USB | |
70 | */ | |
71 | #define CONFIG_USB_OHCI | |
72 | #define CONFIG_USB_STORAGE | |
82d9c9ec BS |
73 | #define CONFIG_USB_CLOCK 0x0001BBBB |
74 | #define CONFIG_USB_CONFIG 0x00001000 | |
4707fb50 | 75 | |
dca3b3d6 | 76 | |
079a136c JL |
77 | /* |
78 | * BOOTP options | |
79 | */ | |
80 | #define CONFIG_BOOTP_BOOTFILESIZE | |
81 | #define CONFIG_BOOTP_BOOTPATH | |
82 | #define CONFIG_BOOTP_GATEWAY | |
83 | #define CONFIG_BOOTP_HOSTNAME | |
84 | ||
85 | ||
4707fb50 | 86 | /* |
dca3b3d6 | 87 | * Command line configuration. |
4707fb50 | 88 | */ |
dca3b3d6 JL |
89 | #include <config_cmd_default.h> |
90 | ||
91 | #define CONFIG_CMD_FAT | |
92 | #define CONFIG_CMD_I2C | |
93 | #define CONFIG_CMD_IDE | |
94 | #define CONFIG_CMD_PING | |
95 | #define CONFIG_CMD_DHCP | |
96 | #define CONFIG_CMD_DIAG | |
97 | #define CONFIG_CMD_IRQ | |
98 | #define CONFIG_CMD_JFFS2 | |
99 | #define CONFIG_CMD_MII | |
100 | #define CONFIG_CMD_SDRAM | |
101 | #define CONFIG_CMD_DATE | |
102 | #define CONFIG_CMD_USB | |
103 | #define CONFIG_CMD_FAT | |
4707fb50 | 104 | |
82d9c9ec | 105 | |
dca3b3d6 | 106 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
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107 | |
108 | /* | |
109 | * Boot low with 16 MB Flash | |
110 | */ | |
6d0f6bcf JCPV |
111 | #define CONFIG_SYS_LOWBOOT 1 |
112 | #define CONFIG_SYS_LOWBOOT16 1 | |
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113 | |
114 | /* | |
115 | * Autobooting | |
116 | */ | |
117 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
118 | ||
82d9c9ec | 119 | #define CONFIG_PREBOOT "echo;" \ |
32bf3d14 | 120 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
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121 | "echo" |
122 | ||
82d9c9ec | 123 | #undef CONFIG_BOOTARGS |
4707fb50 | 124 | |
fcfed4f2 | 125 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
82d9c9ec BS |
126 | "bootcmd=run net_nfs\0" \ |
127 | "bootdelay=3\0" \ | |
128 | "baudrate=115200\0" \ | |
129 | "preboot=echo;echo Type \"run flash_nfs\" to mount root " \ | |
130 | "filesystem over NFS; echo\0" \ | |
fcfed4f2 | 131 | "netdev=eth0\0" \ |
cce4acbb | 132 | "ramargs=setenv bootargs root=/dev/ram rw wdt=off \0" \ |
fcfed4f2 WD |
133 | "addip=setenv bootargs $(bootargs) " \ |
134 | "ip=$(ipaddr):$(serverip):$(gatewayip):" \ | |
135 | "$(netmask):$(hostname):$(netdev):off panic=1\0" \ | |
136 | "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ | |
137 | "flash_self=run ramargs addip;bootm $(kernel_addr) " \ | |
138 | "$(ramdisk_addr)\0" \ | |
82d9c9ec | 139 | "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ |
fcfed4f2 | 140 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
cce4acbb | 141 | "nfsroot=$(serverip):$(rootpath) wdt=off\0" \ |
82d9c9ec | 142 | "hostname=v38b\0" \ |
48690d80 | 143 | "ethact=FEC\0" \ |
82d9c9ec BS |
144 | "rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \ |
145 | "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \ | |
146 | "cp.b 200000 ff000000 $(filesize);" \ | |
147 | "prot on ff000000 ff03ffff\0" \ | |
148 | "load=tftp 200000 $(u-boot)\0" \ | |
149 | "netmask=255.255.0.0\0" \ | |
150 | "ipaddr=192.168.160.18\0" \ | |
151 | "serverip=192.168.1.1\0" \ | |
152 | "ethaddr=00:e0:ee:00:05:2e\0" \ | |
153 | "bootfile=/tftpboot/v38b/uImage\0" \ | |
154 | "u-boot=/tftpboot/v38b/u-boot.bin\0" \ | |
fcfed4f2 | 155 | "" |
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156 | |
157 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
158 | ||
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159 | /* |
160 | * IPB Bus clocking configuration. | |
161 | */ | |
6d0f6bcf | 162 | #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
82d9c9ec | 163 | |
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164 | /* |
165 | * I2C configuration | |
166 | */ | |
167 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
6d0f6bcf JCPV |
168 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ |
169 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ | |
170 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
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171 | |
172 | /* | |
173 | * EEPROM configuration | |
174 | */ | |
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
176 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
177 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
178 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 | |
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179 | |
180 | /* | |
181 | * RTC configuration | |
182 | */ | |
6d0f6bcf | 183 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 |
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184 | |
185 | /* | |
186 | * Flash configuration - use CFI driver | |
187 | */ | |
6d0f6bcf | 188 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 189 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6d0f6bcf JCPV |
190 | #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 |
191 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 | |
192 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ | |
193 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
194 | #define CONFIG_SYS_FLASH_SIZE 0x01000000 /* 16 MiB */ | |
195 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ | |
196 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ | |
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197 | |
198 | /* | |
199 | * Environment settings | |
200 | */ | |
5a1aceb0 | 201 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 202 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) |
0e8d1586 JCPV |
203 | #define CONFIG_ENV_SIZE 0x10000 |
204 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
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205 | #define CONFIG_ENV_OVERWRITE 1 |
206 | ||
207 | /* | |
208 | * Memory map | |
209 | */ | |
6d0f6bcf JCPV |
210 | #define CONFIG_SYS_MBAR 0xF0000000 |
211 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
212 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
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213 | |
214 | /* Use SRAM until RAM will be available */ | |
6d0f6bcf | 215 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
553f0982 | 216 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ |
4707fb50 | 217 | |
25ddd1fb | 218 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 219 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
4707fb50 | 220 | |
14d0a02a | 221 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
222 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
223 | # define CONFIG_SYS_RAMBOOT 1 | |
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224 | #endif |
225 | ||
6d0f6bcf JCPV |
226 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256kB for Monitor */ |
227 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128kB for malloc() */ | |
228 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Linux initial memory map */ | |
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229 | |
230 | /* | |
231 | * Ethernet configuration | |
232 | */ | |
233 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 234 | #define CONFIG_MPC5xxx_FEC_MII100 |
4707fb50 | 235 | #define CONFIG_PHY_ADDR 0x00 |
fcfed4f2 | 236 | #define CONFIG_MII 1 |
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237 | |
238 | /* | |
239 | * GPIO configuration | |
240 | */ | |
6d0f6bcf | 241 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x90001404 |
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242 | |
243 | /* | |
244 | * Miscellaneous configurable options | |
245 | */ | |
6d0f6bcf | 246 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
dca3b3d6 | 247 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 248 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
4707fb50 | 249 | #else |
6d0f6bcf | 250 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
4707fb50 | 251 | #endif |
6d0f6bcf JCPV |
252 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
253 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
254 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
4707fb50 | 255 | |
6d0f6bcf JCPV |
256 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
257 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
4707fb50 | 258 | |
6d0f6bcf | 259 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
4707fb50 | 260 | |
6d0f6bcf | 261 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
dca3b3d6 | 262 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 263 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
dca3b3d6 JL |
264 | #endif |
265 | ||
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266 | /* |
267 | * Various low-level settings | |
268 | */ | |
6d0f6bcf JCPV |
269 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
270 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
4707fb50 | 271 | |
6d0f6bcf JCPV |
272 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
273 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
274 | #define CONFIG_SYS_BOOTCS_CFG 0x00047801 | |
275 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE | |
276 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
4707fb50 | 277 | |
6d0f6bcf JCPV |
278 | #define CONFIG_SYS_CS_BURST 0x00000000 |
279 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
4707fb50 | 280 | |
6d0f6bcf | 281 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
4707fb50 | 282 | |
82d9c9ec BS |
283 | /* |
284 | * IDE/ATA (supports IDE harddisk) | |
4707fb50 | 285 | */ |
82d9c9ec BS |
286 | #undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ |
287 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
288 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
4707fb50 | 289 | |
82d9c9ec | 290 | #define CONFIG_IDE_RESET /* reset for ide supported */ |
4707fb50 BS |
291 | #define CONFIG_IDE_PREINIT |
292 | ||
6d0f6bcf JCPV |
293 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
294 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
4707fb50 | 295 | |
6d0f6bcf | 296 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
4707fb50 | 297 | |
6d0f6bcf | 298 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
4707fb50 | 299 | |
6d0f6bcf | 300 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) /* data I/O offset */ |
4707fb50 | 301 | |
6d0f6bcf | 302 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* normal register accesses offset */ |
4707fb50 | 303 | |
6d0f6bcf | 304 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) /* alternate registers offset */ |
4707fb50 | 305 | |
6d0f6bcf | 306 | #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ |
4707fb50 | 307 | |
82d9c9ec BS |
308 | /* |
309 | * Status LED | |
310 | */ | |
311 | #define CONFIG_STATUS_LED /* Status LED enabled */ | |
312 | #define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ | |
4707fb50 | 313 | |
6d0f6bcf | 314 | #define CONFIG_SYS_LED_BASE MPC5XXX_GPT7_ENABLE /* Timer 7 GPIO */ |
4707fb50 | 315 | #ifndef __ASSEMBLY__ |
4707fb50 BS |
316 | typedef unsigned int led_id_t; |
317 | ||
318 | #define __led_toggle(_msk) \ | |
319 | do { \ | |
6d0f6bcf | 320 | *((volatile long *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \ |
4707fb50 BS |
321 | } while(0) |
322 | ||
323 | #define __led_set(_msk, _st) \ | |
324 | do { \ | |
325 | if ((_st)) \ | |
6d0f6bcf | 326 | *((volatile long *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \ |
4707fb50 | 327 | else \ |
6d0f6bcf | 328 | *((volatile long *) (CONFIG_SYS_LED_BASE)) |= (_msk); \ |
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329 | } while(0) |
330 | ||
331 | #define __led_init(_msk, st) \ | |
82d9c9ec | 332 | do { \ |
6d0f6bcf | 333 | *((volatile long *) (CONFIG_SYS_LED_BASE)) |= 0x34; \ |
82d9c9ec BS |
334 | } while(0) |
335 | #endif /* __ASSEMBLY__ */ | |
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336 | |
337 | #endif /* __CONFIG_H */ |