[people/ms/u-boot.git] / include / configs / v38b.h

/*
 * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering,
 * wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MPC5200			1	/* This is an MPC5200 CPU */
#define CONFIG_V38B			1	/* ...on V38B board */
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO

#define	CONFIG_SYS_TEXT_BASE		0xFF000000

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000	/* ...running at 33.000000MHz */

#define CONFIG_RTC_PCF8563		1	/* has PCF8563 RTC */
#define CONFIG_MPC5200_DDR		1	/* has DDR SDRAM */

#undef CONFIG_HW_WATCHDOG			/* don't use watchdog */

#define CONFIG_NETCONSOLE		1

#define CONFIG_BOARD_EARLY_INIT_R	1	/* do board-specific init */
#define CONFIG_BOARD_EARLY_INIT_F	1	/* do board-specific init */
#define CONFIG_MISC_INIT_R

#define CONFIG_SYS_XLB_PIPELINING		1	/* gives better performance */

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * DDR
 */
#define SDRAM_DDR		1	/* is DDR */
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE		0x018D0000
#define SDRAM_EMODE		0x40090000
#define SDRAM_CONTROL		0x704f0f00
#define SDRAM_CONFIG1		0x73722930
#define SDRAM_CONFIG2		0x47770000
#define SDRAM_TAPDELAY		0x10000000

/*
 * PCI - no suport
 */
#undef CONFIG_PCI

/*
 * Partitions
 */
#define CONFIG_MAC_PARTITION	1
#define CONFIG_DOS_PARTITION	1

/*
 * USB
 */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00001000


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_DATE
#define CONFIG_CMD_USB
#define CONFIG_CMD_FAT


#define CONFIG_TIMESTAMP		/* Print image info with timestamp */

/*
 * Boot low with 16 MB Flash
 */
#define CONFIG_SYS_LOWBOOT		1
#define CONFIG_SYS_LOWBOOT16		1

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"bootcmd=run net_nfs\0"						\
	"bootdelay=3\0"							\
	"baudrate=115200\0"						\
	"preboot=echo;echo Type \"run flash_nfs\" to mount root "	\
		"filesystem over NFS; echo\0"				\
	"netdev=eth0\0"							\
	"ramargs=setenv bootargs root=/dev/ram rw wdt=off \0"		\
	"addip=setenv bootargs $(bootargs) "				\
		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
		"$(netmask):$(hostname):$(netdev):off panic=1\0"	\
	"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0"		\
	"flash_self=run ramargs addip;bootm $(kernel_addr) "		\
		"$(ramdisk_addr)\0"					\
	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$(serverip):$(rootpath) wdt=off\0"		\
	"hostname=v38b\0"						\
	"ethact=FEC\0"							\
	"rootpath=/opt/eldk-3.1.1/ppc_6xx\0"				\
	"update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; "	\
		"cp.b 200000 ff000000 $(filesize);"			\
		"prot on ff000000 ff03ffff\0"				\
	"load=tftp 200000 $(u-boot)\0"					\
	"netmask=255.255.0.0\0"						\
	"ipaddr=192.168.160.18\0"					\
	"serverip=192.168.1.1\0"					\
	"bootfile=/tftpboot/v38b/uImage\0"				\
	"u-boot=/tftpboot/v38b/u-boot.bin\0"				\
	""

#define CONFIG_BOOTCOMMAND	"run net_nfs"

/*
 * IPB Bus clocking configuration.
 */
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK			/* define for 133MHz speed */

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
#define CONFIG_SYS_I2C_SPEED		100000	/* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70

/*
 * RTC configuration
 */
#define CONFIG_SYS_I2C_RTC_ADDR		0x51

/*
 * Flash configuration - use CFI driver
 */
#define CONFIG_SYS_FLASH_CFI		1		/* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER	1		/* Use the common driver */
#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1
#define CONFIG_SYS_FLASH_BASE		0xFF000000
#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max num of flash banks */
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_FLASH_SIZE		0x01000000	/* 16 MiB */
#define CONFIG_SYS_MAX_FLASH_SECT	256		/* max num of sects on one chip */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1	/* flash write speed-up */

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)
#define CONFIG_ENV_SIZE		0x10000
#define CONFIG_ENV_SECT_SIZE	0x10000
#define CONFIG_ENV_OVERWRITE	1

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128kB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Linux initial memory map */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
#define CONFIG_PHY_ADDR		0x00
#define CONFIG_MII		1

/*
 * GPIO configuration
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x90001404

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM */

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00047801
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333

#define CONFIG_SYS_RESET_ADDRESS	0xff000000

/*
 * IDE/ATA (supports IDE harddisk)
 */
#undef CONFIG_IDE_8xx_PCCARD		/* Don't use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT		/* Direct IDE not supported */
#undef CONFIG_IDE_LED			/* LED for ide not supported */

#define CONFIG_IDE_RESET		/* reset for ide supported */
#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus */
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus */

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA

#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)	/* data I/O offset */

#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)	/* normal register accesses offset */

#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)	/* alternate registers offset */

#define CONFIG_SYS_ATA_STRIDE		4		/* Interval between registers */

/*
 * Status LED
 */
#define  CONFIG_STATUS_LED		/* Status LED enabled */
#define  CONFIG_BOARD_SPECIFIC_LED	/* version has board specific leds */

#define CONFIG_SYS_LED_BASE	MPC5XXX_GPT7_ENABLE	/* Timer 7 GPIO */
#ifndef __ASSEMBLY__
typedef unsigned int led_id_t;

#define __led_toggle(_msk) \
	do { \
		*((volatile long *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \
	} while(0)

#define __led_set(_msk, _st) \
	do { \
		if ((_st)) \
			*((volatile long *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \
		else \
			*((volatile long *) (CONFIG_SYS_LED_BASE)) |= (_msk); \
	} while(0)

#define __led_init(_msk, st) \
	do { \
		*((volatile long *) (CONFIG_SYS_LED_BASE)) |= 0x34; \
	} while(0)
#endif /* __ASSEMBLY__ */

#endif /* __CONFIG_H */
Commit	Line	Data
4707fb50	1	/*
82d9c9ec	2	* (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering,
4707fb50 BS	3	* wd@denx.de.
4707fb50 BS	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
4707fb50 BS	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
4707fb50 BS	11	/*
	12	* High Level Configuration Options
	13	* (easy to change)
82d9c9ec	14	*/
82d9c9ec BS	15	#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
82d9c9ec BS	16	#define CONFIG_V38B 1 /* ...on V38B board */
e1219229 AG	17	#define CONFIG_SYS_GENERIC_BOARD
e1219229 AG	18	#define CONFIG_DISPLAY_BOARDINFO
2ae18241 WD	19
	20	#define CONFIG_SYS_TEXT_BASE 0xFF000000
	21
6d0f6bcf	22	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */
4707fb50	23
82d9c9ec BS	24	#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */
82d9c9ec BS	25	#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */
4707fb50	26
ce3f1a40	27	#undef CONFIG_HW_WATCHDOG /* don't use watchdog */
4707fb50 BS	28
	29	#define CONFIG_NETCONSOLE 1
	30
82d9c9ec	31	#define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */
cce4acbb	32	#define CONFIG_BOARD_EARLY_INIT_F 1 /* do board-specific init */
d8d21e69	33	#define CONFIG_MISC_INIT_R
4707fb50	34
6d0f6bcf	35	#define CONFIG_SYS_XLB_PIPELINING 1 /* gives better performance */
4707fb50	36
31d82672 BB	37	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	38
4707fb50 BS	39	/*
	40	* Serial console configuration
	41	*/
82d9c9ec BS	42	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
82d9c9ec BS	43	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf	44	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
4707fb50	45
4707fb50 BS	46	/*
	47	* DDR
	48	*/
	49	#define SDRAM_DDR 1 /* is DDR */
	50	/* Settings for XLB = 132 MHz */
	51	#define SDRAM_MODE 0x018D0000
	52	#define SDRAM_EMODE 0x40090000
	53	#define SDRAM_CONTROL 0x704f0f00
	54	#define SDRAM_CONFIG1 0x73722930
	55	#define SDRAM_CONFIG2 0x47770000
	56	#define SDRAM_TAPDELAY 0x10000000
	57
4707fb50 BS	58	/*
	59	* PCI - no suport
	60	*/
	61	#undef CONFIG_PCI
	62
	63	/*
	64	* Partitions
	65	*/
	66	#define CONFIG_MAC_PARTITION 1
	67	#define CONFIG_DOS_PARTITION 1
	68
	69	/*
	70	* USB
	71	*/
	72	#define CONFIG_USB_OHCI
	73	#define CONFIG_USB_STORAGE
82d9c9ec BS	74	#define CONFIG_USB_CLOCK 0x0001BBBB
82d9c9ec BS	75	#define CONFIG_USB_CONFIG 0x00001000
4707fb50	76
dca3b3d6	77
079a136c JL	78	/*
	79	* BOOTP options
	80	*/
	81	#define CONFIG_BOOTP_BOOTFILESIZE
	82	#define CONFIG_BOOTP_BOOTPATH
	83	#define CONFIG_BOOTP_GATEWAY
	84	#define CONFIG_BOOTP_HOSTNAME
	85
	86
4707fb50	87	/*
dca3b3d6	88	* Command line configuration.
4707fb50	89	*/
dca3b3d6 JL	90	#define CONFIG_CMD_FAT
	91	#define CONFIG_CMD_I2C
	92	#define CONFIG_CMD_IDE
	93	#define CONFIG_CMD_PING
	94	#define CONFIG_CMD_DHCP
	95	#define CONFIG_CMD_DIAG
	96	#define CONFIG_CMD_IRQ
	97	#define CONFIG_CMD_JFFS2
	98	#define CONFIG_CMD_MII
	99	#define CONFIG_CMD_SDRAM
	100	#define CONFIG_CMD_DATE
	101	#define CONFIG_CMD_USB
	102	#define CONFIG_CMD_FAT
4707fb50	103
82d9c9ec	104
dca3b3d6	105	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
4707fb50 BS	106
	107	/*
	108	* Boot low with 16 MB Flash
	109	*/
6d0f6bcf JCPV	110	#define CONFIG_SYS_LOWBOOT 1
6d0f6bcf JCPV	111	#define CONFIG_SYS_LOWBOOT16 1
4707fb50 BS	112
	113	/*
	114	* Autobooting
	115	*/
	116	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	117
82d9c9ec	118	#define CONFIG_PREBOOT "echo;" \
32bf3d14	119	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
4707fb50 BS	120	"echo"
4707fb50 BS	121
82d9c9ec	122	#undef CONFIG_BOOTARGS
4707fb50	123
fcfed4f2	124	#define CONFIG_EXTRA_ENV_SETTINGS \
82d9c9ec BS	125	"bootcmd=run net_nfs\0" \
	126	"bootdelay=3\0" \
	127	"baudrate=115200\0" \
	128	"preboot=echo;echo Type \"run flash_nfs\" to mount root " \
	129	"filesystem over NFS; echo\0" \
fcfed4f2	130	"netdev=eth0\0" \
cce4acbb	131	"ramargs=setenv bootargs root=/dev/ram rw wdt=off \0" \
fcfed4f2 WD	132	"addip=setenv bootargs $(bootargs) " \
	133	"ip=$(ipaddr):$(serverip):$(gatewayip):" \
	134	"$(netmask):$(hostname):$(netdev):off panic=1\0" \
	135	"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
	136	"flash_self=run ramargs addip;bootm $(kernel_addr) " \
	137	"$(ramdisk_addr)\0" \
82d9c9ec	138	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
fcfed4f2	139	"nfsargs=setenv bootargs root=/dev/nfs rw " \
cce4acbb	140	"nfsroot=$(serverip):$(rootpath) wdt=off\0" \
82d9c9ec	141	"hostname=v38b\0" \
48690d80	142	"ethact=FEC\0" \
82d9c9ec BS	143	"rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \
	144	"update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \
	145	"cp.b 200000 ff000000 $(filesize);" \
	146	"prot on ff000000 ff03ffff\0" \
	147	"load=tftp 200000 $(u-boot)\0" \
	148	"netmask=255.255.0.0\0" \
	149	"ipaddr=192.168.160.18\0" \
	150	"serverip=192.168.1.1\0" \
82d9c9ec BS	151	"bootfile=/tftpboot/v38b/uImage\0" \
82d9c9ec BS	152	"u-boot=/tftpboot/v38b/u-boot.bin\0" \
fcfed4f2	153	""
4707fb50 BS	154
	155	#define CONFIG_BOOTCOMMAND "run net_nfs"
	156
4707fb50 BS	157	/*
	158	* IPB Bus clocking configuration.
	159	*/
6d0f6bcf	160	#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
82d9c9ec	161
4707fb50 BS	162	/*
	163	* I2C configuration
	164	*/
	165	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf JCPV	166	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
	167	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
	168	#define CONFIG_SYS_I2C_SLAVE 0x7F
4707fb50 BS	169
	170	/*
	171	* EEPROM configuration
	172	*/
6d0f6bcf JCPV	173	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	174	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	175	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	176	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
4707fb50 BS	177
	178	/*
	179	* RTC configuration
	180	*/
6d0f6bcf	181	#define CONFIG_SYS_I2C_RTC_ADDR 0x51
4707fb50 BS	182
	183	/*
	184	* Flash configuration - use CFI driver
	185	*/
6d0f6bcf	186	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a	187	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
6d0f6bcf JCPV	188	#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
	189	#define CONFIG_SYS_FLASH_BASE 0xFF000000
	190	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
	191	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	192	#define CONFIG_SYS_FLASH_SIZE 0x01000000 /* 16 MiB */
	193	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
	194	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */
4707fb50 BS	195
	196	/*
	197	* Environment settings
	198	*/
5a1aceb0	199	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	200	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
0e8d1586 JCPV	201	#define CONFIG_ENV_SIZE 0x10000
0e8d1586 JCPV	202	#define CONFIG_ENV_SECT_SIZE 0x10000
4707fb50 BS	203	#define CONFIG_ENV_OVERWRITE 1
	204
	205	/*
	206	* Memory map
	207	*/
6d0f6bcf JCPV	208	#define CONFIG_SYS_MBAR 0xF0000000
	209	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	210	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
4707fb50 BS	211
4707fb50 BS	212	/* Use SRAM until RAM will be available */
6d0f6bcf	213	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
553f0982	214	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
4707fb50	215
25ddd1fb	216	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	217	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
4707fb50	218
14d0a02a	219	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	220	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	221	# define CONFIG_SYS_RAMBOOT 1
4707fb50 BS	222	#endif
4707fb50 BS	223
6d0f6bcf JCPV	224	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256kB for Monitor */
	225	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128kB for malloc() */
	226	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Linux initial memory map */
4707fb50 BS	227
	228	/*
	229	* Ethernet configuration
	230	*/
	231	#define CONFIG_MPC5xxx_FEC 1
86321fc1	232	#define CONFIG_MPC5xxx_FEC_MII100
4707fb50	233	#define CONFIG_PHY_ADDR 0x00
fcfed4f2	234	#define CONFIG_MII 1
4707fb50 BS	235
	236	/*
	237	* GPIO configuration
	238	*/
6d0f6bcf	239	#define CONFIG_SYS_GPS_PORT_CONFIG 0x90001404
4707fb50 BS	240
	241	/*
	242	* Miscellaneous configurable options
	243	*/
6d0f6bcf	244	#define CONFIG_SYS_LONGHELP /* undef to save memory */
dca3b3d6	245	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	246	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
4707fb50	247	#else
6d0f6bcf	248	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
4707fb50	249	#endif
6d0f6bcf JCPV	250	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	251	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	252	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
4707fb50	253
6d0f6bcf JCPV	254	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	255	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
4707fb50	256
6d0f6bcf	257	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
4707fb50	258
6d0f6bcf	259	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
dca3b3d6	260	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	261	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
dca3b3d6 JL	262	#endif
dca3b3d6 JL	263
4707fb50 BS	264	/*
	265	* Various low-level settings
	266	*/
6d0f6bcf JCPV	267	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	268	#define CONFIG_SYS_HID0_FINAL HID0_ICE
4707fb50	269
6d0f6bcf JCPV	270	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	271	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	272	#define CONFIG_SYS_BOOTCS_CFG 0x00047801
	273	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	274	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
4707fb50	275
6d0f6bcf JCPV	276	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	277	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
4707fb50	278
6d0f6bcf	279	#define CONFIG_SYS_RESET_ADDRESS 0xff000000
4707fb50	280
82d9c9ec BS	281	/*
82d9c9ec BS	282	* IDE/ATA (supports IDE harddisk)
4707fb50	283	*/
82d9c9ec BS	284	#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */
	285	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	286	#undef CONFIG_IDE_LED /* LED for ide not supported */
4707fb50	287
82d9c9ec	288	#define CONFIG_IDE_RESET /* reset for ide supported */
4707fb50 BS	289	#define CONFIG_IDE_PREINIT
4707fb50 BS	290
6d0f6bcf JCPV	291	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	292	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
4707fb50	293
6d0f6bcf	294	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
4707fb50	295
6d0f6bcf	296	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
4707fb50	297
6d0f6bcf	298	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) /* data I/O offset */
4707fb50	299
6d0f6bcf	300	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* normal register accesses offset */
4707fb50	301
6d0f6bcf	302	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) /* alternate registers offset */
4707fb50	303
6d0f6bcf	304	#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
4707fb50	305
82d9c9ec BS	306	/*
	307	* Status LED
	308	*/
	309	#define CONFIG_STATUS_LED /* Status LED enabled */
	310	#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
4707fb50	311
6d0f6bcf	312	#define CONFIG_SYS_LED_BASE MPC5XXX_GPT7_ENABLE /* Timer 7 GPIO */
4707fb50	313	#ifndef __ASSEMBLY__
4707fb50 BS	314	typedef unsigned int led_id_t;
	315
	316	#define __led_toggle(_msk) \
	317	do { \
6d0f6bcf	318	((volatile long ) (CONFIG_SYS_LED_BASE)) ^= (_msk); \
4707fb50 BS	319	} while(0)
	320
	321	#define __led_set(_msk, _st) \
	322	do { \
	323	if ((_st)) \
6d0f6bcf	324	((volatile long ) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \
4707fb50	325	else \
6d0f6bcf	326	((volatile long ) (CONFIG_SYS_LED_BASE)) \|= (_msk); \
4707fb50 BS	327	} while(0)
	328
	329	#define __led_init(_msk, st) \
82d9c9ec	330	do { \
6d0f6bcf	331	((volatile long ) (CONFIG_SYS_LED_BASE)) \|= 0x34; \
82d9c9ec BS	332	} while(0)
82d9c9ec BS	333	#endif /* __ASSEMBLY__ */
4707fb50 BS	334
4707fb50 BS	335	#endif /* __CONFIG_H */