[people/ms/u-boot.git] / include / configs / v38b.h

/*
 * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering,
 * wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MPC5200			1	/* This is an MPC5200 CPU */
#define CONFIG_V38B			1	/* ...on V38B board */
#define CONFIG_DISPLAY_BOARDINFO

#define	CONFIG_SYS_TEXT_BASE		0xFF000000

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000	/* ...running at 33.000000MHz */

#define CONFIG_RTC_PCF8563		1	/* has PCF8563 RTC */
#define CONFIG_MPC5200_DDR		1	/* has DDR SDRAM */

#undef CONFIG_HW_WATCHDOG			/* don't use watchdog */

#define CONFIG_NETCONSOLE		1

#define CONFIG_BOARD_EARLY_INIT_R	1	/* do board-specific init */
#define CONFIG_BOARD_EARLY_INIT_F	1	/* do board-specific init */
#define CONFIG_MISC_INIT_R

#define CONFIG_SYS_XLB_PIPELINING		1	/* gives better performance */

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * DDR
 */
#define SDRAM_DDR		1	/* is DDR */
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE		0x018D0000
#define SDRAM_EMODE		0x40090000
#define SDRAM_CONTROL		0x704f0f00
#define SDRAM_CONFIG1		0x73722930
#define SDRAM_CONFIG2		0x47770000
#define SDRAM_TAPDELAY		0x10000000

/*
 * PCI - no suport
 */
#undef CONFIG_PCI

/*
 * Partitions
 */
#define CONFIG_MAC_PARTITION	1
#define CONFIG_DOS_PARTITION	1

/*
 * USB
 */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00001000


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_DATE
#define CONFIG_CMD_USB
#define CONFIG_CMD_FAT


#define CONFIG_TIMESTAMP		/* Print image info with timestamp */

/*
 * Boot low with 16 MB Flash
 */
#define CONFIG_SYS_LOWBOOT		1
#define CONFIG_SYS_LOWBOOT16		1

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"bootcmd=run net_nfs\0"						\
	"bootdelay=3\0"							\
	"baudrate=115200\0"						\
	"preboot=echo;echo Type \"run flash_nfs\" to mount root "	\
		"filesystem over NFS; echo\0"				\
	"netdev=eth0\0"							\
	"ramargs=setenv bootargs root=/dev/ram rw wdt=off \0"		\
	"addip=setenv bootargs $(bootargs) "				\
		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
		"$(netmask):$(hostname):$(netdev):off panic=1\0"	\
	"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0"		\
	"flash_self=run ramargs addip;bootm $(kernel_addr) "		\
		"$(ramdisk_addr)\0"					\
	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$(serverip):$(rootpath) wdt=off\0"		\
	"hostname=v38b\0"						\
	"ethact=FEC\0"							\
	"rootpath=/opt/eldk-3.1.1/ppc_6xx\0"				\
	"update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; "	\
		"cp.b 200000 ff000000 $(filesize);"			\
		"prot on ff000000 ff03ffff\0"				\
	"load=tftp 200000 $(u-boot)\0"					\
	"netmask=255.255.0.0\0"						\
	"ipaddr=192.168.160.18\0"					\
	"serverip=192.168.1.1\0"					\
	"bootfile=/tftpboot/v38b/uImage\0"				\
	"u-boot=/tftpboot/v38b/u-boot.bin\0"				\
	""

#define CONFIG_BOOTCOMMAND	"run net_nfs"

/*
 * IPB Bus clocking configuration.
 */
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK			/* define for 133MHz speed */

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
#define CONFIG_SYS_I2C_SPEED		100000	/* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70

/*
 * RTC configuration
 */
#define CONFIG_SYS_I2C_RTC_ADDR		0x51

/*
 * Flash configuration - use CFI driver
 */
#define CONFIG_SYS_FLASH_CFI		1		/* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER	1		/* Use the common driver */
#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1
#define CONFIG_SYS_FLASH_BASE		0xFF000000
#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max num of flash banks */
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_FLASH_SIZE		0x01000000	/* 16 MiB */
#define CONFIG_SYS_MAX_FLASH_SECT	256		/* max num of sects on one chip */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1	/* flash write speed-up */

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)
#define CONFIG_ENV_SIZE		0x10000
#define CONFIG_ENV_SECT_SIZE	0x10000
#define CONFIG_ENV_OVERWRITE	1

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128kB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Linux initial memory map */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
#define CONFIG_PHY_ADDR		0x00
#define CONFIG_MII		1

/*
 * GPIO configuration
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x90001404

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM */

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00047801
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333

#define CONFIG_SYS_RESET_ADDRESS	0xff000000

/*
 * IDE/ATA (supports IDE harddisk)
 */
#undef CONFIG_IDE_8xx_PCCARD		/* Don't use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT		/* Direct IDE not supported */
#undef CONFIG_IDE_LED			/* LED for ide not supported */

#define CONFIG_IDE_RESET		/* reset for ide supported */
#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus */
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus */

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA

#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)	/* data I/O offset */

#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)	/* normal register accesses offset */

#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)	/* alternate registers offset */

#define CONFIG_SYS_ATA_STRIDE		4		/* Interval between registers */

/*
 * Status LED
 */
#define  CONFIG_STATUS_LED		/* Status LED enabled */
#define  CONFIG_BOARD_SPECIFIC_LED	/* version has board specific leds */

#define CONFIG_SYS_LED_BASE	MPC5XXX_GPT7_ENABLE	/* Timer 7 GPIO */
#ifndef __ASSEMBLY__
typedef unsigned int led_id_t;

#define __led_toggle(_msk) \
	do { \
		*((volatile long *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \
	} while(0)

#define __led_set(_msk, _st) \
	do { \
		if ((_st)) \
			*((volatile long *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \
		else \
			*((volatile long *) (CONFIG_SYS_LED_BASE)) |= (_msk); \
	} while(0)

#define __led_init(_msk, st) \
	do { \
		*((volatile long *) (CONFIG_SYS_LED_BASE)) |= 0x34; \
	} while(0)
#endif /* __ASSEMBLY__ */

#endif /* __CONFIG_H */
Commit	Line	Data
4707fb50	1	/*
82d9c9ec	2	* (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering,
4707fb50 BS	3	* wd@denx.de.
4707fb50 BS	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
4707fb50 BS	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
4707fb50 BS	11	/*
	12	* High Level Configuration Options
	13	* (easy to change)
82d9c9ec	14	*/
82d9c9ec BS	15	#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
82d9c9ec BS	16	#define CONFIG_V38B 1 /* ...on V38B board */
e1219229	17	#define CONFIG_DISPLAY_BOARDINFO
2ae18241 WD	18
	19	#define CONFIG_SYS_TEXT_BASE 0xFF000000
	20
6d0f6bcf	21	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */
4707fb50	22
82d9c9ec BS	23	#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */
82d9c9ec BS	24	#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */
4707fb50	25
ce3f1a40	26	#undef CONFIG_HW_WATCHDOG /* don't use watchdog */
4707fb50 BS	27
	28	#define CONFIG_NETCONSOLE 1
	29
82d9c9ec	30	#define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */
cce4acbb	31	#define CONFIG_BOARD_EARLY_INIT_F 1 /* do board-specific init */
d8d21e69	32	#define CONFIG_MISC_INIT_R
4707fb50	33
6d0f6bcf	34	#define CONFIG_SYS_XLB_PIPELINING 1 /* gives better performance */
4707fb50	35
31d82672 BB	36	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	37
4707fb50 BS	38	/*
	39	* Serial console configuration
	40	*/
82d9c9ec BS	41	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
82d9c9ec BS	42	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf	43	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
4707fb50	44
4707fb50 BS	45	/*
	46	* DDR
	47	*/
	48	#define SDRAM_DDR 1 /* is DDR */
	49	/* Settings for XLB = 132 MHz */
	50	#define SDRAM_MODE 0x018D0000
	51	#define SDRAM_EMODE 0x40090000
	52	#define SDRAM_CONTROL 0x704f0f00
	53	#define SDRAM_CONFIG1 0x73722930
	54	#define SDRAM_CONFIG2 0x47770000
	55	#define SDRAM_TAPDELAY 0x10000000
	56
4707fb50 BS	57	/*
	58	* PCI - no suport
	59	*/
	60	#undef CONFIG_PCI
	61
	62	/*
	63	* Partitions
	64	*/
	65	#define CONFIG_MAC_PARTITION 1
	66	#define CONFIG_DOS_PARTITION 1
	67
	68	/*
	69	* USB
	70	*/
	71	#define CONFIG_USB_OHCI
	72	#define CONFIG_USB_STORAGE
82d9c9ec BS	73	#define CONFIG_USB_CLOCK 0x0001BBBB
82d9c9ec BS	74	#define CONFIG_USB_CONFIG 0x00001000
4707fb50	75
dca3b3d6	76
079a136c JL	77	/*
	78	* BOOTP options
	79	*/
	80	#define CONFIG_BOOTP_BOOTFILESIZE
	81	#define CONFIG_BOOTP_BOOTPATH
	82	#define CONFIG_BOOTP_GATEWAY
	83	#define CONFIG_BOOTP_HOSTNAME
	84
	85
4707fb50	86	/*
dca3b3d6	87	* Command line configuration.
4707fb50	88	*/
dca3b3d6 JL	89	#define CONFIG_CMD_FAT
	90	#define CONFIG_CMD_I2C
	91	#define CONFIG_CMD_IDE
	92	#define CONFIG_CMD_PING
	93	#define CONFIG_CMD_DHCP
	94	#define CONFIG_CMD_DIAG
	95	#define CONFIG_CMD_IRQ
	96	#define CONFIG_CMD_JFFS2
	97	#define CONFIG_CMD_MII
	98	#define CONFIG_CMD_SDRAM
	99	#define CONFIG_CMD_DATE
	100	#define CONFIG_CMD_USB
	101	#define CONFIG_CMD_FAT
4707fb50	102
82d9c9ec	103
dca3b3d6	104	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
4707fb50 BS	105
	106	/*
	107	* Boot low with 16 MB Flash
	108	*/
6d0f6bcf JCPV	109	#define CONFIG_SYS_LOWBOOT 1
6d0f6bcf JCPV	110	#define CONFIG_SYS_LOWBOOT16 1
4707fb50 BS	111
	112	/*
	113	* Autobooting
	114	*/
	115	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	116
82d9c9ec	117	#define CONFIG_PREBOOT "echo;" \
32bf3d14	118	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
4707fb50 BS	119	"echo"
4707fb50 BS	120
82d9c9ec	121	#undef CONFIG_BOOTARGS
4707fb50	122
fcfed4f2	123	#define CONFIG_EXTRA_ENV_SETTINGS \
82d9c9ec BS	124	"bootcmd=run net_nfs\0" \
	125	"bootdelay=3\0" \
	126	"baudrate=115200\0" \
	127	"preboot=echo;echo Type \"run flash_nfs\" to mount root " \
	128	"filesystem over NFS; echo\0" \
fcfed4f2	129	"netdev=eth0\0" \
cce4acbb	130	"ramargs=setenv bootargs root=/dev/ram rw wdt=off \0" \
fcfed4f2 WD	131	"addip=setenv bootargs $(bootargs) " \
	132	"ip=$(ipaddr):$(serverip):$(gatewayip):" \
	133	"$(netmask):$(hostname):$(netdev):off panic=1\0" \
	134	"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
	135	"flash_self=run ramargs addip;bootm $(kernel_addr) " \
	136	"$(ramdisk_addr)\0" \
82d9c9ec	137	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
fcfed4f2	138	"nfsargs=setenv bootargs root=/dev/nfs rw " \
cce4acbb	139	"nfsroot=$(serverip):$(rootpath) wdt=off\0" \
82d9c9ec	140	"hostname=v38b\0" \
48690d80	141	"ethact=FEC\0" \
82d9c9ec BS	142	"rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \
	143	"update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \
	144	"cp.b 200000 ff000000 $(filesize);" \
	145	"prot on ff000000 ff03ffff\0" \
	146	"load=tftp 200000 $(u-boot)\0" \
	147	"netmask=255.255.0.0\0" \
	148	"ipaddr=192.168.160.18\0" \
	149	"serverip=192.168.1.1\0" \
82d9c9ec BS	150	"bootfile=/tftpboot/v38b/uImage\0" \
82d9c9ec BS	151	"u-boot=/tftpboot/v38b/u-boot.bin\0" \
fcfed4f2	152	""
4707fb50 BS	153
	154	#define CONFIG_BOOTCOMMAND "run net_nfs"
	155
4707fb50 BS	156	/*
	157	* IPB Bus clocking configuration.
	158	*/
6d0f6bcf	159	#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
82d9c9ec	160
4707fb50 BS	161	/*
	162	* I2C configuration
	163	*/
	164	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf JCPV	165	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
	166	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
	167	#define CONFIG_SYS_I2C_SLAVE 0x7F
4707fb50 BS	168
	169	/*
	170	* EEPROM configuration
	171	*/
6d0f6bcf JCPV	172	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	173	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	174	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	175	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
4707fb50 BS	176
	177	/*
	178	* RTC configuration
	179	*/
6d0f6bcf	180	#define CONFIG_SYS_I2C_RTC_ADDR 0x51
4707fb50 BS	181
	182	/*
	183	* Flash configuration - use CFI driver
	184	*/
6d0f6bcf	185	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a	186	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
6d0f6bcf JCPV	187	#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
	188	#define CONFIG_SYS_FLASH_BASE 0xFF000000
	189	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
	190	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	191	#define CONFIG_SYS_FLASH_SIZE 0x01000000 /* 16 MiB */
	192	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
	193	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */
4707fb50 BS	194
	195	/*
	196	* Environment settings
	197	*/
5a1aceb0	198	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	199	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
0e8d1586 JCPV	200	#define CONFIG_ENV_SIZE 0x10000
0e8d1586 JCPV	201	#define CONFIG_ENV_SECT_SIZE 0x10000
4707fb50 BS	202	#define CONFIG_ENV_OVERWRITE 1
	203
	204	/*
	205	* Memory map
	206	*/
6d0f6bcf JCPV	207	#define CONFIG_SYS_MBAR 0xF0000000
	208	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	209	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
4707fb50 BS	210
4707fb50 BS	211	/* Use SRAM until RAM will be available */
6d0f6bcf	212	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
553f0982	213	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
4707fb50	214
25ddd1fb	215	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	216	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
4707fb50	217
14d0a02a	218	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	219	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	220	# define CONFIG_SYS_RAMBOOT 1
4707fb50 BS	221	#endif
4707fb50 BS	222
6d0f6bcf JCPV	223	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256kB for Monitor */
	224	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128kB for malloc() */
	225	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Linux initial memory map */
4707fb50 BS	226
	227	/*
	228	* Ethernet configuration
	229	*/
	230	#define CONFIG_MPC5xxx_FEC 1
86321fc1	231	#define CONFIG_MPC5xxx_FEC_MII100
4707fb50	232	#define CONFIG_PHY_ADDR 0x00
fcfed4f2	233	#define CONFIG_MII 1
4707fb50 BS	234
	235	/*
	236	* GPIO configuration
	237	*/
6d0f6bcf	238	#define CONFIG_SYS_GPS_PORT_CONFIG 0x90001404
4707fb50 BS	239
	240	/*
	241	* Miscellaneous configurable options
	242	*/
6d0f6bcf	243	#define CONFIG_SYS_LONGHELP /* undef to save memory */
dca3b3d6	244	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	245	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
4707fb50	246	#else
6d0f6bcf	247	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
4707fb50	248	#endif
6d0f6bcf JCPV	249	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	250	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	251	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
4707fb50	252
6d0f6bcf JCPV	253	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	254	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
4707fb50	255
6d0f6bcf	256	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
4707fb50	257
6d0f6bcf	258	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
dca3b3d6	259	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	260	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
dca3b3d6 JL	261	#endif
dca3b3d6 JL	262
4707fb50 BS	263	/*
	264	* Various low-level settings
	265	*/
6d0f6bcf JCPV	266	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	267	#define CONFIG_SYS_HID0_FINAL HID0_ICE
4707fb50	268
6d0f6bcf JCPV	269	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	270	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	271	#define CONFIG_SYS_BOOTCS_CFG 0x00047801
	272	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	273	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
4707fb50	274
6d0f6bcf JCPV	275	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	276	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
4707fb50	277
6d0f6bcf	278	#define CONFIG_SYS_RESET_ADDRESS 0xff000000
4707fb50	279
82d9c9ec BS	280	/*
82d9c9ec BS	281	* IDE/ATA (supports IDE harddisk)
4707fb50	282	*/
82d9c9ec BS	283	#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */
	284	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	285	#undef CONFIG_IDE_LED /* LED for ide not supported */
4707fb50	286
82d9c9ec	287	#define CONFIG_IDE_RESET /* reset for ide supported */
4707fb50 BS	288	#define CONFIG_IDE_PREINIT
4707fb50 BS	289
6d0f6bcf JCPV	290	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	291	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
4707fb50	292
6d0f6bcf	293	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
4707fb50	294
6d0f6bcf	295	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
4707fb50	296
6d0f6bcf	297	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) /* data I/O offset */
4707fb50	298
6d0f6bcf	299	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* normal register accesses offset */
4707fb50	300
6d0f6bcf	301	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) /* alternate registers offset */
4707fb50	302
6d0f6bcf	303	#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
4707fb50	304
82d9c9ec BS	305	/*
	306	* Status LED
	307	*/
	308	#define CONFIG_STATUS_LED /* Status LED enabled */
	309	#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
4707fb50	310
6d0f6bcf	311	#define CONFIG_SYS_LED_BASE MPC5XXX_GPT7_ENABLE /* Timer 7 GPIO */
4707fb50	312	#ifndef __ASSEMBLY__
4707fb50 BS	313	typedef unsigned int led_id_t;
	314
	315	#define __led_toggle(_msk) \
	316	do { \
6d0f6bcf	317	((volatile long ) (CONFIG_SYS_LED_BASE)) ^= (_msk); \
4707fb50 BS	318	} while(0)
	319
	320	#define __led_set(_msk, _st) \
	321	do { \
	322	if ((_st)) \
6d0f6bcf	323	((volatile long ) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \
4707fb50	324	else \
6d0f6bcf	325	((volatile long ) (CONFIG_SYS_LED_BASE)) \|= (_msk); \
4707fb50 BS	326	} while(0)
	327
	328	#define __led_init(_msk, st) \
82d9c9ec	329	do { \
6d0f6bcf	330	((volatile long ) (CONFIG_SYS_LED_BASE)) \|= 0x34; \
82d9c9ec BS	331	} while(0)
82d9c9ec BS	332	#endif /* __ASSEMBLY__ */
4707fb50 BS	333
4707fb50 BS	334	#endif /* __CONFIG_H */