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4707fb50 | 1 | /* |
82d9c9ec | 2 | * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering, |
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3 | * wd@denx.de. |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
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6 | */ |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
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11 | /* |
12 | * High Level Configuration Options | |
13 | * (easy to change) | |
82d9c9ec | 14 | */ |
82d9c9ec BS |
15 | #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ |
16 | #define CONFIG_V38B 1 /* ...on V38B board */ | |
2ae18241 WD |
17 | |
18 | #define CONFIG_SYS_TEXT_BASE 0xFF000000 | |
19 | ||
6d0f6bcf | 20 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */ |
4707fb50 | 21 | |
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22 | #define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ |
23 | #define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ | |
4707fb50 | 24 | |
ce3f1a40 | 25 | #undef CONFIG_HW_WATCHDOG /* don't use watchdog */ |
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26 | |
27 | #define CONFIG_NETCONSOLE 1 | |
28 | ||
82d9c9ec | 29 | #define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */ |
d8d21e69 | 30 | #define CONFIG_MISC_INIT_R |
4707fb50 | 31 | |
6d0f6bcf | 32 | #define CONFIG_SYS_XLB_PIPELINING 1 /* gives better performance */ |
4707fb50 | 33 | |
31d82672 BB |
34 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
35 | ||
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36 | /* |
37 | * Serial console configuration | |
38 | */ | |
82d9c9ec | 39 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ |
6d0f6bcf | 40 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
4707fb50 | 41 | |
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42 | /* |
43 | * DDR | |
44 | */ | |
45 | #define SDRAM_DDR 1 /* is DDR */ | |
46 | /* Settings for XLB = 132 MHz */ | |
47 | #define SDRAM_MODE 0x018D0000 | |
48 | #define SDRAM_EMODE 0x40090000 | |
49 | #define SDRAM_CONTROL 0x704f0f00 | |
50 | #define SDRAM_CONFIG1 0x73722930 | |
51 | #define SDRAM_CONFIG2 0x47770000 | |
52 | #define SDRAM_TAPDELAY 0x10000000 | |
53 | ||
4707fb50 | 54 | /* |
62a3b7dd | 55 | * PCI - no support |
4707fb50 | 56 | */ |
4707fb50 | 57 | |
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58 | /* |
59 | * USB | |
60 | */ | |
61 | #define CONFIG_USB_OHCI | |
82d9c9ec BS |
62 | #define CONFIG_USB_CLOCK 0x0001BBBB |
63 | #define CONFIG_USB_CONFIG 0x00001000 | |
4707fb50 | 64 | |
079a136c JL |
65 | /* |
66 | * BOOTP options | |
67 | */ | |
68 | #define CONFIG_BOOTP_BOOTFILESIZE | |
69 | #define CONFIG_BOOTP_BOOTPATH | |
70 | #define CONFIG_BOOTP_GATEWAY | |
71 | #define CONFIG_BOOTP_HOSTNAME | |
72 | ||
4707fb50 | 73 | /* |
dca3b3d6 | 74 | * Command line configuration. |
4707fb50 | 75 | */ |
dca3b3d6 | 76 | #define CONFIG_CMD_SDRAM |
4707fb50 | 77 | |
dca3b3d6 | 78 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
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79 | |
80 | /* | |
81 | * Boot low with 16 MB Flash | |
82 | */ | |
6d0f6bcf JCPV |
83 | #define CONFIG_SYS_LOWBOOT 1 |
84 | #define CONFIG_SYS_LOWBOOT16 1 | |
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85 | |
86 | /* | |
87 | * Autobooting | |
88 | */ | |
4707fb50 | 89 | |
82d9c9ec | 90 | #define CONFIG_PREBOOT "echo;" \ |
32bf3d14 | 91 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
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92 | "echo" |
93 | ||
82d9c9ec | 94 | #undef CONFIG_BOOTARGS |
4707fb50 | 95 | |
fcfed4f2 | 96 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
82d9c9ec BS |
97 | "bootcmd=run net_nfs\0" \ |
98 | "bootdelay=3\0" \ | |
99 | "baudrate=115200\0" \ | |
100 | "preboot=echo;echo Type \"run flash_nfs\" to mount root " \ | |
101 | "filesystem over NFS; echo\0" \ | |
fcfed4f2 | 102 | "netdev=eth0\0" \ |
cce4acbb | 103 | "ramargs=setenv bootargs root=/dev/ram rw wdt=off \0" \ |
fcfed4f2 WD |
104 | "addip=setenv bootargs $(bootargs) " \ |
105 | "ip=$(ipaddr):$(serverip):$(gatewayip):" \ | |
106 | "$(netmask):$(hostname):$(netdev):off panic=1\0" \ | |
107 | "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ | |
108 | "flash_self=run ramargs addip;bootm $(kernel_addr) " \ | |
109 | "$(ramdisk_addr)\0" \ | |
82d9c9ec | 110 | "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ |
fcfed4f2 | 111 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
cce4acbb | 112 | "nfsroot=$(serverip):$(rootpath) wdt=off\0" \ |
82d9c9ec | 113 | "hostname=v38b\0" \ |
48690d80 | 114 | "ethact=FEC\0" \ |
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115 | "rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \ |
116 | "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \ | |
117 | "cp.b 200000 ff000000 $(filesize);" \ | |
118 | "prot on ff000000 ff03ffff\0" \ | |
119 | "load=tftp 200000 $(u-boot)\0" \ | |
120 | "netmask=255.255.0.0\0" \ | |
121 | "ipaddr=192.168.160.18\0" \ | |
122 | "serverip=192.168.1.1\0" \ | |
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123 | "bootfile=/tftpboot/v38b/uImage\0" \ |
124 | "u-boot=/tftpboot/v38b/u-boot.bin\0" \ | |
fcfed4f2 | 125 | "" |
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126 | |
127 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
128 | ||
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129 | /* |
130 | * IPB Bus clocking configuration. | |
131 | */ | |
6d0f6bcf | 132 | #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
82d9c9ec | 133 | |
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134 | /* |
135 | * Flash configuration - use CFI driver | |
136 | */ | |
6d0f6bcf | 137 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 138 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6d0f6bcf JCPV |
139 | #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 |
140 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 | |
141 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ | |
142 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
143 | #define CONFIG_SYS_FLASH_SIZE 0x01000000 /* 16 MiB */ | |
144 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ | |
145 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ | |
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146 | |
147 | /* | |
148 | * Environment settings | |
149 | */ | |
5a1aceb0 | 150 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 151 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) |
0e8d1586 JCPV |
152 | #define CONFIG_ENV_SIZE 0x10000 |
153 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
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154 | #define CONFIG_ENV_OVERWRITE 1 |
155 | ||
156 | /* | |
157 | * Memory map | |
158 | */ | |
6d0f6bcf JCPV |
159 | #define CONFIG_SYS_MBAR 0xF0000000 |
160 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
161 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
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162 | |
163 | /* Use SRAM until RAM will be available */ | |
6d0f6bcf | 164 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
553f0982 | 165 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ |
4707fb50 | 166 | |
25ddd1fb | 167 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 168 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
4707fb50 | 169 | |
14d0a02a | 170 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
171 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
172 | # define CONFIG_SYS_RAMBOOT 1 | |
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173 | #endif |
174 | ||
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256kB for Monitor */ |
176 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128kB for malloc() */ | |
177 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Linux initial memory map */ | |
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178 | |
179 | /* | |
180 | * Ethernet configuration | |
181 | */ | |
182 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 183 | #define CONFIG_MPC5xxx_FEC_MII100 |
4707fb50 | 184 | #define CONFIG_PHY_ADDR 0x00 |
fcfed4f2 | 185 | #define CONFIG_MII 1 |
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186 | |
187 | /* | |
188 | * GPIO configuration | |
189 | */ | |
6d0f6bcf | 190 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x90001404 |
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191 | |
192 | /* | |
193 | * Miscellaneous configurable options | |
194 | */ | |
6d0f6bcf | 195 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
dca3b3d6 | 196 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 197 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
4707fb50 | 198 | #else |
6d0f6bcf | 199 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
4707fb50 | 200 | #endif |
6d0f6bcf JCPV |
201 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
202 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
203 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
4707fb50 | 204 | |
6d0f6bcf JCPV |
205 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
206 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
4707fb50 | 207 | |
6d0f6bcf | 208 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
4707fb50 | 209 | |
6d0f6bcf | 210 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
dca3b3d6 | 211 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 212 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
dca3b3d6 JL |
213 | #endif |
214 | ||
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215 | /* |
216 | * Various low-level settings | |
217 | */ | |
6d0f6bcf JCPV |
218 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
219 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
4707fb50 | 220 | |
6d0f6bcf JCPV |
221 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
222 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
223 | #define CONFIG_SYS_BOOTCS_CFG 0x00047801 | |
224 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE | |
225 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
4707fb50 | 226 | |
6d0f6bcf JCPV |
227 | #define CONFIG_SYS_CS_BURST 0x00000000 |
228 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
4707fb50 | 229 | |
6d0f6bcf | 230 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
4707fb50 | 231 | |
82d9c9ec BS |
232 | /* |
233 | * IDE/ATA (supports IDE harddisk) | |
4707fb50 | 234 | */ |
82d9c9ec | 235 | #undef CONFIG_IDE_LED /* LED for ide not supported */ |
4707fb50 | 236 | |
82d9c9ec | 237 | #define CONFIG_IDE_RESET /* reset for ide supported */ |
4707fb50 BS |
238 | #define CONFIG_IDE_PREINIT |
239 | ||
6d0f6bcf JCPV |
240 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
241 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
4707fb50 | 242 | |
6d0f6bcf | 243 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
4707fb50 | 244 | |
6d0f6bcf | 245 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
4707fb50 | 246 | |
6d0f6bcf | 247 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) /* data I/O offset */ |
4707fb50 | 248 | |
6d0f6bcf | 249 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* normal register accesses offset */ |
4707fb50 | 250 | |
6d0f6bcf | 251 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) /* alternate registers offset */ |
4707fb50 | 252 | |
6d0f6bcf | 253 | #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ |
4707fb50 | 254 | |
82d9c9ec BS |
255 | /* |
256 | * Status LED | |
257 | */ | |
4707fb50 | 258 | |
6d0f6bcf | 259 | #define CONFIG_SYS_LED_BASE MPC5XXX_GPT7_ENABLE /* Timer 7 GPIO */ |
4707fb50 | 260 | #ifndef __ASSEMBLY__ |
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261 | typedef unsigned int led_id_t; |
262 | ||
263 | #define __led_toggle(_msk) \ | |
264 | do { \ | |
6d0f6bcf | 265 | *((volatile long *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \ |
4707fb50 BS |
266 | } while(0) |
267 | ||
268 | #define __led_set(_msk, _st) \ | |
269 | do { \ | |
270 | if ((_st)) \ | |
6d0f6bcf | 271 | *((volatile long *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \ |
4707fb50 | 272 | else \ |
6d0f6bcf | 273 | *((volatile long *) (CONFIG_SYS_LED_BASE)) |= (_msk); \ |
4707fb50 BS |
274 | } while(0) |
275 | ||
276 | #define __led_init(_msk, st) \ | |
82d9c9ec | 277 | do { \ |
6d0f6bcf | 278 | *((volatile long *) (CONFIG_SYS_LED_BASE)) |= 0x34; \ |
82d9c9ec BS |
279 | } while(0) |
280 | #endif /* __ASSEMBLY__ */ | |
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281 | |
282 | #endif /* __CONFIG_H */ |