[people/ms/u-boot.git] / include / configs / vct.h

/*
 * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * This file contains the configuration parameters for the VCT board
 * family:
 *
 * vct_premium
 * vct_premium_small
 * vct_premium_onenand
 * vct_premium_onenand_small
 * vct_platinum
 * vct_platinum_small
 * vct_platinum_onenand
 * vct_platinum_onenand_small
 * vct_platinumavc
 * vct_platinumavc_small
 * vct_platinumavc_onenand
 * vct_platinumavc_onenand_small
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CPU_CLOCK_RATE			324000000 /* Clock for the MIPS core */
#define CONFIG_SYS_MIPS_TIMER_FREQ	(CPU_CLOCK_RATE / 2)

#define CONFIG_SKIP_LOWLEVEL_INIT	/* SDRAM is initialized by the bootstrap code */

#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
#define CONFIG_SYS_MALLOC_LEN		(1 << 20)
#define CONFIG_SYS_BOOTPARAMS_LEN	(128 << 10)
#define CONFIG_SYS_INIT_SP_OFFSET	0x400000

#if !defined(CONFIG_VCT_NAND) && !defined(CONFIG_VCT_ONENAND)
#define CONFIG_VCT_NOR
#endif

/*
 * UART
 */
#ifdef CONFIG_VCT_PLATINUMAVC
#define UART_1_BASE		0xBDC30000
#else
#define UART_1_BASE		0xBF89C000
#endif

#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4
#define CONFIG_SYS_NS16550_COM1		UART_1_BASE
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_CLK		921600

/*
 * SDRAM
 */
#define CONFIG_SYS_SDRAM_BASE		0x80000000
#define CONFIG_SYS_MBYTES_SDRAM		128
#define CONFIG_SYS_MEMTEST_START	0x80200000
#define CONFIG_SYS_MEMTEST_END		0x80400000
#define CONFIG_SYS_LOAD_ADDR		0x80400000	/* default load address */

#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
/*
 * SMSC91C11x Network Card
 */
#define CONFIG_SMC911X
#define CONFIG_SMC911X_BASE	0x00000000
#define CONFIG_SMC911X_32_BIT
#define CONFIG_NET_RETRY_COUNT		20
#endif

/*
 * Commands
 */

/*
 * Only Premium/Platinum have ethernet support right now
 */
#if (defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)) && \
	!defined(CONFIG_VCT_SMALL_IMAGE)
#endif

/*
 * Only Premium/Platinum have USB-EHCI support right now
 */
#if (defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)) && \
	!defined(CONFIG_VCT_SMALL_IMAGE)
#endif

#if defined(CONFIG_CMD_USB)
#define CONFIG_SUPPORT_VFAT

/*
 * USB/EHCI
 */
#define CONFIG_USB_EHCI_VCT		/* on VCT platform		*/
#define CONFIG_EHCI_MMIO_BIG_ENDIAN
#define CONFIG_EHCI_DESC_BIG_ENDIAN
#define CONFIG_EHCI_IS_TDI
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
#endif /* CONFIG_CMD_USB */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_SUBNETMASK

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size	*/
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_TIMESTAMP			/* Print image info with timestamp */
#define CONFIG_CMDLINE_EDITING			/* add command line history	*/

/*
 * FLASH and environment organization
 */
#if defined(CONFIG_VCT_NOR)
#define CONFIG_FLASH_NOT_MEM_MAPPED

/*
 * We need special accessor functions for the CFI FLASH driver. This
 * can be enabled via the CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS option.
 */
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS

/*
 * For the non-memory-mapped NOR FLASH, we need to define the
 * NOR FLASH area. This can't be detected via the addr2info()
 * function, since we check for flash access in the very early
 * U-Boot code, before the NOR FLASH is detected.
 */
#define CONFIG_FLASH_BASE		0xb0000000
#define CONFIG_FLASH_END		0xbfffffff

/*
 * CFI driver settings
 */
#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1	/* Use AMD (Spansion) reset cmd */
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT	/* no byte writes on IXP4xx	*/

#define CONFIG_SYS_FLASH_BASE		0xb0000000
#define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x10000		/* size of one complete sector	*/
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
#endif /* CONFIG_ENV_IS_IN_FLASH */
#endif /* CONFIG_VCT_NOR */

#if defined(CONFIG_VCT_ONENAND)
#define CONFIG_USE_ONENAND_BOARD_INIT
#define	CONFIG_SYS_ONENAND_BASE		0x00000000	/* this is not real address */
#define CONFIG_SYS_FLASH_BASE		0x00000000
#define CONFIG_ENV_ADDR			(128 << 10)	/* after compr. U-Boot image */
#define	CONFIG_ENV_SIZE			(128 << 10)	/* erase size */
#endif /* CONFIG_VCT_ONENAND */

/*
 * I2C/EEPROM
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED	83000	/* 83 kHz is supposed to work */
#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7f

/*
 * Software (bit-bang) I2C driver configuration
 */
#define CONFIG_SYS_GPIO_I2C_SCL		11
#define CONFIG_SYS_GPIO_I2C_SDA		10

#ifndef __ASSEMBLY__
int vct_gpio_dir(int pin, int dir);
void vct_gpio_set(int pin, int val);
int vct_gpio_get(int pin);
#endif

#define I2C_INIT	vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SCL, 1)
#define I2C_ACTIVE	vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 1)
#define I2C_TRISTATE	vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 0)
#define I2C_READ	vct_gpio_get(CONFIG_SYS_GPIO_I2C_SDA)
#define I2C_SDA(bit)	vct_gpio_set(CONFIG_SYS_GPIO_I2C_SDA, bit)
#define I2C_SCL(bit)	vct_gpio_set(CONFIG_SYS_GPIO_I2C_SCL, bit)
#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
/* CAT24WC32 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
					/* 32 byte page write mode using*/
					/* last 5 bits of the address	*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */

#define CONFIG_BOOTCOMMAND	"run test3"

/*
 * UBI configuration
 */
#if defined(CONFIG_VCT_ONENAND)
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS

#define MTDIDS_DEFAULT		"onenand0=onenand"
#define MTDPARTS_DEFAULT	"mtdparts=onenand:128k(u-boot),"	\
					"128k(env),"		\
					"20m(kernel),"		\
					"-(rootfs)"
#endif

/*
 * We need a small, stripped down image to fit into the first 128k OneNAND
 * erase block (gzipped). This image only needs basic commands for FLASH
 * (NOR/OneNAND) usage and Linux kernel booting.
 */
#if defined(CONFIG_VCT_SMALL_IMAGE)
#undef CONFIG_SMC911X
#undef CONFIG_SYS_I2C_SOFT
#undef CONFIG_SOURCE
#undef CONFIG_SYS_LONGHELP
#undef CONFIG_TIMESTAMP
#endif /* CONFIG_VCT_SMALL_IMAGE */

#endif  /* __CONFIG_H */
Commit	Line	Data
ae691e57 SR	1	/*
	2	* (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
ae691e57 SR	5	*/
	6
	7	/*
	8	* This file contains the configuration parameters for the VCT board
	9	* family:
	10	*
	11	* vct_premium
	12	* vct_premium_small
	13	* vct_premium_onenand
	14	* vct_premium_onenand_small
	15	* vct_platinum
	16	* vct_platinum_small
	17	* vct_platinum_onenand
	18	* vct_platinum_onenand_small
	19	* vct_platinumavc
	20	* vct_platinumavc_small
	21	* vct_platinumavc_onenand
	22	* vct_platinumavc_onenand_small
	23	*/
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
ae691e57 SR	28	#define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */
ae691e57 SR	29	#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
ae691e57 SR	30
	31	#define CONFIG_SKIP_LOWLEVEL_INIT /* SDRAM is initialized by the bootstrap code */
	32
14d0a02a	33	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
ae691e57	34	#define CONFIG_SYS_MONITOR_LEN (256 << 10)
ae691e57 SR	35	#define CONFIG_SYS_MALLOC_LEN (1 << 20)
	36	#define CONFIG_SYS_BOOTPARAMS_LEN (128 << 10)
	37	#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
	38
	39	#if !defined(CONFIG_VCT_NAND) && !defined(CONFIG_VCT_ONENAND)
	40	#define CONFIG_VCT_NOR
ae691e57 SR	41	#endif
	42
	43	/*
	44	* UART
	45	*/
294f10ca DZ	46	#ifdef CONFIG_VCT_PLATINUMAVC
	47	#define UART_1_BASE 0xBDC30000
	48	#else
	49	#define UART_1_BASE 0xBF89C000
	50	#endif
	51
	52	#define CONFIG_SYS_NS16550_SERIAL
294f10ca DZ	53	#define CONFIG_SYS_NS16550_REG_SIZE -4
	54	#define CONFIG_SYS_NS16550_COM1 UART_1_BASE
	55	#define CONFIG_CONS_INDEX 1
	56	#define CONFIG_SYS_NS16550_CLK 921600
ae691e57 SR	57
	58	/*
	59	* SDRAM
	60	*/
	61	#define CONFIG_SYS_SDRAM_BASE 0x80000000
	62	#define CONFIG_SYS_MBYTES_SDRAM 128
	63	#define CONFIG_SYS_MEMTEST_START 0x80200000
	64	#define CONFIG_SYS_MEMTEST_END 0x80400000
	65	#define CONFIG_SYS_LOAD_ADDR 0x80400000 /* default load address */
	66
	67	#if defined(CONFIG_VCT_PREMIUM) \|\| defined(CONFIG_VCT_PLATINUM)
	68	/*
	69	* SMSC91C11x Network Card
	70	*/
736fead8 BW	71	#define CONFIG_SMC911X
	72	#define CONFIG_SMC911X_BASE 0x00000000
	73	#define CONFIG_SMC911X_32_BIT
ae691e57 SR	74	#define CONFIG_NET_RETRY_COUNT 20
	75	#endif
	76
	77	/*
	78	* Commands
	79	*/
ae691e57 SR	80
	81	/*
	82	* Only Premium/Platinum have ethernet support right now
	83	*/
383015b2 DS	84	#if (defined(CONFIG_VCT_PREMIUM) \|\| defined(CONFIG_VCT_PLATINUM)) && \
383015b2 DS	85	!defined(CONFIG_VCT_SMALL_IMAGE)
ae691e57 SR	86	#endif
	87
	88	/*
	89	* Only Premium/Platinum have USB-EHCI support right now
	90	*/
383015b2 DS	91	#if (defined(CONFIG_VCT_PREMIUM) \|\| defined(CONFIG_VCT_PLATINUM)) && \
383015b2 DS	92	!defined(CONFIG_VCT_SMALL_IMAGE)
ae691e57 SR	93	#endif
	94
	95	#if defined(CONFIG_CMD_USB)
ae691e57 SR	96	#define CONFIG_SUPPORT_VFAT
	97
	98	/*
	99	* USB/EHCI
	100	*/
ae691e57	101	#define CONFIG_USB_EHCI_VCT /* on VCT platform */
ae691e57 SR	102	#define CONFIG_EHCI_MMIO_BIG_ENDIAN
	103	#define CONFIG_EHCI_DESC_BIG_ENDIAN
	104	#define CONFIG_EHCI_IS_TDI
	105	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
	106	#endif /* CONFIG_CMD_USB */
	107
ae691e57 SR	108	/*
	109	* BOOTP options
	110	*/
	111	#define CONFIG_BOOTP_BOOTFILESIZE
	112	#define CONFIG_BOOTP_BOOTPATH
	113	#define CONFIG_BOOTP_GATEWAY
	114	#define CONFIG_BOOTP_HOSTNAME
	115	#define CONFIG_BOOTP_SUBNETMASK
	116
	117	/*
	118	* Miscellaneous configurable options
	119	*/
	120	#define CONFIG_SYS_LONGHELP /* undef to save memory */
ae691e57	121	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
ae691e57 SR	122	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	123	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	124	#define CONFIG_CMDLINE_EDITING /* add command line history */
ae691e57 SR	125
	126	/*
	127	* FLASH and environment organization
	128	*/
	129	#if defined(CONFIG_VCT_NOR)
ae691e57 SR	130	#define CONFIG_FLASH_NOT_MEM_MAPPED
	131
	132	/*
	133	* We need special accessor functions for the CFI FLASH driver. This
	134	* can be enabled via the CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS option.
	135	*/
	136	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
	137
	138	/*
	139	* For the non-memory-mapped NOR FLASH, we need to define the
	140	* NOR FLASH area. This can't be detected via the addr2info()
	141	* function, since we check for flash access in the very early
	142	* U-Boot code, before the NOR FLASH is detected.
	143	*/
	144	#define CONFIG_FLASH_BASE 0xb0000000
	145	#define CONFIG_FLASH_END 0xbfffffff
	146
	147	/*
	148	* CFI driver settings
	149	*/
	150	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
	151	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
	152	#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
	153	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
	154
	155	#define CONFIG_SYS_FLASH_BASE 0xb0000000
	156	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	157	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	158	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
	159
	160	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	161	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	162
	163	#ifdef CONFIG_ENV_IS_IN_FLASH
	164	#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
	165	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
	166	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
	167
	168	/* Address and size of Redundant Environment Sector */
	169	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
	170	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
	171	#endif /* CONFIG_ENV_IS_IN_FLASH */
	172	#endif /* CONFIG_VCT_NOR */
	173
	174	#if defined(CONFIG_VCT_ONENAND)
	175	#define CONFIG_USE_ONENAND_BOARD_INIT
ae691e57 SR	176	#define CONFIG_SYS_ONENAND_BASE 0x00000000 /* this is not real address */
	177	#define CONFIG_SYS_FLASH_BASE 0x00000000
	178	#define CONFIG_ENV_ADDR (128 << 10) /* after compr. U-Boot image */
	179	#define CONFIG_ENV_SIZE (128 << 10) /* erase size */
	180	#endif /* CONFIG_VCT_ONENAND */
	181
ae691e57 SR	182	/*
	183	* I2C/EEPROM
	184	*/
ea818dbb HS	185	#define CONFIG_SYS_I2C
	186	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
	187	#define CONFIG_SYS_I2C_SOFT_SPEED 83000 /* 83 kHz is supposed to work */
	188	#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7f
ae691e57 SR	189
	190	/*
	191	* Software (bit-bang) I2C driver configuration
	192	*/
	193	#define CONFIG_SYS_GPIO_I2C_SCL 11
	194	#define CONFIG_SYS_GPIO_I2C_SDA 10
	195
	196	#ifndef __ASSEMBLY__
	197	int vct_gpio_dir(int pin, int dir);
	198	void vct_gpio_set(int pin, int val);
	199	int vct_gpio_get(int pin);
	200	#endif
	201
	202	#define I2C_INIT vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SCL, 1)
	203	#define I2C_ACTIVE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 1)
	204	#define I2C_TRISTATE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 0)
	205	#define I2C_READ vct_gpio_get(CONFIG_SYS_GPIO_I2C_SDA)
	206	#define I2C_SDA(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SDA, bit)
	207	#define I2C_SCL(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SCL, bit)
	208	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
	209
	210	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	211	/* CAT24WC32 */
	212	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
	213	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
	214	/* 32 byte page write mode using*/
	215	/* last 5 bits of the address */
	216	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
	217
	218	#define CONFIG_BOOTCOMMAND "run test3"
ae691e57	219
ae691e57 SR	220	/*
	221	* UBI configuration
	222	*/
	223	#if defined(CONFIG_VCT_ONENAND)
942556a9	224	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
ae691e57	225	#define CONFIG_MTD_PARTITIONS
ae691e57 SR	226
	227	#define MTDIDS_DEFAULT "onenand0=onenand"
	228	#define MTDPARTS_DEFAULT "mtdparts=onenand:128k(u-boot)," \
	229	"128k(env)," \
	230	"20m(kernel)," \
	231	"-(rootfs)"
	232	#endif
	233
	234	/*
	235	* We need a small, stripped down image to fit into the first 128k OneNAND
	236	* erase block (gzipped). This image only needs basic commands for FLASH
	237	* (NOR/OneNAND) usage and Linux kernel booting.
	238	*/
	239	#if defined(CONFIG_VCT_SMALL_IMAGE)
736fead8	240	#undef CONFIG_SMC911X
ea818dbb	241	#undef CONFIG_SYS_I2C_SOFT
74de7aef	242	#undef CONFIG_SOURCE
ae691e57 SR	243	#undef CONFIG_SYS_LONGHELP
	244	#undef CONFIG_TIMESTAMP
	245	#endif /* CONFIG_VCT_SMALL_IMAGE */
	246
	247	#endif /* __CONFIG_H */