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ae691e57 SR |
1 | /* |
2 | * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
ae691e57 SR |
5 | */ |
6 | ||
7 | /* | |
8 | * This file contains the configuration parameters for the VCT board | |
9 | * family: | |
10 | * | |
11 | * vct_premium | |
12 | * vct_premium_small | |
13 | * vct_premium_onenand | |
14 | * vct_premium_onenand_small | |
15 | * vct_platinum | |
16 | * vct_platinum_small | |
17 | * vct_platinum_onenand | |
18 | * vct_platinum_onenand_small | |
19 | * vct_platinumavc | |
20 | * vct_platinumavc_small | |
21 | * vct_platinumavc_onenand | |
22 | * vct_platinumavc_onenand_small | |
23 | */ | |
24 | ||
25 | #ifndef __CONFIG_H | |
26 | #define __CONFIG_H | |
27 | ||
ae691e57 SR |
28 | #define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */ |
29 | #define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2) | |
ae691e57 SR |
30 | |
31 | #define CONFIG_SKIP_LOWLEVEL_INIT /* SDRAM is initialized by the bootstrap code */ | |
32 | ||
14d0a02a | 33 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
ae691e57 | 34 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) |
ae691e57 SR |
35 | #define CONFIG_SYS_MALLOC_LEN (1 << 20) |
36 | #define CONFIG_SYS_BOOTPARAMS_LEN (128 << 10) | |
37 | #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 | |
38 | ||
39 | #if !defined(CONFIG_VCT_NAND) && !defined(CONFIG_VCT_ONENAND) | |
40 | #define CONFIG_VCT_NOR | |
ae691e57 SR |
41 | #endif |
42 | ||
43 | /* | |
44 | * UART | |
45 | */ | |
294f10ca DZ |
46 | #ifdef CONFIG_VCT_PLATINUMAVC |
47 | #define UART_1_BASE 0xBDC30000 | |
48 | #else | |
49 | #define UART_1_BASE 0xBF89C000 | |
50 | #endif | |
51 | ||
52 | #define CONFIG_SYS_NS16550_SERIAL | |
294f10ca DZ |
53 | #define CONFIG_SYS_NS16550_REG_SIZE -4 |
54 | #define CONFIG_SYS_NS16550_COM1 UART_1_BASE | |
55 | #define CONFIG_CONS_INDEX 1 | |
56 | #define CONFIG_SYS_NS16550_CLK 921600 | |
ae691e57 SR |
57 | |
58 | /* | |
59 | * SDRAM | |
60 | */ | |
61 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 | |
62 | #define CONFIG_SYS_MBYTES_SDRAM 128 | |
63 | #define CONFIG_SYS_MEMTEST_START 0x80200000 | |
64 | #define CONFIG_SYS_MEMTEST_END 0x80400000 | |
65 | #define CONFIG_SYS_LOAD_ADDR 0x80400000 /* default load address */ | |
66 | ||
67 | #if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM) | |
ae691e57 SR |
68 | #define CONFIG_NET_RETRY_COUNT 20 |
69 | #endif | |
70 | ||
71 | /* | |
72 | * Commands | |
73 | */ | |
ae691e57 | 74 | #if defined(CONFIG_CMD_USB) |
ae691e57 SR |
75 | |
76 | /* | |
77 | * USB/EHCI | |
78 | */ | |
ae691e57 | 79 | #define CONFIG_USB_EHCI_VCT /* on VCT platform */ |
ae691e57 SR |
80 | #define CONFIG_EHCI_MMIO_BIG_ENDIAN |
81 | #define CONFIG_EHCI_DESC_BIG_ENDIAN | |
82 | #define CONFIG_EHCI_IS_TDI | |
83 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */ | |
84 | #endif /* CONFIG_CMD_USB */ | |
85 | ||
ae691e57 SR |
86 | /* |
87 | * BOOTP options | |
88 | */ | |
89 | #define CONFIG_BOOTP_BOOTFILESIZE | |
90 | #define CONFIG_BOOTP_BOOTPATH | |
91 | #define CONFIG_BOOTP_GATEWAY | |
92 | #define CONFIG_BOOTP_HOSTNAME | |
93 | #define CONFIG_BOOTP_SUBNETMASK | |
94 | ||
95 | /* | |
96 | * Miscellaneous configurable options | |
97 | */ | |
98 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
ae691e57 | 99 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
ae691e57 SR |
100 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
101 | #define CONFIG_CMDLINE_EDITING /* add command line history */ | |
ae691e57 SR |
102 | |
103 | /* | |
104 | * FLASH and environment organization | |
105 | */ | |
106 | #if defined(CONFIG_VCT_NOR) | |
ae691e57 SR |
107 | #define CONFIG_FLASH_NOT_MEM_MAPPED |
108 | ||
109 | /* | |
110 | * We need special accessor functions for the CFI FLASH driver. This | |
111 | * can be enabled via the CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS option. | |
112 | */ | |
113 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS | |
114 | ||
115 | /* | |
116 | * For the non-memory-mapped NOR FLASH, we need to define the | |
117 | * NOR FLASH area. This can't be detected via the addr2info() | |
118 | * function, since we check for flash access in the very early | |
119 | * U-Boot code, before the NOR FLASH is detected. | |
120 | */ | |
121 | #define CONFIG_FLASH_BASE 0xb0000000 | |
122 | #define CONFIG_FLASH_END 0xbfffffff | |
123 | ||
124 | /* | |
125 | * CFI driver settings | |
126 | */ | |
127 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ | |
128 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ | |
129 | #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */ | |
130 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ | |
131 | ||
132 | #define CONFIG_SYS_FLASH_BASE 0xb0000000 | |
133 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
134 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
135 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
136 | ||
137 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
138 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
139 | ||
140 | #ifdef CONFIG_ENV_IS_IN_FLASH | |
141 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ | |
142 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) | |
143 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
144 | ||
145 | /* Address and size of Redundant Environment Sector */ | |
146 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) | |
147 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
148 | #endif /* CONFIG_ENV_IS_IN_FLASH */ | |
149 | #endif /* CONFIG_VCT_NOR */ | |
150 | ||
151 | #if defined(CONFIG_VCT_ONENAND) | |
152 | #define CONFIG_USE_ONENAND_BOARD_INIT | |
ae691e57 SR |
153 | #define CONFIG_SYS_ONENAND_BASE 0x00000000 /* this is not real address */ |
154 | #define CONFIG_SYS_FLASH_BASE 0x00000000 | |
155 | #define CONFIG_ENV_ADDR (128 << 10) /* after compr. U-Boot image */ | |
156 | #define CONFIG_ENV_SIZE (128 << 10) /* erase size */ | |
157 | #endif /* CONFIG_VCT_ONENAND */ | |
158 | ||
ae691e57 SR |
159 | /* |
160 | * I2C/EEPROM | |
161 | */ | |
ea818dbb HS |
162 | #define CONFIG_SYS_I2C |
163 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ | |
164 | #define CONFIG_SYS_I2C_SOFT_SPEED 83000 /* 83 kHz is supposed to work */ | |
165 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7f | |
ae691e57 SR |
166 | |
167 | /* | |
168 | * Software (bit-bang) I2C driver configuration | |
169 | */ | |
170 | #define CONFIG_SYS_GPIO_I2C_SCL 11 | |
171 | #define CONFIG_SYS_GPIO_I2C_SDA 10 | |
172 | ||
173 | #ifndef __ASSEMBLY__ | |
174 | int vct_gpio_dir(int pin, int dir); | |
175 | void vct_gpio_set(int pin, int val); | |
176 | int vct_gpio_get(int pin); | |
177 | #endif | |
178 | ||
179 | #define I2C_INIT vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SCL, 1) | |
180 | #define I2C_ACTIVE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 1) | |
181 | #define I2C_TRISTATE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 0) | |
182 | #define I2C_READ vct_gpio_get(CONFIG_SYS_GPIO_I2C_SDA) | |
183 | #define I2C_SDA(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SDA, bit) | |
184 | #define I2C_SCL(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SCL, bit) | |
185 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
186 | ||
187 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
188 | /* CAT24WC32 */ | |
189 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ | |
190 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ | |
191 | /* 32 byte page write mode using*/ | |
192 | /* last 5 bits of the address */ | |
193 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
194 | ||
195 | #define CONFIG_BOOTCOMMAND "run test3" | |
ae691e57 | 196 | |
ae691e57 SR |
197 | /* |
198 | * UBI configuration | |
199 | */ | |
200 | #if defined(CONFIG_VCT_ONENAND) | |
942556a9 | 201 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
ae691e57 | 202 | #define CONFIG_MTD_PARTITIONS |
ae691e57 SR |
203 | #endif |
204 | ||
205 | /* | |
206 | * We need a small, stripped down image to fit into the first 128k OneNAND | |
207 | * erase block (gzipped). This image only needs basic commands for FLASH | |
208 | * (NOR/OneNAND) usage and Linux kernel booting. | |
209 | */ | |
210 | #if defined(CONFIG_VCT_SMALL_IMAGE) | |
ea818dbb | 211 | #undef CONFIG_SYS_I2C_SOFT |
74de7aef | 212 | #undef CONFIG_SOURCE |
ae691e57 SR |
213 | #undef CONFIG_SYS_LONGHELP |
214 | #undef CONFIG_TIMESTAMP | |
215 | #endif /* CONFIG_VCT_SMALL_IMAGE */ | |
216 | ||
217 | #endif /* __CONFIG_H */ |