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Commit | Line | Data |
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4e43b2e8 HS |
1 | /* |
2 | * Copyright (C) Freescale Semiconductor, Inc. 2006. | |
3 | * | |
4 | * (C) Copyright 2010 | |
5 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
4e43b2e8 HS |
8 | */ |
9 | /* | |
10 | * ve8313 board configuration file | |
11 | */ | |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
16 | /* | |
17 | * High Level Configuration Options | |
18 | */ | |
19 | #define CONFIG_E300 1 | |
4e43b2e8 HS |
20 | #define CONFIG_MPC831x 1 |
21 | #define CONFIG_MPC8313 1 | |
22 | #define CONFIG_VE8313 1 | |
23 | ||
2ae18241 WD |
24 | #ifndef CONFIG_SYS_TEXT_BASE |
25 | #define CONFIG_SYS_TEXT_BASE 0xfe000000 | |
26 | #endif | |
27 | ||
842033e6 | 28 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 |
a2243b84 | 29 | #define CONFIG_FSL_ELBC 1 |
4e43b2e8 | 30 | |
4e43b2e8 HS |
31 | /* |
32 | * On-board devices | |
33 | * | |
34 | */ | |
35 | #define CONFIG_83XX_CLKIN 32000000 /* in Hz */ | |
36 | ||
37 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
38 | ||
39 | #define CONFIG_SYS_IMMR 0xE0000000 | |
40 | ||
41 | #define CONFIG_SYS_MEMTEST_START 0x00001000 | |
42 | #define CONFIG_SYS_MEMTEST_END 0x07000000 | |
43 | ||
44 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */ | |
45 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */ | |
46 | ||
47 | /* | |
48 | * Device configurations | |
49 | */ | |
50 | ||
51 | /* | |
52 | * DDR Setup | |
53 | */ | |
be29fa71 | 54 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
4e43b2e8 HS |
55 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE |
56 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
57 | ||
58 | /* | |
59 | * Manually set up DDR parameters, as this board does not | |
60 | * have the SPD connected to I2C. | |
61 | */ | |
be29fa71 | 62 | #define CONFIG_SYS_DDR_SIZE 128 /* MB */ |
2e651b24 | 63 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
4e43b2e8 | 64 | | CSCONFIG_AP \ |
2fef4020 JH |
65 | | CSCONFIG_ODT_RD_NEVER \ |
66 | | CSCONFIG_ODT_WR_ALL \ | |
be29fa71 JH |
67 | | CSCONFIG_ROW_BIT_13 \ |
68 | | CSCONFIG_COL_BIT_10) | |
4e43b2e8 HS |
69 | /* 0x80840102 */ |
70 | ||
71 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
be29fa71 JH |
72 | #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ |
73 | | (0 << TIMING_CFG0_WRT_SHIFT) \ | |
74 | | (3 << TIMING_CFG0_RRT_SHIFT) \ | |
75 | | (2 << TIMING_CFG0_WWT_SHIFT) \ | |
76 | | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ | |
77 | | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ | |
78 | | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | |
79 | | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) | |
4e43b2e8 | 80 | /* 0x0e720802 */ |
be29fa71 JH |
81 | #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ |
82 | | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ | |
83 | | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ | |
84 | | (5 << TIMING_CFG1_CASLAT_SHIFT) \ | |
85 | | (6 << TIMING_CFG1_REFREC_SHIFT) \ | |
86 | | (2 << TIMING_CFG1_WRREC_SHIFT) \ | |
87 | | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | |
88 | | (2 << TIMING_CFG1_WRTORD_SHIFT)) | |
4e43b2e8 | 89 | /* 0x26256222 */ |
be29fa71 JH |
90 | #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ |
91 | | (5 << TIMING_CFG2_CPO_SHIFT) \ | |
92 | | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | |
93 | | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ | |
94 | | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ | |
95 | | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ | |
96 | | (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) | |
4e43b2e8 | 97 | /* 0x029028c7 */ |
be29fa71 JH |
98 | #define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \ |
99 | | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) | |
4e43b2e8 | 100 | /* 0x03202000 */ |
be29fa71 | 101 | #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ |
4e43b2e8 | 102 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
2fef4020 | 103 | | SDRAM_CFG_DBW_32) |
4e43b2e8 | 104 | /* 0x43080000 */ |
be29fa71 JH |
105 | #define CONFIG_SYS_SDRAM_CFG2 0x00401000 |
106 | #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \ | |
107 | | (0x0232 << SDRAM_MODE_SD_SHIFT)) | |
4e43b2e8 | 108 | /* 0x44400232 */ |
be29fa71 | 109 | #define CONFIG_SYS_DDR_MODE_2 0x8000C000 |
4e43b2e8 HS |
110 | |
111 | #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 | |
112 | /*0x02000000*/ | |
be29fa71 | 113 | #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ |
4e43b2e8 HS |
114 | | DDRCDR_PZ_NOMZ \ |
115 | | DDRCDR_NZ_NOMZ \ | |
be29fa71 | 116 | | DDRCDR_M_ODR) |
4e43b2e8 HS |
117 | /* 0x73000002 */ |
118 | ||
119 | /* | |
120 | * FLASH on the Local Bus | |
121 | */ | |
122 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ | |
123 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
124 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 | |
125 | #define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */ | |
126 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ | |
127 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ | |
128 | ||
be29fa71 | 129 | #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ |
7d6a0982 JH |
130 | | BR_PS_16 /* 16 bit */ \ |
131 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
132 | | BR_V) /* valid */ | |
4e43b2e8 | 133 | #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ |
be29fa71 JH |
134 | | OR_GPCM_CSNT \ |
135 | | OR_GPCM_ACS_DIV4 \ | |
136 | | OR_GPCM_SCY_5 \ | |
7d6a0982 | 137 | | OR_GPCM_TRLX_SET \ |
be29fa71 JH |
138 | | OR_GPCM_EAD) |
139 | /* 0xfe000c55 */ | |
4e43b2e8 HS |
140 | |
141 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
7d6a0982 | 142 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) |
4e43b2e8 HS |
143 | |
144 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
145 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */ | |
146 | ||
147 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
148 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
149 | ||
14d0a02a | 150 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
4e43b2e8 HS |
151 | |
152 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) | |
153 | #define CONFIG_SYS_RAMBOOT | |
154 | #endif | |
155 | ||
156 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
157 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ | |
be29fa71 | 158 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ |
4e43b2e8 | 159 | |
be29fa71 JH |
160 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
161 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
4e43b2e8 HS |
162 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
163 | ||
164 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ | |
165 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) | |
166 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) | |
167 | ||
168 | /* | |
169 | * Local Bus LCRR and LBCR regs | |
170 | */ | |
171 | #define CONFIG_SYS_LCRR_EADC LCRR_EADC_3 | |
172 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 | |
173 | ||
174 | #define CONFIG_SYS_LBC_LBCR 0x00040000 | |
175 | ||
176 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 | |
177 | ||
178 | /* | |
179 | * NAND settings | |
180 | */ | |
181 | #define CONFIG_SYS_NAND_BASE 0x61000000 | |
182 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
4e43b2e8 HS |
183 | #define CONFIG_CMD_NAND 1 |
184 | #define CONFIG_NAND_FSL_ELBC 1 | |
185 | #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 | |
186 | ||
be29fa71 JH |
187 | #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ |
188 | | BR_PS_8 \ | |
189 | | BR_DECC_CHK_GEN \ | |
190 | | BR_MS_FCM \ | |
191 | | BR_V) /* valid */ | |
192 | /* 0x61000c21 */ | |
7d6a0982 | 193 | #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ |
be29fa71 JH |
194 | | OR_FCM_BCTLD \ |
195 | | OR_FCM_CHT \ | |
196 | | OR_FCM_SCY_2 \ | |
197 | | OR_FCM_RST \ | |
198 | | OR_FCM_TRLX) | |
199 | /* 0xffff90ac */ | |
4e43b2e8 HS |
200 | |
201 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM | |
202 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM | |
203 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM | |
204 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM | |
205 | ||
206 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE | |
7d6a0982 | 207 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
4e43b2e8 HS |
208 | |
209 | #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM | |
210 | #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM | |
211 | ||
212 | /* CS2 NvRAM */ | |
be29fa71 JH |
213 | #define CONFIG_SYS_BR2_PRELIM (0x60000000 \ |
214 | | BR_PS_8 \ | |
4e43b2e8 HS |
215 | | BR_V) |
216 | /* 0x60000801 */ | |
7d6a0982 | 217 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ |
be29fa71 JH |
218 | | OR_GPCM_CSNT \ |
219 | | OR_GPCM_XACS \ | |
4e43b2e8 | 220 | | OR_GPCM_SCY_3 \ |
7d6a0982 JH |
221 | | OR_GPCM_TRLX_SET \ |
222 | | OR_GPCM_EHTR_SET \ | |
4e43b2e8 HS |
223 | | OR_GPCM_EAD) |
224 | /* 0xfffe0937 */ | |
225 | /* local bus read write buffer mapping SRAM@0x64000000 */ | |
be29fa71 JH |
226 | #define CONFIG_SYS_BR3_PRELIM (0x62000000 \ |
227 | | BR_PS_16 \ | |
4e43b2e8 HS |
228 | | BR_V) |
229 | /* 0x62001001 */ | |
230 | ||
7d6a0982 | 231 | #define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB \ |
be29fa71 JH |
232 | | OR_GPCM_CSNT \ |
233 | | OR_GPCM_XACS \ | |
4e43b2e8 | 234 | | OR_GPCM_SCY_15 \ |
7d6a0982 JH |
235 | | OR_GPCM_TRLX_SET \ |
236 | | OR_GPCM_EHTR_SET \ | |
4e43b2e8 HS |
237 | | OR_GPCM_EAD) |
238 | /* 0xfe0009f7 */ | |
239 | ||
4e43b2e8 HS |
240 | /* |
241 | * Serial Port | |
242 | */ | |
243 | #define CONFIG_CONS_INDEX 1 | |
4e43b2e8 HS |
244 | #define CONFIG_SYS_NS16550_SERIAL |
245 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
246 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
247 | ||
248 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
249 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} | |
250 | ||
251 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) | |
252 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
253 | ||
4e43b2e8 HS |
254 | #if defined(CONFIG_PCI) |
255 | /* | |
256 | * General PCI | |
257 | * Addresses are mapped 1-1. | |
258 | */ | |
259 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 | |
260 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
261 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
262 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
263 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
264 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
be29fa71 JH |
265 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 |
266 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
267 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
4e43b2e8 | 268 | |
4e43b2e8 HS |
269 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
270 | #endif | |
271 | ||
272 | /* | |
273 | * TSEC | |
274 | */ | |
275 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
276 | ||
4e43b2e8 HS |
277 | #define CONFIG_TSEC1 |
278 | #ifdef CONFIG_TSEC1 | |
279 | #define CONFIG_HAS_ETH0 | |
280 | #define CONFIG_TSEC1_NAME "TSEC1" | |
281 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 | |
282 | #define TSEC1_PHY_ADDR 0x01 | |
283 | #define TSEC1_FLAGS 0 | |
284 | #define TSEC1_PHYIDX 0 | |
285 | #endif | |
286 | ||
287 | /* Options are: TSEC[0-1] */ | |
288 | #define CONFIG_ETHPRIME "TSEC1" | |
289 | ||
290 | /* | |
291 | * Environment | |
292 | */ | |
293 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
be29fa71 JH |
294 | #define CONFIG_ENV_ADDR \ |
295 | (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) | |
4e43b2e8 HS |
296 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
297 | #define CONFIG_ENV_SIZE 0x4000 | |
298 | /* Address and size of Redundant Environment Sector */ | |
be29fa71 JH |
299 | #define CONFIG_ENV_OFFSET_REDUND \ |
300 | (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) | |
4e43b2e8 HS |
301 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
302 | ||
303 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
304 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
305 | ||
306 | /* | |
307 | * BOOTP options | |
308 | */ | |
309 | #define CONFIG_BOOTP_BOOTFILESIZE | |
310 | #define CONFIG_BOOTP_BOOTPATH | |
311 | #define CONFIG_BOOTP_GATEWAY | |
312 | #define CONFIG_BOOTP_HOSTNAME | |
313 | ||
314 | /* | |
315 | * Command line configuration. | |
316 | */ | |
4e43b2e8 HS |
317 | #define CONFIG_CMD_PCI |
318 | ||
319 | #define CONFIG_CMDLINE_EDITING 1 | |
320 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
321 | ||
322 | /* | |
323 | * Miscellaneous configurable options | |
324 | */ | |
325 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
326 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ | |
4e43b2e8 HS |
327 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
328 | ||
329 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
330 | #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ | |
331 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */ | |
4e43b2e8 HS |
332 | |
333 | /* | |
334 | * For booting Linux, the board info and command line data | |
9f530d59 | 335 | * have to be in the first 256 MB of memory, since this is |
4e43b2e8 HS |
336 | * the maximum mapped by the Linux kernel during initialization. |
337 | */ | |
be29fa71 JH |
338 | /* Initial Memory map for Linux*/ |
339 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
4e43b2e8 HS |
340 | |
341 | /* 0x64050000 */ | |
342 | #define CONFIG_SYS_HRCW_LOW (\ | |
343 | 0x20000000 /* reserved, must be set */ |\ | |
344 | HRCWL_DDRCM |\ | |
345 | HRCWL_CSB_TO_CLKIN_4X1 | \ | |
346 | HRCWL_CORE_TO_CSB_2_5X1) | |
347 | ||
348 | /* 0xa0600004 */ | |
349 | #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \ | |
350 | HRCWH_PCI_ARBITER_ENABLE | \ | |
351 | HRCWH_CORE_ENABLE | \ | |
352 | HRCWH_FROM_0X00000100 | \ | |
353 | HRCWH_BOOTSEQ_DISABLE |\ | |
354 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
355 | HRCWH_ROM_LOC_LOCAL_16BIT | \ | |
356 | HRCWH_TSEC1M_IN_MII | \ | |
357 | HRCWH_BIG_ENDIAN | \ | |
358 | HRCWH_LALE_EARLY) | |
359 | ||
360 | /* System IO Config */ | |
361 | #define CONFIG_SYS_SICRH (0x01000000 | \ | |
362 | SICRH_ETSEC2_B | \ | |
363 | SICRH_ETSEC2_C | \ | |
364 | SICRH_ETSEC2_D | \ | |
365 | SICRH_ETSEC2_E | \ | |
366 | SICRH_ETSEC2_F | \ | |
367 | SICRH_ETSEC2_G | \ | |
368 | SICRH_TSOBI1 | \ | |
369 | SICRH_TSOBI2) | |
370 | /* 0x010fff03 */ | |
371 | #define CONFIG_SYS_SICRL (SICRL_LBC | \ | |
372 | SICRL_SPI_A | \ | |
373 | SICRL_SPI_B | \ | |
374 | SICRL_SPI_C | \ | |
375 | SICRL_SPI_D | \ | |
376 | SICRL_ETSEC2_A) | |
377 | /* 0x33fc0003) */ | |
378 | ||
379 | #define CONFIG_SYS_HID0_INIT 0x000000000 | |
380 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
381 | HID0_ENABLE_INSTRUCTION_CACHE) | |
382 | ||
383 | #define CONFIG_SYS_HID2 HID2_HBE | |
384 | ||
385 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ | |
386 | ||
387 | /* DDR @ 0x00000000 */ | |
72cd4087 | 388 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) |
be29fa71 JH |
389 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ |
390 | | BATU_BL_256M \ | |
391 | | BATU_VS \ | |
392 | | BATU_VP) | |
4e43b2e8 HS |
393 | |
394 | #if defined(CONFIG_PCI) | |
395 | /* PCI @ 0x80000000 */ | |
72cd4087 | 396 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) |
be29fa71 JH |
397 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ |
398 | | BATU_BL_256M \ | |
399 | | BATU_VS \ | |
400 | | BATU_VP) | |
401 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ | |
72cd4087 | 402 | | BATL_PP_RW \ |
be29fa71 JH |
403 | | BATL_CACHEINHIBIT \ |
404 | | BATL_GUARDEDSTORAGE) | |
405 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ | |
406 | | BATU_BL_256M \ | |
407 | | BATU_VS \ | |
408 | | BATU_VP) | |
4e43b2e8 HS |
409 | #else |
410 | #define CONFIG_SYS_IBAT1L (0) | |
411 | #define CONFIG_SYS_IBAT1U (0) | |
412 | #define CONFIG_SYS_IBAT2L (0) | |
413 | #define CONFIG_SYS_IBAT2U (0) | |
414 | #endif | |
415 | ||
416 | /* PCI2 not supported on 8313 */ | |
417 | #define CONFIG_SYS_IBAT3L (0) | |
418 | #define CONFIG_SYS_IBAT3U (0) | |
419 | #define CONFIG_SYS_IBAT4L (0) | |
420 | #define CONFIG_SYS_IBAT4U (0) | |
421 | ||
422 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ | |
be29fa71 | 423 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ |
72cd4087 | 424 | | BATL_PP_RW \ |
be29fa71 JH |
425 | | BATL_CACHEINHIBIT \ |
426 | | BATL_GUARDEDSTORAGE) | |
427 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ | |
428 | | BATU_BL_256M \ | |
429 | | BATU_VS \ | |
430 | | BATU_VP) | |
4e43b2e8 HS |
431 | |
432 | /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ | |
72cd4087 | 433 | #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) |
4e43b2e8 HS |
434 | #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
435 | ||
436 | /* FPGA, SRAM, NAND @ 0x60000000 */ | |
72cd4087 | 437 | #define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) |
4e43b2e8 HS |
438 | #define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
439 | ||
440 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
441 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
442 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
443 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
444 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
445 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
446 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
447 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
448 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
449 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
450 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
451 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
452 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
453 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
454 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
455 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
456 | ||
4e43b2e8 HS |
457 | #define CONFIG_NETDEV eth0 |
458 | ||
459 | #define CONFIG_HOSTNAME ve8313 | |
460 | #define CONFIG_UBOOTPATH ve8313/u-boot.bin | |
461 | ||
4e43b2e8 HS |
462 | #define CONFIG_BAUDRATE 115200 |
463 | ||
4e43b2e8 | 464 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
5368c55d MV |
465 | "netdev=" __stringify(CONFIG_NETDEV) "\0" \ |
466 | "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \ | |
467 | "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
4e43b2e8 HS |
468 | "u-boot_addr_r=100000\0" \ |
469 | "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ | |
5368c55d MV |
470 | "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ |
471 | " +${filesize};" \ | |
472 | "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \ | |
473 | "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \ | |
be29fa71 | 474 | " ${filesize};" \ |
5368c55d | 475 | "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \ |
4e43b2e8 HS |
476 | |
477 | #endif /* __CONFIG_H */ |