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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
4e43b2e8 HS |
2 | /* |
3 | * Copyright (C) Freescale Semiconductor, Inc. 2006. | |
4 | * | |
5 | * (C) Copyright 2010 | |
6 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
4e43b2e8 HS |
7 | */ |
8 | /* | |
9 | * ve8313 board configuration file | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | */ | |
18 | #define CONFIG_E300 1 | |
4e43b2e8 | 19 | |
842033e6 | 20 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 |
a2243b84 | 21 | #define CONFIG_FSL_ELBC 1 |
4e43b2e8 | 22 | |
4e43b2e8 HS |
23 | /* |
24 | * On-board devices | |
25 | * | |
26 | */ | |
4e43b2e8 HS |
27 | #define CONFIG_SYS_MEMTEST_START 0x00001000 |
28 | #define CONFIG_SYS_MEMTEST_END 0x07000000 | |
29 | ||
4e43b2e8 HS |
30 | /* |
31 | * Device configurations | |
32 | */ | |
33 | ||
34 | /* | |
35 | * DDR Setup | |
36 | */ | |
8a81bfd2 | 37 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
4e43b2e8 HS |
38 | |
39 | /* | |
40 | * Manually set up DDR parameters, as this board does not | |
41 | * have the SPD connected to I2C. | |
42 | */ | |
be29fa71 | 43 | #define CONFIG_SYS_DDR_SIZE 128 /* MB */ |
2e651b24 | 44 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
4e43b2e8 | 45 | | CSCONFIG_AP \ |
2fef4020 JH |
46 | | CSCONFIG_ODT_RD_NEVER \ |
47 | | CSCONFIG_ODT_WR_ALL \ | |
be29fa71 JH |
48 | | CSCONFIG_ROW_BIT_13 \ |
49 | | CSCONFIG_COL_BIT_10) | |
4e43b2e8 HS |
50 | /* 0x80840102 */ |
51 | ||
52 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
be29fa71 JH |
53 | #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ |
54 | | (0 << TIMING_CFG0_WRT_SHIFT) \ | |
55 | | (3 << TIMING_CFG0_RRT_SHIFT) \ | |
56 | | (2 << TIMING_CFG0_WWT_SHIFT) \ | |
57 | | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ | |
58 | | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ | |
59 | | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | |
60 | | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) | |
4e43b2e8 | 61 | /* 0x0e720802 */ |
be29fa71 JH |
62 | #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ |
63 | | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ | |
64 | | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ | |
65 | | (5 << TIMING_CFG1_CASLAT_SHIFT) \ | |
66 | | (6 << TIMING_CFG1_REFREC_SHIFT) \ | |
67 | | (2 << TIMING_CFG1_WRREC_SHIFT) \ | |
68 | | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | |
69 | | (2 << TIMING_CFG1_WRTORD_SHIFT)) | |
4e43b2e8 | 70 | /* 0x26256222 */ |
be29fa71 JH |
71 | #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ |
72 | | (5 << TIMING_CFG2_CPO_SHIFT) \ | |
73 | | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | |
74 | | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ | |
75 | | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ | |
76 | | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ | |
77 | | (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) | |
4e43b2e8 | 78 | /* 0x029028c7 */ |
be29fa71 JH |
79 | #define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \ |
80 | | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) | |
4e43b2e8 | 81 | /* 0x03202000 */ |
be29fa71 | 82 | #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ |
4e43b2e8 | 83 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
2fef4020 | 84 | | SDRAM_CFG_DBW_32) |
4e43b2e8 | 85 | /* 0x43080000 */ |
be29fa71 JH |
86 | #define CONFIG_SYS_SDRAM_CFG2 0x00401000 |
87 | #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \ | |
88 | | (0x0232 << SDRAM_MODE_SD_SHIFT)) | |
4e43b2e8 | 89 | /* 0x44400232 */ |
be29fa71 | 90 | #define CONFIG_SYS_DDR_MODE_2 0x8000C000 |
4e43b2e8 HS |
91 | |
92 | #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 | |
93 | /*0x02000000*/ | |
be29fa71 | 94 | #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ |
4e43b2e8 HS |
95 | | DDRCDR_PZ_NOMZ \ |
96 | | DDRCDR_NZ_NOMZ \ | |
be29fa71 | 97 | | DDRCDR_M_ODR) |
4e43b2e8 HS |
98 | /* 0x73000002 */ |
99 | ||
100 | /* | |
101 | * FLASH on the Local Bus | |
102 | */ | |
4e43b2e8 HS |
103 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 |
104 | #define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */ | |
105 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ | |
4e43b2e8 | 106 | |
4e43b2e8 HS |
107 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
108 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */ | |
109 | ||
110 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
111 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
112 | ||
14d0a02a | 113 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
4e43b2e8 HS |
114 | |
115 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) | |
116 | #define CONFIG_SYS_RAMBOOT | |
117 | #endif | |
118 | ||
119 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
120 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ | |
be29fa71 | 121 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ |
4e43b2e8 | 122 | |
be29fa71 JH |
123 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
124 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
4e43b2e8 HS |
125 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
126 | ||
127 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ | |
128 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) | |
129 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) | |
130 | ||
4e43b2e8 HS |
131 | /* |
132 | * NAND settings | |
133 | */ | |
134 | #define CONFIG_SYS_NAND_BASE 0x61000000 | |
135 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
4e43b2e8 HS |
136 | #define CONFIG_NAND_FSL_ELBC 1 |
137 | #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 | |
138 | ||
1e35d425 | 139 | |
4e43b2e8 | 140 | |
1e35d425 MS |
141 | /* Still needed for spl_minimal.c */ |
142 | #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM | |
143 | #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM | |
4e43b2e8 | 144 | |
a8f97539 | 145 | |
4e43b2e8 | 146 | |
4e43b2e8 HS |
147 | /* |
148 | * Serial Port | |
149 | */ | |
4e43b2e8 HS |
150 | #define CONFIG_SYS_NS16550_SERIAL |
151 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
152 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
153 | ||
154 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
155 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} | |
156 | ||
157 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) | |
158 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
159 | ||
4e43b2e8 HS |
160 | #if defined(CONFIG_PCI) |
161 | /* | |
162 | * General PCI | |
163 | * Addresses are mapped 1-1. | |
164 | */ | |
165 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 | |
166 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
167 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
168 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
169 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
170 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
be29fa71 JH |
171 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 |
172 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
173 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
4e43b2e8 | 174 | |
4e43b2e8 HS |
175 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
176 | #endif | |
177 | ||
178 | /* | |
179 | * TSEC | |
180 | */ | |
4e43b2e8 | 181 | |
4e43b2e8 HS |
182 | #define CONFIG_TSEC1 |
183 | #ifdef CONFIG_TSEC1 | |
184 | #define CONFIG_HAS_ETH0 | |
185 | #define CONFIG_TSEC1_NAME "TSEC1" | |
186 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 | |
187 | #define TSEC1_PHY_ADDR 0x01 | |
188 | #define TSEC1_FLAGS 0 | |
189 | #define TSEC1_PHYIDX 0 | |
190 | #endif | |
191 | ||
192 | /* Options are: TSEC[0-1] */ | |
193 | #define CONFIG_ETHPRIME "TSEC1" | |
194 | ||
195 | /* | |
196 | * Environment | |
197 | */ | |
4e43b2e8 | 198 | /* Address and size of Redundant Environment Sector */ |
4e43b2e8 HS |
199 | |
200 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
201 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
202 | ||
203 | /* | |
204 | * BOOTP options | |
205 | */ | |
206 | #define CONFIG_BOOTP_BOOTFILESIZE | |
4e43b2e8 HS |
207 | |
208 | /* | |
209 | * Command line configuration. | |
210 | */ | |
4e43b2e8 | 211 | |
4e43b2e8 HS |
212 | /* |
213 | * Miscellaneous configurable options | |
214 | */ | |
4e43b2e8 | 215 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
4e43b2e8 HS |
216 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
217 | ||
4e43b2e8 | 218 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */ |
4e43b2e8 HS |
219 | |
220 | /* | |
221 | * For booting Linux, the board info and command line data | |
9f530d59 | 222 | * have to be in the first 256 MB of memory, since this is |
4e43b2e8 HS |
223 | * the maximum mapped by the Linux kernel during initialization. |
224 | */ | |
be29fa71 JH |
225 | /* Initial Memory map for Linux*/ |
226 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
4e43b2e8 | 227 | |
4e43b2e8 HS |
228 | /* System IO Config */ |
229 | #define CONFIG_SYS_SICRH (0x01000000 | \ | |
230 | SICRH_ETSEC2_B | \ | |
231 | SICRH_ETSEC2_C | \ | |
232 | SICRH_ETSEC2_D | \ | |
233 | SICRH_ETSEC2_E | \ | |
234 | SICRH_ETSEC2_F | \ | |
235 | SICRH_ETSEC2_G | \ | |
236 | SICRH_TSOBI1 | \ | |
237 | SICRH_TSOBI2) | |
238 | /* 0x010fff03 */ | |
239 | #define CONFIG_SYS_SICRL (SICRL_LBC | \ | |
240 | SICRL_SPI_A | \ | |
241 | SICRL_SPI_B | \ | |
242 | SICRL_SPI_C | \ | |
243 | SICRL_SPI_D | \ | |
244 | SICRL_ETSEC2_A) | |
245 | /* 0x33fc0003) */ | |
246 | ||
4e43b2e8 HS |
247 | #define CONFIG_NETDEV eth0 |
248 | ||
5bc0543d | 249 | #define CONFIG_HOSTNAME "ve8313" |
4e43b2e8 HS |
250 | #define CONFIG_UBOOTPATH ve8313/u-boot.bin |
251 | ||
4e43b2e8 | 252 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
5368c55d MV |
253 | "netdev=" __stringify(CONFIG_NETDEV) "\0" \ |
254 | "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \ | |
255 | "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
4e43b2e8 HS |
256 | "u-boot_addr_r=100000\0" \ |
257 | "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ | |
5368c55d MV |
258 | "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ |
259 | " +${filesize};" \ | |
260 | "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \ | |
261 | "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \ | |
be29fa71 | 262 | " ${filesize};" \ |
5368c55d | 263 | "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \ |
4e43b2e8 HS |
264 | |
265 | #endif /* __CONFIG_H */ |