]>
Commit | Line | Data |
---|---|---|
3d3befa7 WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Texas Instruments. | |
4 | * Kshitij Gupta <kshitij@ti.com> | |
5 | * Configuation settings for the TI OMAP Innovator board. | |
6 | * | |
7 | * (C) Copyright 2004 | |
8 | * ARM Ltd. | |
9 | * Philippe Robin, <philippe.robin@arm.com> | |
10 | * Configuration for Versatile PB. | |
11 | * | |
3765b3e7 | 12 | * SPDX-License-Identifier: GPL-2.0+ |
3d3befa7 WD |
13 | */ |
14 | ||
15 | #ifndef __CONFIG_H | |
16 | #define __CONFIG_H | |
17 | ||
18 | /* | |
19 | * High Level Configuration Options | |
20 | * (easy to change) | |
21 | */ | |
5d7b131d | 22 | #define CONFIG_VERSATILE 1 /* This is Versatile Platform Board */ |
2600b857 | 23 | #define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */ |
3d3befa7 | 24 | |
2600b857 JCPV |
25 | #define CONFIG_SYS_MEMTEST_START 0x100000 |
26 | #define CONFIG_SYS_MEMTEST_END 0x10000000 | |
3d3befa7 | 27 | |
5b6da283 RH |
28 | #define CONFIG_SYS_TIMERBASE 0x101E2000 /* Timer 0 and 1 base */ |
29 | #define CONFIG_SYS_TIMER_RATE (1000000 / 256) | |
30 | #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) | |
31 | #define CONFIG_SYS_TIMER_COUNTS_DOWN | |
3d3befa7 WD |
32 | |
33 | /* | |
34 | * control registers | |
35 | */ | |
2600b857 | 36 | #define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */ |
3d3befa7 WD |
37 | |
38 | /* | |
39 | * System controller bit assignment | |
40 | */ | |
41 | #define VERSATILE_REFCLK 0 | |
42 | #define VERSATILE_TIMCLK 1 | |
43 | ||
44 | #define VERSATILE_TIMER1_EnSel 15 | |
45 | #define VERSATILE_TIMER2_EnSel 17 | |
46 | #define VERSATILE_TIMER3_EnSel 19 | |
47 | #define VERSATILE_TIMER4_EnSel 21 | |
48 | ||
2600b857 | 49 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
3d3befa7 | 50 | #define CONFIG_SETUP_MEMORY_TAGS 1 |
2600b857 | 51 | #define CONFIG_MISC_INIT_R 1 |
3d3befa7 WD |
52 | /* |
53 | * Size of malloc() pool | |
54 | */ | |
d388298a | 55 | #define CONFIG_ENV_SIZE 8192 |
2600b857 | 56 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) |
3d3befa7 WD |
57 | |
58 | /* | |
59 | * Hardware drivers | |
60 | */ | |
61 | ||
7194ab80 | 62 | #define CONFIG_SMC91111 |
3d3befa7 | 63 | #define CONFIG_SMC_USE_32_BIT |
53677ef1 | 64 | #define CONFIG_SMC91111_BASE 0x10010000 |
3d3befa7 WD |
65 | #undef CONFIG_SMC91111_EXT_PHY |
66 | ||
67 | /* | |
68 | * NS16550 Configuration | |
69 | */ | |
48d0192f | 70 | #define CONFIG_PL011_SERIAL |
6705d81e | 71 | #define CONFIG_PL011_CLOCK 24000000 |
2600b857 JCPV |
72 | #define CONFIG_PL01x_PORTS \ |
73 | {(void *)CONFIG_SYS_SERIAL0, \ | |
74 | (void *)CONFIG_SYS_SERIAL1 } | |
3d3befa7 | 75 | #define CONFIG_CONS_INDEX 0 |
6705d81e | 76 | |
2600b857 | 77 | #define CONFIG_BAUDRATE 38400 |
6d0f6bcf JCPV |
78 | #define CONFIG_SYS_SERIAL0 0x101F1000 |
79 | #define CONFIG_SYS_SERIAL1 0x101F2000 | |
3d3befa7 | 80 | |
dca3b3d6 JL |
81 | /* |
82 | * Command line configuration. | |
83 | */ | |
2600b857 | 84 | #define CONFIG_CMD_BDI |
dca3b3d6 | 85 | #define CONFIG_CMD_DHCP |
2600b857 | 86 | #define CONFIG_CMD_FLASH |
dca3b3d6 | 87 | #define CONFIG_CMD_IMI |
2600b857 | 88 | #define CONFIG_CMD_MEMORY |
dca3b3d6 JL |
89 | #define CONFIG_CMD_NET |
90 | #define CONFIG_CMD_PING | |
bdab39d3 | 91 | #define CONFIG_CMD_SAVEENV |
3d3befa7 | 92 | |
d3b8c1a7 JL |
93 | /* |
94 | * BOOTP options | |
95 | */ | |
2600b857 | 96 | #define CONFIG_BOOTP_BOOTPATH |
d3b8c1a7 JL |
97 | #define CONFIG_BOOTP_GATEWAY |
98 | #define CONFIG_BOOTP_HOSTNAME | |
2600b857 | 99 | #define CONFIG_BOOTP_SUBNETMASK |
3d3befa7 WD |
100 | |
101 | #define CONFIG_BOOTDELAY 2 | |
2600b857 | 102 | #define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp "\ |
7d7c497d LW |
103 | "netdev=25,0,0xf1010000,0xf1010010,eth0 "\ |
104 | "console=ttyAMA0,38400n1" | |
3d3befa7 WD |
105 | |
106 | /* | |
107 | * Static configuration when assigning fixed address | |
108 | */ | |
2600b857 | 109 | #define CONFIG_BOOTFILE "/tftpboot/uImage" /* file to load */ |
3d3befa7 WD |
110 | |
111 | /* | |
112 | * Miscellaneous configurable options | |
113 | */ | |
2600b857 | 114 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
2600b857 | 115 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
d6e8ed83 JCPV |
116 | /* Monitor Command Prompt */ |
117 | #ifdef CONFIG_ARCH_VERSATILE_AB | |
118 | # define CONFIG_SYS_PROMPT "VersatileAB # " | |
119 | #else | |
120 | # define CONFIG_SYS_PROMPT "VersatilePB # " | |
121 | #endif | |
3d3befa7 | 122 | /* Print Buffer Size */ |
2600b857 JCPV |
123 | #define CONFIG_SYS_PBSIZE \ |
124 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
125 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
126 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
3d3befa7 | 127 | |
6d0f6bcf | 128 | #define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ |
3d3befa7 | 129 | |
3d3befa7 WD |
130 | /*----------------------------------------------------------------------- |
131 | * Physical Memory Map | |
132 | */ | |
2600b857 JCPV |
133 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
134 | #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ | |
135 | #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ | |
98692271 | 136 | #define PHYS_FLASH_SIZE 0x04000000 /* 64MB */ |
3d3befa7 | 137 | |
d388298a SB |
138 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
139 | #define CONFIG_SYS_INIT_RAM_ADDR 0x00800000 | |
140 | #define CONFIG_SYS_INIT_RAM_SIZE 0x000FFFFF | |
141 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
142 | GENERATED_GBL_DATA_SIZE) | |
143 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
144 | CONFIG_SYS_GBL_DATA_OFFSET) | |
145 | ||
146 | #define CONFIG_BOARD_EARLY_INIT_F | |
147 | ||
3d3befa7 WD |
148 | /*----------------------------------------------------------------------- |
149 | * FLASH and environment organization | |
150 | */ | |
d388298a SB |
151 | #ifdef CONFIG_ARCH_VERSATILE_QEMU |
152 | #define CONFIG_SYS_TEXT_BASE 0x10000 | |
153 | #define CONFIG_SYS_NO_FLASH | |
154 | #define CONFIG_ENV_IS_NOWHERE | |
155 | #define CONFIG_SYS_MONITOR_LEN 0x80000 | |
156 | #else | |
157 | #define CONFIG_SYS_TEXT_BASE 0x01000000 | |
98692271 JCPV |
158 | /* |
159 | * Use the CFI flash driver for ease of use | |
160 | */ | |
161 | #define CONFIG_SYS_FLASH_CFI | |
162 | #define CONFIG_FLASH_CFI_DRIVER | |
163 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
164 | /* | |
165 | * System control register | |
166 | */ | |
2600b857 JCPV |
167 | #define VERSATILE_SYS_BASE 0x10000000 |
168 | #define VERSATILE_SYS_FLASH_OFFSET 0x4C | |
169 | #define VERSATILE_FLASHCTRL \ | |
170 | (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET) | |
171 | /* Enable writing to flash */ | |
172 | #define VERSATILE_FLASHPROG_FLVPPEN (1 << 0) | |
d407bf52 | 173 | |
3d3befa7 | 174 | /* timeout values are in ticks */ |
98692271 JCPV |
175 | #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ |
176 | #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ | |
177 | ||
178 | /* | |
179 | * Note that CONFIG_SYS_MAX_FLASH_SECT allows for a parameter block | |
180 | * i.e. | |
181 | * the bottom "sector" (bottom boot), or top "sector" | |
182 | * (top boot), is a seperate erase region divided into | |
183 | * 4 (equal) smaller sectors. This, notionally, allows | |
184 | * quicker erase/rewrire of the most frequently changed | |
185 | * area...... | |
186 | * CONFIG_SYS_MAX_FLASH_SECT is padded up to a multiple of 4 | |
187 | */ | |
188 | ||
189 | #ifdef CONFIG_ARCH_VERSATILE_AB | |
190 | #define FLASH_SECTOR_SIZE 0x00020000 /* 128 KB sectors */ | |
191 | #define CONFIG_ENV_SECT_SIZE (2 * FLASH_SECTOR_SIZE) | |
192 | #define CONFIG_SYS_MAX_FLASH_SECT (520) | |
193 | #endif | |
194 | ||
195 | #ifdef CONFIG_ARCH_VERSATILE_PB /* Versatile PB is default */ | |
196 | #define FLASH_SECTOR_SIZE 0x00040000 /* 256 KB sectors */ | |
197 | #define CONFIG_ENV_SECT_SIZE FLASH_SECTOR_SIZE | |
198 | #define CONFIG_SYS_MAX_FLASH_SECT (260) | |
199 | #endif | |
200 | ||
201 | #define CONFIG_SYS_FLASH_BASE 0x34000000 | |
202 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
203 | ||
204 | #define CONFIG_SYS_MONITOR_LEN (4 * CONFIG_ENV_SECT_SIZE) | |
205 | ||
206 | /* The ARM Boot Monitor is shipped in the lowest sector of flash */ | |
3d3befa7 | 207 | |
98692271 | 208 | #define FLASH_TOP (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE) |
98692271 JCPV |
209 | #define CONFIG_ENV_ADDR (FLASH_TOP - CONFIG_ENV_SECT_SIZE) |
210 | #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) | |
211 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_ENV_ADDR - CONFIG_SYS_MONITOR_LEN) | |
3d3befa7 | 212 | |
98692271 JCPV |
213 | #define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ |
214 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ | |
d407bf52 | 215 | |
de1f9ac8 | 216 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ |
d388298a SB |
217 | #endif |
218 | ||
98692271 | 219 | #endif /* __CONFIG_H */ |