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3d3befa7 WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Texas Instruments. | |
4 | * Kshitij Gupta <kshitij@ti.com> | |
5 | * Configuation settings for the TI OMAP Innovator board. | |
6 | * | |
7 | * (C) Copyright 2004 | |
8 | * ARM Ltd. | |
9 | * Philippe Robin, <philippe.robin@arm.com> | |
10 | * Configuration for Versatile PB. | |
11 | * | |
12 | * See file CREDITS for list of people who contributed to this | |
13 | * project. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License as | |
17 | * published by the Free Software Foundation; either version 2 of | |
18 | * the License, or (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
28 | * MA 02111-1307 USA | |
29 | */ | |
30 | ||
31 | #ifndef __CONFIG_H | |
32 | #define __CONFIG_H | |
33 | ||
34 | /* | |
35 | * High Level Configuration Options | |
36 | * (easy to change) | |
37 | */ | |
2600b857 | 38 | #define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ |
3d3befa7 | 39 | #define CONFIG_VERSATILE 1 /* in Versatile Platform Board */ |
2600b857 | 40 | #define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */ |
3d3befa7 | 41 | |
2600b857 JCPV |
42 | #define CONFIG_SYS_MEMTEST_START 0x100000 |
43 | #define CONFIG_SYS_MEMTEST_END 0x10000000 | |
44 | #define CONFIG_SYS_HZ (1000000 / 256) | |
45 | #define CONFIG_SYS_TIMERBASE 0x101E2000 /* Timer 0 and 1 base */ | |
3d3befa7 | 46 | |
6d0f6bcf | 47 | #define CONFIG_SYS_TIMER_INTERVAL 10000 |
2600b857 JCPV |
48 | #define CONFIG_SYS_TIMER_RELOAD (CONFIG_SYS_TIMER_INTERVAL >> 4) |
49 | #define CONFIG_SYS_TIMER_CTRL 0x84 /* Enable, Clock / 16 */ | |
3d3befa7 WD |
50 | |
51 | /* | |
52 | * control registers | |
53 | */ | |
2600b857 | 54 | #define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */ |
3d3befa7 WD |
55 | |
56 | /* | |
57 | * System controller bit assignment | |
58 | */ | |
59 | #define VERSATILE_REFCLK 0 | |
60 | #define VERSATILE_TIMCLK 1 | |
61 | ||
62 | #define VERSATILE_TIMER1_EnSel 15 | |
63 | #define VERSATILE_TIMER2_EnSel 17 | |
64 | #define VERSATILE_TIMER3_EnSel 19 | |
65 | #define VERSATILE_TIMER4_EnSel 21 | |
66 | ||
2600b857 | 67 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
3d3befa7 | 68 | #define CONFIG_SETUP_MEMORY_TAGS 1 |
2600b857 | 69 | #define CONFIG_MISC_INIT_R 1 |
3d3befa7 WD |
70 | /* |
71 | * Size of malloc() pool | |
72 | */ | |
d388298a | 73 | #define CONFIG_ENV_SIZE 8192 |
2600b857 | 74 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) |
3d3befa7 WD |
75 | |
76 | /* | |
77 | * Hardware drivers | |
78 | */ | |
79 | ||
7194ab80 | 80 | #define CONFIG_SMC91111 |
3d3befa7 | 81 | #define CONFIG_SMC_USE_32_BIT |
53677ef1 | 82 | #define CONFIG_SMC91111_BASE 0x10010000 |
3d3befa7 WD |
83 | #undef CONFIG_SMC91111_EXT_PHY |
84 | ||
85 | /* | |
86 | * NS16550 Configuration | |
87 | */ | |
48d0192f | 88 | #define CONFIG_PL011_SERIAL |
6705d81e | 89 | #define CONFIG_PL011_CLOCK 24000000 |
2600b857 JCPV |
90 | #define CONFIG_PL01x_PORTS \ |
91 | {(void *)CONFIG_SYS_SERIAL0, \ | |
92 | (void *)CONFIG_SYS_SERIAL1 } | |
3d3befa7 | 93 | #define CONFIG_CONS_INDEX 0 |
6705d81e | 94 | |
2600b857 | 95 | #define CONFIG_BAUDRATE 38400 |
6d0f6bcf JCPV |
96 | #define CONFIG_SYS_SERIAL0 0x101F1000 |
97 | #define CONFIG_SYS_SERIAL1 0x101F2000 | |
3d3befa7 | 98 | |
dca3b3d6 JL |
99 | /* |
100 | * Command line configuration. | |
101 | */ | |
2600b857 | 102 | #define CONFIG_CMD_BDI |
dca3b3d6 | 103 | #define CONFIG_CMD_DHCP |
2600b857 | 104 | #define CONFIG_CMD_FLASH |
dca3b3d6 | 105 | #define CONFIG_CMD_IMI |
2600b857 | 106 | #define CONFIG_CMD_MEMORY |
dca3b3d6 JL |
107 | #define CONFIG_CMD_NET |
108 | #define CONFIG_CMD_PING | |
bdab39d3 | 109 | #define CONFIG_CMD_SAVEENV |
3d3befa7 | 110 | |
d3b8c1a7 JL |
111 | /* |
112 | * BOOTP options | |
113 | */ | |
2600b857 | 114 | #define CONFIG_BOOTP_BOOTPATH |
d3b8c1a7 JL |
115 | #define CONFIG_BOOTP_GATEWAY |
116 | #define CONFIG_BOOTP_HOSTNAME | |
2600b857 | 117 | #define CONFIG_BOOTP_SUBNETMASK |
3d3befa7 WD |
118 | |
119 | #define CONFIG_BOOTDELAY 2 | |
2600b857 JCPV |
120 | #define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp "\ |
121 | "netdev=25,0,0xf1010000,0xf1010010,eth0" | |
3d3befa7 WD |
122 | |
123 | /* | |
124 | * Static configuration when assigning fixed address | |
125 | */ | |
2600b857 | 126 | #define CONFIG_BOOTFILE "/tftpboot/uImage" /* file to load */ |
3d3befa7 WD |
127 | |
128 | /* | |
129 | * Miscellaneous configurable options | |
130 | */ | |
2600b857 | 131 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
2600b857 | 132 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
d6e8ed83 JCPV |
133 | /* Monitor Command Prompt */ |
134 | #ifdef CONFIG_ARCH_VERSATILE_AB | |
135 | # define CONFIG_SYS_PROMPT "VersatileAB # " | |
136 | #else | |
137 | # define CONFIG_SYS_PROMPT "VersatilePB # " | |
138 | #endif | |
3d3befa7 | 139 | /* Print Buffer Size */ |
2600b857 JCPV |
140 | #define CONFIG_SYS_PBSIZE \ |
141 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
142 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
143 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
3d3befa7 | 144 | |
6d0f6bcf | 145 | #define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ |
3d3befa7 | 146 | |
3d3befa7 WD |
147 | /*----------------------------------------------------------------------- |
148 | * Physical Memory Map | |
149 | */ | |
2600b857 JCPV |
150 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
151 | #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ | |
152 | #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ | |
98692271 | 153 | #define PHYS_FLASH_SIZE 0x04000000 /* 64MB */ |
3d3befa7 | 154 | |
d388298a SB |
155 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
156 | #define CONFIG_SYS_INIT_RAM_ADDR 0x00800000 | |
157 | #define CONFIG_SYS_INIT_RAM_SIZE 0x000FFFFF | |
158 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
159 | GENERATED_GBL_DATA_SIZE) | |
160 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
161 | CONFIG_SYS_GBL_DATA_OFFSET) | |
162 | ||
163 | #define CONFIG_BOARD_EARLY_INIT_F | |
164 | ||
3d3befa7 WD |
165 | /*----------------------------------------------------------------------- |
166 | * FLASH and environment organization | |
167 | */ | |
d388298a SB |
168 | #ifdef CONFIG_ARCH_VERSATILE_QEMU |
169 | #define CONFIG_SYS_TEXT_BASE 0x10000 | |
170 | #define CONFIG_SYS_NO_FLASH | |
171 | #define CONFIG_ENV_IS_NOWHERE | |
172 | #define CONFIG_SYS_MONITOR_LEN 0x80000 | |
173 | #else | |
174 | #define CONFIG_SYS_TEXT_BASE 0x01000000 | |
98692271 JCPV |
175 | /* |
176 | * Use the CFI flash driver for ease of use | |
177 | */ | |
178 | #define CONFIG_SYS_FLASH_CFI | |
179 | #define CONFIG_FLASH_CFI_DRIVER | |
180 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
181 | /* | |
182 | * System control register | |
183 | */ | |
2600b857 JCPV |
184 | #define VERSATILE_SYS_BASE 0x10000000 |
185 | #define VERSATILE_SYS_FLASH_OFFSET 0x4C | |
186 | #define VERSATILE_FLASHCTRL \ | |
187 | (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET) | |
188 | /* Enable writing to flash */ | |
189 | #define VERSATILE_FLASHPROG_FLVPPEN (1 << 0) | |
d407bf52 | 190 | |
3d3befa7 | 191 | /* timeout values are in ticks */ |
98692271 JCPV |
192 | #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ |
193 | #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ | |
194 | ||
195 | /* | |
196 | * Note that CONFIG_SYS_MAX_FLASH_SECT allows for a parameter block | |
197 | * i.e. | |
198 | * the bottom "sector" (bottom boot), or top "sector" | |
199 | * (top boot), is a seperate erase region divided into | |
200 | * 4 (equal) smaller sectors. This, notionally, allows | |
201 | * quicker erase/rewrire of the most frequently changed | |
202 | * area...... | |
203 | * CONFIG_SYS_MAX_FLASH_SECT is padded up to a multiple of 4 | |
204 | */ | |
205 | ||
206 | #ifdef CONFIG_ARCH_VERSATILE_AB | |
207 | #define FLASH_SECTOR_SIZE 0x00020000 /* 128 KB sectors */ | |
208 | #define CONFIG_ENV_SECT_SIZE (2 * FLASH_SECTOR_SIZE) | |
209 | #define CONFIG_SYS_MAX_FLASH_SECT (520) | |
210 | #endif | |
211 | ||
212 | #ifdef CONFIG_ARCH_VERSATILE_PB /* Versatile PB is default */ | |
213 | #define FLASH_SECTOR_SIZE 0x00040000 /* 256 KB sectors */ | |
214 | #define CONFIG_ENV_SECT_SIZE FLASH_SECTOR_SIZE | |
215 | #define CONFIG_SYS_MAX_FLASH_SECT (260) | |
216 | #endif | |
217 | ||
218 | #define CONFIG_SYS_FLASH_BASE 0x34000000 | |
219 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
220 | ||
221 | #define CONFIG_SYS_MONITOR_LEN (4 * CONFIG_ENV_SECT_SIZE) | |
222 | ||
223 | /* The ARM Boot Monitor is shipped in the lowest sector of flash */ | |
3d3befa7 | 224 | |
98692271 | 225 | #define FLASH_TOP (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE) |
98692271 JCPV |
226 | #define CONFIG_ENV_ADDR (FLASH_TOP - CONFIG_ENV_SECT_SIZE) |
227 | #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) | |
228 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_ENV_ADDR - CONFIG_SYS_MONITOR_LEN) | |
3d3befa7 | 229 | |
98692271 JCPV |
230 | #define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ |
231 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ | |
d407bf52 | 232 | |
de1f9ac8 | 233 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ |
d388298a SB |
234 | #endif |
235 | ||
98692271 | 236 | #endif /* __CONFIG_H */ |