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12916829 DF |
1 | /* |
2 | * Configuration for Versatile Express. Parts were derived from other ARM | |
3 | * configurations. | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #ifndef __VEXPRESS_AEMV8A_H | |
9 | #define __VEXPRESS_AEMV8A_H | |
10 | ||
f91afc4d | 11 | #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP |
261d2760 | 12 | #ifndef CONFIG_SEMIHOSTING |
f91afc4d | 13 | #error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING |
261d2760 | 14 | #endif |
261d2760 DR |
15 | #define CONFIG_ARMV8_SWITCH_TO_EL1 |
16 | #endif | |
17 | ||
12916829 DF |
18 | #define CONFIG_REMAKE_ELF |
19 | ||
12916829 DF |
20 | #define CONFIG_SUPPORT_RAW_INITRD |
21 | ||
12916829 | 22 | #define CONFIG_IDENT_STRING " vexpress_aemv8a" |
12916829 DF |
23 | |
24 | /* Link Definitions */ | |
fc04b923 RH |
25 | #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ |
26 | defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM) | |
261d2760 DR |
27 | /* ATF loads u-boot here for BASE_FVP model */ |
28 | #define CONFIG_SYS_TEXT_BASE 0x88000000 | |
29 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) | |
ffc10373 LW |
30 | #elif CONFIG_TARGET_VEXPRESS64_JUNO |
31 | #define CONFIG_SYS_TEXT_BASE 0xe0000000 | |
32 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) | |
261d2760 | 33 | #endif |
12916829 | 34 | |
0d3012af RH |
35 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
36 | ||
12916829 DF |
37 | /* CS register bases for the original memory map. */ |
38 | #define V2M_PA_CS0 0x00000000 | |
39 | #define V2M_PA_CS1 0x14000000 | |
40 | #define V2M_PA_CS2 0x18000000 | |
41 | #define V2M_PA_CS3 0x1c000000 | |
42 | #define V2M_PA_CS4 0x0c000000 | |
43 | #define V2M_PA_CS5 0x10000000 | |
44 | ||
45 | #define V2M_PERIPH_OFFSET(x) (x << 16) | |
46 | #define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1)) | |
47 | #define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2)) | |
48 | #define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3)) | |
49 | ||
50 | #define V2M_BASE 0x80000000 | |
51 | ||
12916829 DF |
52 | /* Common peripherals relative to CS7. */ |
53 | #define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) | |
54 | #define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) | |
55 | #define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6)) | |
56 | #define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7)) | |
57 | ||
ffc10373 LW |
58 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
59 | #define V2M_UART0 0x7ff80000 | |
60 | #define V2M_UART1 0x7ff70000 | |
61 | #else /* Not Juno */ | |
12916829 DF |
62 | #define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9)) |
63 | #define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10)) | |
64 | #define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11)) | |
65 | #define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12)) | |
ffc10373 | 66 | #endif |
12916829 DF |
67 | |
68 | #define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15)) | |
69 | ||
70 | #define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17)) | |
71 | #define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18)) | |
72 | ||
73 | #define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22)) | |
74 | #define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23)) | |
75 | ||
76 | #define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26)) | |
77 | ||
78 | #define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31)) | |
79 | ||
80 | /* System register offsets. */ | |
81 | #define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) | |
82 | #define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) | |
83 | #define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) | |
84 | ||
85 | /* Generic Timer Definitions */ | |
86 | #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ | |
87 | ||
88 | /* Generic Interrupt Controller Definitions */ | |
c71645ad DF |
89 | #ifdef CONFIG_GICV3 |
90 | #define GICD_BASE (0x2f000000) | |
91 | #define GICR_BASE (0x2f100000) | |
92 | #else | |
261d2760 | 93 | |
fc04b923 RH |
94 | #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ |
95 | defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM) | |
261d2760 DR |
96 | #define GICD_BASE (0x2f000000) |
97 | #define GICC_BASE (0x2c000000) | |
ffc10373 LW |
98 | #elif CONFIG_TARGET_VEXPRESS64_JUNO |
99 | #define GICD_BASE (0x2C010000) | |
100 | #define GICC_BASE (0x2C02f000) | |
261d2760 | 101 | #endif |
03314f0e | 102 | #endif /* !CONFIG_GICV3 */ |
12916829 | 103 | |
12916829 | 104 | /* Size of malloc() pool */ |
5bcae13e | 105 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) |
12916829 | 106 | |
b31f9d7a LW |
107 | /* Ethernet Configuration */ |
108 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO | |
109 | /* The real hardware Versatile express uses SMSC9118 */ | |
110 | #define CONFIG_SMC911X 1 | |
111 | #define CONFIG_SMC911X_32_BIT 1 | |
112 | #define CONFIG_SMC911X_BASE (0x018000000) | |
113 | #else | |
114 | /* The Vexpress64 simulators use SMSC91C111 */ | |
3865ceb7 BS |
115 | #define CONFIG_SMC91111 1 |
116 | #define CONFIG_SMC91111_BASE (0x01A000000) | |
b31f9d7a | 117 | #endif |
12916829 DF |
118 | |
119 | /* PL011 Serial Configuration */ | |
d280ea00 | 120 | #define CONFIG_BAUDRATE 115200 |
d8bafe13 | 121 | #define CONFIG_CONS_INDEX 0 |
d280ea00 | 122 | #define CONFIG_PL01X_SERIAL |
12916829 | 123 | #define CONFIG_PL011_SERIAL |
ffc10373 LW |
124 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
125 | #define CONFIG_PL011_CLOCK 7273800 | |
126 | #else | |
12916829 | 127 | #define CONFIG_PL011_CLOCK 24000000 |
ffc10373 | 128 | #endif |
12916829 DF |
129 | |
130 | /* Command line configuration */ | |
131 | #define CONFIG_MENU | |
132 | /*#define CONFIG_MENU_SHOW*/ | |
67172528 | 133 | #define CONFIG_CMD_UNZIP |
12916829 DF |
134 | #define CONFIG_CMD_PXE |
135 | #define CONFIG_CMD_ENV | |
12916829 DF |
136 | #define CONFIG_DOS_PARTITION |
137 | ||
138 | /* BOOTP options */ | |
139 | #define CONFIG_BOOTP_BOOTFILESIZE | |
140 | #define CONFIG_BOOTP_BOOTPATH | |
141 | #define CONFIG_BOOTP_GATEWAY | |
142 | #define CONFIG_BOOTP_HOSTNAME | |
143 | #define CONFIG_BOOTP_PXE | |
12916829 DF |
144 | |
145 | /* Miscellaneous configurable options */ | |
146 | #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) | |
147 | ||
148 | /* Physical Memory Map */ | |
12916829 | 149 | #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ |
30355708 LW |
150 | /* Top 16MB reserved for secure world use */ |
151 | #define DRAM_SEC_SIZE 0x01000000 | |
152 | #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE | |
153 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
154 | ||
2c2b2183 RH |
155 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
156 | #define CONFIG_NR_DRAM_BANKS 2 | |
157 | #define PHYS_SDRAM_2 (0x880000000) | |
158 | #define PHYS_SDRAM_2_SIZE 0x180000000 | |
159 | #else | |
160 | #define CONFIG_NR_DRAM_BANKS 1 | |
161 | #endif | |
162 | ||
30355708 | 163 | /* Enable memtest */ |
30355708 LW |
164 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 |
165 | #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) | |
12916829 DF |
166 | |
167 | /* Initial environment variables */ | |
10d1491b LW |
168 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
169 | /* | |
170 | * Defines where the kernel and FDT exist in NOR flash and where it will | |
171 | * be copied into DRAM | |
172 | */ | |
173 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
ecbed5d6 RH |
174 | "kernel_name=norkern\0" \ |
175 | "kernel_alt_name=Image\0" \ | |
7babe482 | 176 | "kernel_addr=0x80080000\0" \ |
4a6bdb59 RH |
177 | "initrd_name=ramdisk.img\0" \ |
178 | "initrd_addr=0x84000000\0" \ | |
da3e620d | 179 | "fdtfile=board.dtb\0" \ |
ecbed5d6 | 180 | "fdt_alt_name=juno\0" \ |
10d1491b LW |
181 | "fdt_addr=0x83000000\0" \ |
182 | "fdt_high=0xffffffffffffffff\0" \ | |
183 | "initrd_high=0xffffffffffffffff\0" \ | |
184 | ||
185 | /* Assume we boot with root on the first partition of a USB stick */ | |
186 | #define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " \ | |
492f24e8 | 187 | "root=/dev/sda2 rw " \ |
33665f7c | 188 | "rootwait "\ |
c0ae9703 RH |
189 | "earlyprintk=pl011,0x7ff80000 debug "\ |
190 | "user_debug=31 "\ | |
74e264b4 | 191 | "androidboot.hardware=juno "\ |
10d1491b LW |
192 | "loglevel=9" |
193 | ||
194 | /* Copy the kernel and FDT to DRAM memory and boot */ | |
195 | #define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr} ; " \ | |
ecbed5d6 RH |
196 | "if test $? -eq 1; then "\ |
197 | " echo Loading ${kernel_alt_name} instead of "\ | |
198 | "${kernel_name}; "\ | |
199 | " afs load ${kernel_alt_name} ${kernel_addr};"\ | |
200 | "fi ; "\ | |
da3e620d | 201 | "afs load ${fdtfile} ${fdt_addr} ; " \ |
ecbed5d6 RH |
202 | "if test $? -eq 1; then "\ |
203 | " echo Loading ${fdt_alt_name} instead of "\ | |
da3e620d | 204 | "${fdtfile}; "\ |
ecbed5d6 RH |
205 | " afs load ${fdt_alt_name} ${fdt_addr}; "\ |
206 | "fi ; "\ | |
10d1491b | 207 | "fdt addr ${fdt_addr}; fdt resize; " \ |
4a6bdb59 RH |
208 | "if afs load ${initrd_name} ${initrd_addr} ; "\ |
209 | "then "\ | |
210 | " setenv initrd_param ${initrd_addr}; "\ | |
211 | " else setenv initrd_param -; "\ | |
212 | "fi ; " \ | |
213 | "booti ${kernel_addr} ${initrd_param} ${fdt_addr}" | |
10d1491b | 214 | |
10d1491b LW |
215 | |
216 | #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP | |
261d2760 | 217 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
1fd0f92e | 218 | "kernel_name=Image\0" \ |
7babe482 | 219 | "kernel_addr=0x80080000\0" \ |
261d2760 | 220 | "initrd_name=ramdisk.img\0" \ |
49995ffe | 221 | "initrd_addr=0x88000000\0" \ |
da3e620d | 222 | "fdtfile=devtree.dtb\0" \ |
49995ffe | 223 | "fdt_addr=0x83000000\0" \ |
261d2760 DR |
224 | "fdt_high=0xffffffffffffffff\0" \ |
225 | "initrd_high=0xffffffffffffffff\0" | |
226 | ||
227 | #define CONFIG_BOOTARGS "console=ttyAMA0 earlyprintk=pl011,"\ | |
228 | "0x1c090000 debug user_debug=31 "\ | |
229 | "loglevel=9" | |
230 | ||
49995ffe | 231 | #define CONFIG_BOOTCOMMAND "smhload ${kernel_name} ${kernel_addr}; " \ |
da3e620d | 232 | "smhload ${fdtfile} ${fdt_addr}; " \ |
c0ae9703 RH |
233 | "smhload ${initrd_name} ${initrd_addr} "\ |
234 | "initrd_end; " \ | |
1fd0f92e LW |
235 | "fdt addr ${fdt_addr}; fdt resize; " \ |
236 | "fdt chosen ${initrd_addr} ${initrd_end}; " \ | |
237 | "booti $kernel_addr - $fdt_addr" | |
261d2760 | 238 | |
261d2760 | 239 | |
fc04b923 RH |
240 | #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM |
241 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
242 | "kernel_addr=0x80080000\0" \ | |
243 | "initrd_addr=0x84000000\0" \ | |
244 | "fdt_addr=0x83000000\0" \ | |
245 | "fdt_high=0xffffffffffffffff\0" \ | |
246 | "initrd_high=0xffffffffffffffff\0" | |
247 | ||
248 | #define CONFIG_BOOTARGS "console=ttyAMA0 earlyprintk=pl011,"\ | |
249 | "0x1c090000 debug user_debug=31 "\ | |
250 | "androidboot.hardware=fvpbase "\ | |
251 | "root=/dev/vda2 rw "\ | |
252 | "rootwait "\ | |
253 | "loglevel=9" | |
254 | ||
255 | #define CONFIG_BOOTCOMMAND "booti $kernel_addr $initrd_addr $fdt_addr" | |
256 | ||
fc04b923 | 257 | |
261d2760 | 258 | #endif |
12916829 | 259 | |
12916829 DF |
260 | /* Monitor Command Prompt */ |
261 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
12916829 DF |
262 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
263 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
12916829 DF |
264 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
265 | #define CONFIG_SYS_LONGHELP | |
5bcae13e | 266 | #define CONFIG_CMDLINE_EDITING |
12916829 DF |
267 | #define CONFIG_SYS_MAXARGS 64 /* max command args */ |
268 | ||
f3c71c93 RH |
269 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
270 | #define CONFIG_SYS_FLASH_BASE 0x08000000 | |
271 | /* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */ | |
272 | #define CONFIG_SYS_MAX_FLASH_SECT 259 | |
273 | /* Store environment at top of flash in the same location as blank.img */ | |
274 | /* in the Juno firmware. */ | |
275 | #define CONFIG_ENV_ADDR 0x0BFC0000 | |
276 | #define CONFIG_ENV_SECT_SIZE 0x00010000 | |
14f264e6 | 277 | #else |
f3c71c93 RH |
278 | #define CONFIG_SYS_FLASH_BASE 0x0C000000 |
279 | /* 256 x 256KiB sectors */ | |
280 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
281 | /* Store environment at top of flash */ | |
282 | #define CONFIG_ENV_ADDR 0x0FFC0000 | |
283 | #define CONFIG_ENV_SECT_SIZE 0x00040000 | |
284 | #endif | |
285 | ||
14f264e6 LW |
286 | #define CONFIG_SYS_FLASH_CFI 1 |
287 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
f19f389f | 288 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT |
f3c71c93 | 289 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
14f264e6 | 290 | |
14f264e6 LW |
291 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ |
292 | #define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ | |
293 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ | |
f3c71c93 RH |
294 | #define FLASH_MAX_SECTOR_SIZE 0x00040000 |
295 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE | |
296 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
14f264e6 | 297 | |
12916829 | 298 | #endif /* __VEXPRESS_AEMV8A_H */ |