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f8f8acd7 SB |
1 | /* |
2 | * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> | |
3 | * | |
4 | * (C) Copyright 2009 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * Configuration settings for the MX51-3Stack Freescale board. | |
7 | * | |
3765b3e7 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
f8f8acd7 SB |
9 | */ |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
f8f8acd7 SB |
14 | |
15 | #define CONFIG_MX51 /* in a mx51 */ | |
c02d8280 | 16 | #define CONFIG_SYS_TEXT_BASE 0x97800000 |
f8f8acd7 | 17 | |
595f3e56 LHR |
18 | #include <asm/arch/imx-regs.h> |
19 | ||
f8f8acd7 SB |
20 | #define CONFIG_DISPLAY_CPUINFO |
21 | #define CONFIG_DISPLAY_BOARDINFO | |
22 | ||
23 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
f8f8acd7 SB |
24 | #define CONFIG_SETUP_MEMORY_TAGS |
25 | #define CONFIG_INITRD_TAG | |
9660e442 | 26 | #define CONFIG_BOARD_LATE_INIT |
f8f8acd7 | 27 | |
1cf820f1 SB |
28 | #ifndef MACH_TYPE_TTC_VISION2 |
29 | #define MACH_TYPE_TTC_VISION2 2775 | |
30 | #endif | |
db545e49 FE |
31 | #define CONFIG_MACH_TYPE MACH_TYPE_TTC_VISION2 |
32 | ||
f8f8acd7 SB |
33 | /* |
34 | * Size of malloc() pool | |
35 | */ | |
e9934f0b | 36 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
f8f8acd7 | 37 | |
f8f8acd7 SB |
38 | /* |
39 | * Hardware drivers | |
40 | */ | |
41 | #define CONFIG_MXC_UART | |
40f6fffe | 42 | #define CONFIG_MXC_UART_BASE UART3_BASE |
f8f8acd7 SB |
43 | #define CONFIG_MXC_GPIO |
44 | #define CONFIG_MXC_SPI | |
45 | #define CONFIG_HW_WATCHDOG | |
46 | ||
47 | /* | |
48 | * SPI Configs | |
49 | * */ | |
50 | #define CONFIG_FSL_SF | |
51 | #define CONFIG_CMD_SF | |
52 | ||
f8f8acd7 SB |
53 | #define CONFIG_SPI_FLASH_STMICRO |
54 | ||
55 | /* | |
56 | * Use gpio 4 pin 25 as chip select for SPI flash | |
57 | * This corresponds to gpio 121 | |
58 | */ | |
155fa9af | 59 | #define CONFIG_SF_DEFAULT_CS 1 |
f8f8acd7 SB |
60 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 |
61 | #define CONFIG_SF_DEFAULT_SPEED 25000000 | |
62 | ||
155fa9af | 63 | #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS |
f8f8acd7 SB |
64 | #define CONFIG_ENV_SPI_BUS 0 |
65 | #define CONFIG_ENV_SPI_MAX_HZ 25000000 | |
66 | #define CONFIG_ENV_SPI_MODE SPI_MODE_0 | |
67 | ||
68 | #define CONFIG_ENV_OFFSET (6 * 64 * 1024) | |
69 | #define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024) | |
70 | #define CONFIG_ENV_SIZE (4 * 1024) | |
71 | ||
72 | #define CONFIG_FSL_ENV_IN_SF | |
73 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
74 | ||
75 | /* PMIC Controller */ | |
be3b51aa ŁM |
76 | #define CONFIG_POWER |
77 | #define CONFIG_POWER_SPI | |
78 | #define CONFIG_POWER_FSL | |
f8f8acd7 SB |
79 | #define CONFIG_FSL_PMIC_BUS 0 |
80 | #define CONFIG_FSL_PMIC_CS 0 | |
81 | #define CONFIG_FSL_PMIC_CLK 2500000 | |
82 | #define CONFIG_FSL_PMIC_MODE SPI_MODE_0 | |
bac395ee | 83 | #define CONFIG_FSL_PMIC_BITLEN 32 |
4e8b7544 | 84 | #define CONFIG_RTC_MC13XXX |
f8f8acd7 SB |
85 | |
86 | /* | |
87 | * MMC Configs | |
88 | */ | |
89 | #define CONFIG_FSL_ESDHC | |
90 | #ifdef CONFIG_FSL_ESDHC | |
91 | #define CONFIG_SYS_FSL_ESDHC_ADDR (0x70004000) | |
92 | #define CONFIG_SYS_FSL_ESDHC_NUM 1 | |
93 | ||
94 | #define CONFIG_MMC | |
95 | ||
96 | #define CONFIG_CMD_MMC | |
97 | #define CONFIG_GENERIC_MMC | |
98 | #define CONFIG_CMD_FAT | |
99 | #define CONFIG_DOS_PARTITION | |
100 | #endif | |
101 | ||
102 | #define CONFIG_CMD_DATE | |
103 | ||
104 | /* | |
105 | * Eth Configs | |
106 | */ | |
107 | #define CONFIG_HAS_ETH1 | |
f8f8acd7 | 108 | #define CONFIG_MII |
f8f8acd7 SB |
109 | |
110 | #define CONFIG_FEC_MXC | |
111 | #define IMX_FEC_BASE FEC_BASE_ADDR | |
112 | #define CONFIG_FEC_MXC_PHYADDR 0x1F | |
113 | ||
114 | #define CONFIG_CMD_PING | |
115 | #define CONFIG_CMD_MII | |
f8f8acd7 SB |
116 | |
117 | /* allow to overwrite serial and ethaddr */ | |
118 | #define CONFIG_ENV_OVERWRITE | |
119 | #define CONFIG_CONS_INDEX 3 | |
120 | #define CONFIG_BAUDRATE 115200 | |
f8f8acd7 SB |
121 | |
122 | /*********************************************************** | |
123 | * Command definition | |
124 | ***********************************************************/ | |
125 | ||
f8f8acd7 | 126 | #define CONFIG_CMD_SPI |
f8f8acd7 SB |
127 | |
128 | #define CONFIG_BOOTDELAY 3 | |
129 | ||
130 | #define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */ | |
131 | ||
132 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
133 | "netdev=eth0\0" \ | |
134 | "loadaddr=0x90800000\0" | |
135 | ||
136 | /* | |
137 | * Miscellaneous configurable options | |
138 | */ | |
139 | #define CONFIG_SYS_LONGHELP | |
f8f8acd7 SB |
140 | #define CONFIG_AUTO_COMPLETE |
141 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
142 | ||
143 | /* Print Buffer Size */ | |
144 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
145 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
146 | #define CONFIG_SYS_MAXARGS 64 /* max number of command args */ | |
147 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
148 | ||
149 | #define CONFIG_SYS_MEMTEST_START 0x90000000 | |
150 | #define CONFIG_SYS_MEMTEST_END 0x10000 | |
151 | ||
152 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
153 | ||
f8f8acd7 SB |
154 | #define CONFIG_CMDLINE_EDITING |
155 | #define CONFIG_SYS_HUSH_PARSER | |
f8f8acd7 | 156 | |
f8f8acd7 SB |
157 | /* |
158 | * Physical Memory Map | |
159 | */ | |
160 | #define CONFIG_NR_DRAM_BANKS 2 | |
161 | #define PHYS_SDRAM_1 CSD0_BASE_ADDR | |
162 | #define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) | |
163 | #define PHYS_SDRAM_2 CSD1_BASE_ADDR | |
164 | #define PHYS_SDRAM_2_SIZE (256 * 1024 * 1024) | |
43883dc3 SB |
165 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
166 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
167 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
168 | ||
169 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
170 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
171 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
172 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
173 | ||
f8f8acd7 SB |
174 | #define CONFIG_BOARD_EARLY_INIT_F |
175 | ||
176 | /* 166 MHz DDR RAM */ | |
177 | #define CONFIG_SYS_DDR_CLKSEL 0 | |
178 | #define CONFIG_SYS_CLKTL_CBCDR 0x19239100 | |
39e85761 | 179 | #define CONFIG_SYS_MAIN_PWR_ON |
f8f8acd7 SB |
180 | |
181 | #define CONFIG_SYS_NO_FLASH | |
182 | ||
a0152c4b SB |
183 | /* |
184 | * Framebuffer and LCD | |
185 | */ | |
186 | #define CONFIG_PREBOOT | |
e9934f0b | 187 | #define CONFIG_VIDEO |
695af9ab | 188 | #define CONFIG_VIDEO_IPUV3 |
e9934f0b SB |
189 | #define CONFIG_CFB_CONSOLE |
190 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
fca37fcd FE |
191 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
192 | #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE | |
e9934f0b | 193 | #define CONFIG_VIDEO_BMP_RLE8 |
a0152c4b SB |
194 | #define CONFIG_SPLASH_SCREEN |
195 | #define CONFIG_CMD_BMP | |
196 | #define CONFIG_BMP_16BPP | |
9fbdb1aa | 197 | #define CONFIG_IPUV3_CLK 133000000 |
a0152c4b | 198 | |
f8f8acd7 | 199 | #endif /* __CONFIG_H */ |