[thirdparty/u-boot.git] / include / configs / vme8349.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * esd vme8349 U-Boot configuration file
 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
 *
 * (C) Copyright 2006-2010
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * reinhard.arlt@esd-electronics.de
 * Based on the MPC8349EMDS config.
 */

/*
 * vme8349 board configuration file.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1	/* E300 Family */

/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
#undef CONFIG_MPC83XX_PCI2		/* support for 2nd PCI controller */

#undef CONFIG_SYS_DRAM_TEST			/* memory test, takes time */

/*
 * DDR Setup
 */
#define CONFIG_DDR_ECC			/* only for ECC DDR module */
#define CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
#define CONFIG_SPD_EEPROM
#define SPD_EEPROM_ADDRESS		0x54
#define CONFIG_SYS_READ_SPD		vme8349_read_spd
#define CONFIG_SYS_83XX_DDR_USES_CS0	/* esd; Fsl board uses CS2/CS3 */

/*
 * 32-bit data path mode.
 *
 * Please note that using this mode for devices with the real density of 64-bit
 * effectively reduces the amount of available memory due to the effect of
 * wrapping around while translating address to row/columns, for example in the
 * 256MB module the upper 128MB get aliased with contents of the lower
 * 128MB); normally this define should be used for devices with real 32-bit
 * data path.
 */
#undef CONFIG_DDR_32BIT

#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* DDR is sys memory*/
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
#define CONFIG_DDR_2T_TIMING
#define CONFIG_SYS_DDRCDR		(DDRCDR_DHC_EN \
					| DDRCDR_ODT \
					| DDRCDR_Q_DRN)
					/* 0x80080001 */

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_BASE		0xf8000000	/* start of FLASH   */
#define CONFIG_SYS_FLASH_SIZE		128		/* flash size in MB */


#define CONFIG_SYS_WINDOW1_BASE		0xf0000000


#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device*/

#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase TO (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write TO (ms) */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xF7000000	/* Initial RAM addr */
#define CONFIG_SYS_INIT_RAM_SIZE		0x1000		/* size */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB */
#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Malloc size */

#undef CONFIG_SYS_LB_SDRAM	/* if board has SDRAM on local bus */

/*
 * Serial Port
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_SYS_NS16550_COM1		(CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2		(CONFIG_SYS_IMMR + 0x4600)

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */

#define CONFIG_SYS_I2C_8574_ADDR2       0x20    /* I2C1, PCF8574 */

/* TSEC */
#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */

#define CONFIG_SYS_PCI2_MEM_BASE	0xA0000000
#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI2_MMIO_BASE	0xB0000000
#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI2_IO_BASE		0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS		0xE2100000
#define CONFIG_SYS_PCI2_IO_SIZE		0x00100000	/* 1M */

#if defined(CONFIG_PCI)

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
	#define PCI_ENET0_IOADDR	0xFIXME
	#define PCI_ENET0_MEMADDR	0xFIXME
	#define PCI_IDSEL_NUMBER	0xFIXME
#endif

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */

#endif	/* CONFIG_PCI */

/*
 * TSEC configuration
 */

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_GMII			/* MII PHY management */
#define CONFIG_TSEC1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2
#define CONFIG_TSEC2_NAME	"TSEC1"
#define CONFIG_PHY_M88E1111
#define TSEC1_PHY_ADDR		0x08
#define TSEC2_PHY_ADDR		0x10
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME		"TSEC0"

#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */
#ifndef CONFIG_SYS_RAMBOOT
/* Address and size of Redundant Environment Sector	*/
#endif

#define CONFIG_LOADS_ECHO		/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * Command line configuration.
 */
#define CONFIG_SYS_RTC_BUS_NUM  0x01
#define CONFIG_SYS_I2C_RTC_ADDR	0x32

/* Pass Ethernet MAC to VxWorks */
#define CONFIG_SYS_VXWORKS_MAC_PTR	0x000043f0

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Init Memory map for Linux*/

#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */

/* System IO Config */
#define CONFIG_SYS_SICRH 0
#define CONFIG_SYS_SICRL SICRL_LDP_A

#define CONFIG_SYS_GPIO1_PRELIM
#define CONFIG_SYS_GPIO1_DIR	0x00100000
#define CONFIG_SYS_GPIO1_DAT	0x00100000

#define CONFIG_SYS_GPIO2_PRELIM
#define CONFIG_SYS_GPIO2_DIR	0x78900000
#define CONFIG_SYS_GPIO2_DAT	0x70100000

#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#endif

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#endif

/*
 * Environment Configuration
 */
#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#endif

#define CONFIG_HOSTNAME		"VME8349"
#define CONFIG_ROOTPATH		"/tftpboot/rootfs"
#define CONFIG_BOOTFILE		"uImage"

#define CONFIG_LOADADDR		800000	/* def location for tftp and bootm */

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=vme8349\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
		"bootm\0"						\
	"load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0"		\
	"update=protect off fff00000 fff3ffff; "			\
		"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
	"upd=run load update\0"						\
	"fdtaddr=780000\0"						\
	"fdtfile=vme8349.dtb\0"						\
	""

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs root=/dev/nfs rw "				\
		"nfsroot=$serverip:$rootpath "				\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
							"$netdev:off "	\
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv bootargs root=/dev/ram rw "				\
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND	"run flash_self"

#ifndef __ASSEMBLY__
int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
		     unsigned char *buffer, int len);
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
c2e49f70 RA	2	/*
	3	* esd vme8349 U-Boot configuration file
	4	* Copyright (c) 2008, 2009 esd gmbh Hannover Germany
	5	*
2ae18241	6	* (C) Copyright 2006-2010
c2e49f70 RA	7	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	8	*
	9	* reinhard.arlt@esd-electronics.de
	10	* Based on the MPC8349EMDS config.
c2e49f70 RA	11	*/
	12
	13	/*
	14	* vme8349 board configuration file.
	15	*/
	16
	17	#ifndef __CONFIG_H
	18	#define __CONFIG_H
	19
	20	/*
	21	* High Level Configuration Options
	22	*/
	23	#define CONFIG_E300 1 /* E300 Family */
c2e49f70	24
c2e49f70 RA	25	/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
	26	#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
	27
c2e49f70	28	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
c2e49f70 RA	29
	30	/*
	31	* DDR Setup
	32	*/
	33	#define CONFIG_DDR_ECC /* only for ECC DDR module */
	34	#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
1dee9be6 RA	35	#define CONFIG_SPD_EEPROM
	36	#define SPD_EEPROM_ADDRESS 0x54
	37	#define CONFIG_SYS_READ_SPD vme8349_read_spd
c2e49f70 RA	38	#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
	39
	40	/*
	41	* 32-bit data path mode.
	42	*
	43	* Please note that using this mode for devices with the real density of 64-bit
	44	* effectively reduces the amount of available memory due to the effect of
	45	* wrapping around while translating address to row/columns, for example in the
	46	* 256MB module the upper 128MB get aliased with contents of the lower
	47	* 128MB); normally this define should be used for devices with real 32-bit
	48	* data path.
	49	*/
	50	#undef CONFIG_DDR_32BIT
	51
8a81bfd2	52	#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/
2fef4020 JH	53	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
2fef4020 JH	54	\| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
c2e49f70	55	#define CONFIG_DDR_2T_TIMING
2fef4020 JH	56	#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
	57	\| DDRCDR_ODT \
	58	\| DDRCDR_Q_DRN)
	59	/* 0x80080001 */
c2e49f70 RA	60
	61	/*
	62	* FLASH on the Local Bus
	63	*/
1dee9be6 RA	64	#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
1dee9be6 RA	65	#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
7d6a0982	66
c2e49f70	67
7d6a0982	68	#define CONFIG_SYS_WINDOW1_BASE 0xf0000000
a8f97539	69
c2e49f70 RA	70
	71	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	72	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
	73
	74	#undef CONFIG_SYS_FLASH_CHECKSUM
	75	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
	76	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
	77
c7357a2b	78	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
c2e49f70 RA	79
	80	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	81	#define CONFIG_SYS_RAMBOOT
	82	#else
1dee9be6	83	#undef CONFIG_SYS_RAMBOOT
c2e49f70 RA	84	#endif
	85
	86	#define CONFIG_SYS_INIT_RAM_LOCK 1
	87	#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
553f0982	88	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
c2e49f70	89
553f0982	90	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
25ddd1fb	91	GENERATED_GBL_DATA_SIZE)
c2e49f70 RA	92	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	93
	94	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
c8a90646	95	#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
c2e49f70	96
c2e49f70 RA	97	#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
	98
	99	/*
	100	* Serial Port
	101	*/
c2e49f70 RA	102	#define CONFIG_SYS_NS16550_SERIAL
	103	#define CONFIG_SYS_NS16550_REG_SIZE 1
	104	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	105
	106	#define CONFIG_SYS_BAUDRATE_TABLE \
c7357a2b	107	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
c2e49f70 RA	108
	109	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
	110	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
	111
c2e49f70	112	/* I2C */
00f792e0 HS	113	#define CONFIG_SYS_I2C
	114	#define CONFIG_SYS_I2C_FSL
	115	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	116	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	117	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	118	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	119	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	120	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
	121	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
efaf6f1b	122	/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
c2e49f70 RA	123
	124	#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
	125
	126	/* TSEC */
	127	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
	128	#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
	129	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
	130	#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
	131
	132	/*
	133	* General PCI
	134	* Addresses are mapped 1-1.
	135	*/
	136	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
	137	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	138	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
	139	#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
	140	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
	141	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
	142	#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
	143	#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
	144	#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
	145
	146	#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
	147	#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
	148	#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
	149	#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
	150	#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
	151	#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
	152	#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
	153	#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
	154	#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
	155
	156	#if defined(CONFIG_PCI)
	157
c2e49f70 RA	158	#undef CONFIG_EEPRO100
	159	#undef CONFIG_TULIP
	160
	161	#if !defined(CONFIG_PCI_PNP)
	162	#define PCI_ENET0_IOADDR 0xFIXME
	163	#define PCI_ENET0_MEMADDR 0xFIXME
	164	#define PCI_IDSEL_NUMBER 0xFIXME
	165	#endif
	166
1dee9be6 RA	167	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	168	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
	169
c2e49f70 RA	170	#endif /* CONFIG_PCI */
	171
	172	/*
	173	* TSEC configuration
	174	*/
c2e49f70 RA	175
c2e49f70 RA	176	#if defined(CONFIG_TSEC_ENET)
c2e49f70	177
1dee9be6	178	#define CONFIG_GMII /* MII PHY management */
c2e49f70 RA	179	#define CONFIG_TSEC1
	180	#define CONFIG_TSEC1_NAME "TSEC0"
	181	#define CONFIG_TSEC2
	182	#define CONFIG_TSEC2_NAME "TSEC1"
	183	#define CONFIG_PHY_M88E1111
	184	#define TSEC1_PHY_ADDR 0x08
	185	#define TSEC2_PHY_ADDR 0x10
	186	#define TSEC1_PHYIDX 0
	187	#define TSEC2_PHYIDX 0
	188	#define TSEC1_FLAGS TSEC_GIGABIT
	189	#define TSEC2_FLAGS TSEC_GIGABIT
	190
	191	/* Options are: TSEC[0-1] */
	192	#define CONFIG_ETHPRIME "TSEC0"
	193
	194	#endif /* CONFIG_TSEC_ENET */
	195
	196	/*
	197	* Environment
	198	*/
	199	#ifndef CONFIG_SYS_RAMBOOT
c2e49f70	200	/* Address and size of Redundant Environment Sector */
c2e49f70 RA	201	#endif
	202
	203	#define CONFIG_LOADS_ECHO /* echo on for serial download */
	204	#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
	205
	206	/*
	207	* BOOTP options
	208	*/
	209	#define CONFIG_BOOTP_BOOTFILESIZE
c2e49f70 RA	210
	211	/*
	212	* Command line configuration.
	213	*/
c2e49f70 RA	214	#define CONFIG_SYS_RTC_BUS_NUM 0x01
c2e49f70 RA	215	#define CONFIG_SYS_I2C_RTC_ADDR 0x32
c2e49f70	216
c2e49f70 RA	217	/* Pass Ethernet MAC to VxWorks */
	218	#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
	219
	220	#undef CONFIG_WATCHDOG /* watchdog disabled */
	221
	222	/*
	223	* Miscellaneous configurable options
	224	*/
c2e49f70	225	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
c2e49f70	226
c2e49f70 RA	227	/*
c2e49f70 RA	228	* For booting Linux, the board info and command line data
9f530d59	229	* have to be in the first 256 MB of memory, since this is
c2e49f70 RA	230	* the maximum mapped by the Linux kernel during initialization.
c2e49f70 RA	231	*/
9f530d59	232	#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
c2e49f70 RA	233
	234	#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
	235
c2e49f70 RA	236	/* System IO Config */
	237	#define CONFIG_SYS_SICRH 0
	238	#define CONFIG_SYS_SICRL SICRL_LDP_A
	239
c2e49f70 RA	240	#define CONFIG_SYS_GPIO1_PRELIM
	241	#define CONFIG_SYS_GPIO1_DIR 0x00100000
	242	#define CONFIG_SYS_GPIO1_DAT 0x00100000
	243
	244	#define CONFIG_SYS_GPIO2_PRELIM
	245	#define CONFIG_SYS_GPIO2_DIR 0x78900000
	246	#define CONFIG_SYS_GPIO2_DAT 0x70100000
	247
c2e49f70	248	#ifdef CONFIG_PCI
842033e6	249	#define CONFIG_PCI_INDIRECT_BRIDGE
c2e49f70 RA	250	#endif
c2e49f70 RA	251
c2e49f70 RA	252	#if defined(CONFIG_CMD_KGDB)
c2e49f70 RA	253	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
c2e49f70 RA	254	#endif
	255
	256	/*
	257	* Environment Configuration
	258	*/
	259	#define CONFIG_ENV_OVERWRITE
	260
	261	#if defined(CONFIG_TSEC_ENET)
	262	#define CONFIG_HAS_ETH0
	263	#define CONFIG_HAS_ETH1
	264	#endif
	265
5bc0543d	266	#define CONFIG_HOSTNAME "VME8349"
8b3637c6	267	#define CONFIG_ROOTPATH "/tftpboot/rootfs"
b3f44c21	268	#define CONFIG_BOOTFILE "uImage"
c2e49f70	269
79f516bc	270	#define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
c2e49f70	271
c2e49f70 RA	272	#define CONFIG_EXTRA_ENV_SETTINGS \
	273	"netdev=eth0\0" \
	274	"hostname=vme8349\0" \
	275	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	276	"nfsroot=${serverip}:${rootpath}\0" \
	277	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	278	"addip=setenv bootargs ${bootargs} " \
	279	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	280	":${hostname}:${netdev}:off panic=1\0" \
	281	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	282	"flash_nfs=run nfsargs addip addtty;" \
	283	"bootm ${kernel_addr}\0" \
	284	"flash_self=run ramargs addip addtty;" \
	285	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	286	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
	287	"bootm\0" \
	288	"load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
	289	"update=protect off fff00000 fff3ffff; " \
	290	"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
	291	"upd=run load update\0" \
79f516bc	292	"fdtaddr=780000\0" \
c2e49f70 RA	293	"fdtfile=vme8349.dtb\0" \
	294	""
	295
c7357a2b JH	296	#define CONFIG_NFSBOOTCOMMAND \
	297	"setenv bootargs root=/dev/nfs rw " \
	298	"nfsroot=$serverip:$rootpath " \
	299	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
	300	"$netdev:off " \
	301	"console=$consoledev,$baudrate $othbootargs;" \
	302	"tftp $loadaddr $bootfile;" \
	303	"tftp $fdtaddr $fdtfile;" \
	304	"bootm $loadaddr - $fdtaddr"
c2e49f70 RA	305
c2e49f70 RA	306	#define CONFIG_RAMBOOTCOMMAND \
c7357a2b JH	307	"setenv bootargs root=/dev/ram rw " \
	308	"console=$consoledev,$baudrate $othbootargs;" \
	309	"tftp $ramdiskaddr $ramdiskfile;" \
	310	"tftp $loadaddr $bootfile;" \
	311	"tftp $fdtaddr $fdtfile;" \
	312	"bootm $loadaddr $ramdiskaddr $fdtaddr"
c2e49f70 RA	313
	314	#define CONFIG_BOOTCOMMAND "run flash_self"
	315
1dee9be6 RA	316	#ifndef __ASSEMBLY__
	317	int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
	318	unsigned char *buffer, int len);
	319	#endif
	320
c2e49f70	321	#endif /* __CONFIG_H */