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c2e49f70 RA |
1 | /* |
2 | * esd vme8349 U-Boot configuration file | |
3 | * Copyright (c) 2008, 2009 esd gmbh Hannover Germany | |
4 | * | |
2ae18241 | 5 | * (C) Copyright 2006-2010 |
c2e49f70 RA |
6 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
7 | * | |
8 | * reinhard.arlt@esd-electronics.de | |
9 | * Based on the MPC8349EMDS config. | |
10 | * | |
3765b3e7 | 11 | * SPDX-License-Identifier: GPL-2.0+ |
c2e49f70 RA |
12 | */ |
13 | ||
14 | /* | |
15 | * vme8349 board configuration file. | |
16 | */ | |
17 | ||
18 | #ifndef __CONFIG_H | |
19 | #define __CONFIG_H | |
20 | ||
fdfaa29e KP |
21 | #define CONFIG_DISPLAY_BOARDINFO |
22 | ||
1dee9be6 RA |
23 | /* |
24 | * Top level Makefile configuration choices | |
25 | */ | |
2ae18241 | 26 | #ifdef CONFIG_CADDY2 |
1dee9be6 RA |
27 | #define VME_CADDY2 |
28 | #endif | |
29 | ||
c2e49f70 RA |
30 | /* |
31 | * High Level Configuration Options | |
32 | */ | |
33 | #define CONFIG_E300 1 /* E300 Family */ | |
c2e49f70 RA |
34 | #define CONFIG_MPC834x 1 /* MPC834x family */ |
35 | #define CONFIG_MPC8349 1 /* MPC8349 specific */ | |
36 | #define CONFIG_VME8349 1 /* ESD VME8349 board specific */ | |
37 | ||
2ae18241 WD |
38 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
39 | ||
1dee9be6 RA |
40 | #define CONFIG_MISC_INIT_R |
41 | ||
c2e49f70 RA |
42 | #define CONFIG_PCI |
43 | /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ | |
44 | #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ | |
45 | ||
2ae18241 WD |
46 | #define CONFIG_PCI_66M |
47 | #ifdef CONFIG_PCI_66M | |
c2e49f70 RA |
48 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ |
49 | #else | |
50 | #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ | |
51 | #endif | |
52 | ||
53 | #ifndef CONFIG_SYS_CLK_FREQ | |
2ae18241 | 54 | #ifdef CONFIG_PCI_66M |
c2e49f70 RA |
55 | #define CONFIG_SYS_CLK_FREQ 66000000 |
56 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 | |
57 | #else | |
58 | #define CONFIG_SYS_CLK_FREQ 33000000 | |
59 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 | |
60 | #endif | |
61 | #endif | |
62 | ||
63 | #define CONFIG_SYS_IMMR 0xE0000000 | |
64 | ||
65 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ | |
66 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ | |
67 | #define CONFIG_SYS_MEMTEST_END 0x00100000 | |
68 | ||
69 | /* | |
70 | * DDR Setup | |
71 | */ | |
72 | #define CONFIG_DDR_ECC /* only for ECC DDR module */ | |
73 | #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ | |
1dee9be6 RA |
74 | #define CONFIG_SPD_EEPROM |
75 | #define SPD_EEPROM_ADDRESS 0x54 | |
76 | #define CONFIG_SYS_READ_SPD vme8349_read_spd | |
c2e49f70 RA |
77 | #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ |
78 | ||
79 | /* | |
80 | * 32-bit data path mode. | |
81 | * | |
82 | * Please note that using this mode for devices with the real density of 64-bit | |
83 | * effectively reduces the amount of available memory due to the effect of | |
84 | * wrapping around while translating address to row/columns, for example in the | |
85 | * 256MB module the upper 128MB get aliased with contents of the lower | |
86 | * 128MB); normally this define should be used for devices with real 32-bit | |
87 | * data path. | |
88 | */ | |
89 | #undef CONFIG_DDR_32BIT | |
90 | ||
91 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ | |
92 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
93 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
2fef4020 JH |
94 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ |
95 | | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) | |
c2e49f70 | 96 | #define CONFIG_DDR_2T_TIMING |
2fef4020 JH |
97 | #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \ |
98 | | DDRCDR_ODT \ | |
99 | | DDRCDR_Q_DRN) | |
100 | /* 0x80080001 */ | |
c2e49f70 RA |
101 | |
102 | /* | |
103 | * FLASH on the Local Bus | |
104 | */ | |
105 | #define CONFIG_SYS_FLASH_CFI | |
106 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
1dee9be6 RA |
107 | #ifdef VME_CADDY2 |
108 | #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ | |
109 | #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ | |
110 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ | |
7d6a0982 JH |
111 | BR_PS_16 | /* 16bit */ \ |
112 | BR_MS_GPCM | /* MSEL = GPCM */ \ | |
113 | BR_V) /* valid */ | |
114 | ||
115 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
116 | | OR_GPCM_XAM \ | |
117 | | OR_GPCM_CSNT \ | |
118 | | OR_GPCM_ACS_DIV2 \ | |
119 | | OR_GPCM_XACS \ | |
120 | | OR_GPCM_SCY_15 \ | |
121 | | OR_GPCM_TRLX_SET \ | |
122 | | OR_GPCM_EHTR_SET \ | |
123 | | OR_GPCM_EAD) | |
124 | /* 0xffc06ff7 */ | |
1dee9be6 | 125 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE |
7d6a0982 | 126 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB) |
1dee9be6 RA |
127 | #else |
128 | #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ | |
129 | #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ | |
c2e49f70 | 130 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ |
7d6a0982 JH |
131 | BR_PS_16 | /* 16bit */ \ |
132 | BR_MS_GPCM | /* MSEL = GPCM */ \ | |
133 | BR_V) /* valid */ | |
134 | ||
135 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
136 | | OR_GPCM_XAM \ | |
137 | | OR_GPCM_CSNT \ | |
138 | | OR_GPCM_ACS_DIV2 \ | |
139 | | OR_GPCM_XACS \ | |
140 | | OR_GPCM_SCY_15 \ | |
141 | | OR_GPCM_TRLX_SET \ | |
142 | | OR_GPCM_EHTR_SET \ | |
143 | | OR_GPCM_EAD) | |
144 | /* 0xf8006ff7 */ | |
c2e49f70 | 145 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE |
7d6a0982 | 146 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) |
1dee9be6 RA |
147 | #endif |
148 | /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ | |
c2e49f70 | 149 | |
7d6a0982 JH |
150 | #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 |
151 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ | |
152 | | BR_PS_32 \ | |
153 | | BR_MS_GPCM \ | |
154 | | BR_V) | |
155 | /* 0xF0001801 */ | |
156 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \ | |
157 | | OR_GPCM_SETA) | |
158 | /* 0xfffc0208 */ | |
159 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE | |
160 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB) | |
c2e49f70 RA |
161 | |
162 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
163 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ | |
164 | ||
165 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
166 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */ | |
167 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */ | |
168 | ||
c7357a2b | 169 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
c2e49f70 RA |
170 | |
171 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) | |
172 | #define CONFIG_SYS_RAMBOOT | |
173 | #else | |
1dee9be6 | 174 | #undef CONFIG_SYS_RAMBOOT |
c2e49f70 RA |
175 | #endif |
176 | ||
177 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
178 | #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */ | |
553f0982 | 179 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */ |
c2e49f70 | 180 | |
553f0982 | 181 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
25ddd1fb | 182 | GENERATED_GBL_DATA_SIZE) |
c2e49f70 RA |
183 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
184 | ||
185 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ | |
c8a90646 | 186 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ |
c2e49f70 RA |
187 | |
188 | /* | |
189 | * Local Bus LCRR and LBCR regs | |
1dee9be6 | 190 | * LCRR: no DLL bypass, Clock divider is 4 |
c2e49f70 RA |
191 | * External Local Bus rate is |
192 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
193 | */ | |
c7190f02 | 194 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 |
c2e49f70 RA |
195 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
196 | ||
197 | #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ | |
198 | ||
199 | /* | |
200 | * Serial Port | |
201 | */ | |
202 | #define CONFIG_CONS_INDEX 1 | |
c2e49f70 RA |
203 | #define CONFIG_SYS_NS16550_SERIAL |
204 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
205 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
206 | ||
207 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
c7357a2b | 208 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
c2e49f70 RA |
209 | |
210 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) | |
211 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) | |
212 | ||
213 | #define CONFIG_CMDLINE_EDITING /* add command line history */ | |
a059e90e | 214 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
c2e49f70 | 215 | |
c2e49f70 | 216 | /* I2C */ |
00f792e0 HS |
217 | #define CONFIG_SYS_I2C |
218 | #define CONFIG_SYS_I2C_FSL | |
219 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
220 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
221 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
222 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
223 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
224 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
225 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
efaf6f1b | 226 | /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ |
c2e49f70 RA |
227 | |
228 | #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ | |
229 | ||
230 | /* TSEC */ | |
231 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 | |
232 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) | |
233 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 | |
234 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) | |
235 | ||
236 | /* | |
237 | * General PCI | |
238 | * Addresses are mapped 1-1. | |
239 | */ | |
240 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 | |
241 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
242 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
243 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
244 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
245 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
246 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 | |
247 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
248 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
249 | ||
250 | #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 | |
251 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE | |
252 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
253 | #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 | |
254 | #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE | |
255 | #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ | |
256 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 | |
257 | #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 | |
258 | #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ | |
259 | ||
260 | #if defined(CONFIG_PCI) | |
261 | ||
262 | #define PCI_64BIT | |
263 | #define PCI_ONE_PCI1 | |
264 | #if defined(PCI_64BIT) | |
265 | #undef PCI_ALL_PCI1 | |
266 | #undef PCI_TWO_PCI1 | |
267 | #undef PCI_ONE_PCI1 | |
268 | #endif | |
269 | ||
1dee9be6 | 270 | #ifndef VME_CADDY2 |
1dee9be6 RA |
271 | #endif |
272 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
c2e49f70 RA |
273 | |
274 | #undef CONFIG_EEPRO100 | |
275 | #undef CONFIG_TULIP | |
276 | ||
277 | #if !defined(CONFIG_PCI_PNP) | |
278 | #define PCI_ENET0_IOADDR 0xFIXME | |
279 | #define PCI_ENET0_MEMADDR 0xFIXME | |
280 | #define PCI_IDSEL_NUMBER 0xFIXME | |
281 | #endif | |
282 | ||
1dee9be6 RA |
283 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
284 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ | |
285 | ||
c2e49f70 RA |
286 | #endif /* CONFIG_PCI */ |
287 | ||
288 | /* | |
289 | * TSEC configuration | |
290 | */ | |
1dee9be6 | 291 | #ifdef VME_CADDY2 |
1dee9be6 | 292 | #else |
c2e49f70 | 293 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ |
1dee9be6 | 294 | #endif |
c2e49f70 RA |
295 | |
296 | #if defined(CONFIG_TSEC_ENET) | |
c2e49f70 | 297 | |
1dee9be6 | 298 | #define CONFIG_GMII /* MII PHY management */ |
c2e49f70 RA |
299 | #define CONFIG_TSEC1 |
300 | #define CONFIG_TSEC1_NAME "TSEC0" | |
301 | #define CONFIG_TSEC2 | |
302 | #define CONFIG_TSEC2_NAME "TSEC1" | |
303 | #define CONFIG_PHY_M88E1111 | |
304 | #define TSEC1_PHY_ADDR 0x08 | |
305 | #define TSEC2_PHY_ADDR 0x10 | |
306 | #define TSEC1_PHYIDX 0 | |
307 | #define TSEC2_PHYIDX 0 | |
308 | #define TSEC1_FLAGS TSEC_GIGABIT | |
309 | #define TSEC2_FLAGS TSEC_GIGABIT | |
310 | ||
311 | /* Options are: TSEC[0-1] */ | |
312 | #define CONFIG_ETHPRIME "TSEC0" | |
313 | ||
314 | #endif /* CONFIG_TSEC_ENET */ | |
315 | ||
316 | /* | |
317 | * Environment | |
318 | */ | |
319 | #ifndef CONFIG_SYS_RAMBOOT | |
320 | #define CONFIG_ENV_IS_IN_FLASH | |
321 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000) | |
322 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ | |
323 | #define CONFIG_ENV_SIZE 0x2000 | |
324 | ||
325 | /* Address and size of Redundant Environment Sector */ | |
326 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) | |
327 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
328 | ||
329 | #else | |
330 | #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ | |
331 | #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ | |
332 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) | |
333 | #define CONFIG_ENV_SIZE 0x2000 | |
334 | #endif | |
335 | ||
336 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
337 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
338 | ||
339 | /* | |
340 | * BOOTP options | |
341 | */ | |
342 | #define CONFIG_BOOTP_BOOTFILESIZE | |
343 | #define CONFIG_BOOTP_BOOTPATH | |
344 | #define CONFIG_BOOTP_GATEWAY | |
345 | #define CONFIG_BOOTP_HOSTNAME | |
346 | ||
347 | /* | |
348 | * Command line configuration. | |
349 | */ | |
c2e49f70 | 350 | #define CONFIG_CMD_MII |
c2e49f70 RA |
351 | #define CONFIG_CMD_DATE |
352 | #define CONFIG_SYS_RTC_BUS_NUM 0x01 | |
353 | #define CONFIG_SYS_I2C_RTC_ADDR 0x32 | |
354 | #define CONFIG_RTC_RX8025 | |
355 | #define CONFIG_CMD_TSI148 | |
356 | ||
357 | #if defined(CONFIG_PCI) | |
358 | #define CONFIG_CMD_PCI | |
359 | #endif | |
360 | ||
361 | #if defined(CONFIG_SYS_RAMBOOT) | |
362 | #undef CONFIG_CMD_ENV | |
c2e49f70 RA |
363 | #endif |
364 | ||
c2e49f70 RA |
365 | /* Pass Ethernet MAC to VxWorks */ |
366 | #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 | |
367 | ||
368 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
369 | ||
370 | /* | |
371 | * Miscellaneous configurable options | |
372 | */ | |
373 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
374 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
c2e49f70 RA |
375 | |
376 | #if defined(CONFIG_CMD_KGDB) | |
377 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
378 | #else | |
379 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
380 | #endif | |
381 | ||
382 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
383 | #define CONFIG_SYS_MAXARGS 16 /* max num of command args */ | |
384 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */ | |
c2e49f70 RA |
385 | |
386 | /* | |
387 | * For booting Linux, the board info and command line data | |
9f530d59 | 388 | * have to be in the first 256 MB of memory, since this is |
c2e49f70 RA |
389 | * the maximum mapped by the Linux kernel during initialization. |
390 | */ | |
9f530d59 | 391 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/ |
c2e49f70 RA |
392 | |
393 | #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ | |
394 | ||
395 | #define CONFIG_SYS_HRCW_LOW (\ | |
396 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
397 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
398 | HRCWL_CSB_TO_CLKIN |\ | |
399 | HRCWL_VCO_1X2 |\ | |
400 | HRCWL_CORE_TO_CSB_2X1) | |
401 | ||
402 | #if defined(PCI_64BIT) | |
403 | #define CONFIG_SYS_HRCW_HIGH (\ | |
404 | HRCWH_PCI_HOST |\ | |
405 | HRCWH_64_BIT_PCI |\ | |
406 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
407 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
408 | HRCWH_CORE_ENABLE |\ | |
409 | HRCWH_FROM_0X00000100 |\ | |
410 | HRCWH_BOOTSEQ_DISABLE |\ | |
411 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
412 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
413 | HRCWH_TSEC1M_IN_GMII |\ | |
414 | HRCWH_TSEC2M_IN_GMII) | |
415 | #else | |
416 | #define CONFIG_SYS_HRCW_HIGH (\ | |
417 | HRCWH_PCI_HOST |\ | |
418 | HRCWH_32_BIT_PCI |\ | |
419 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
420 | HRCWH_PCI2_ARBITER_ENABLE |\ | |
421 | HRCWH_CORE_ENABLE |\ | |
422 | HRCWH_FROM_0X00000100 |\ | |
423 | HRCWH_BOOTSEQ_DISABLE |\ | |
424 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
425 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
426 | HRCWH_TSEC1M_IN_GMII |\ | |
427 | HRCWH_TSEC2M_IN_GMII) | |
428 | #endif | |
429 | ||
430 | /* System IO Config */ | |
431 | #define CONFIG_SYS_SICRH 0 | |
432 | #define CONFIG_SYS_SICRL SICRL_LDP_A | |
433 | ||
434 | #define CONFIG_SYS_HID0_INIT 0x000000000 | |
1a2e203b KP |
435 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ |
436 | HID0_ENABLE_INSTRUCTION_CACHE) | |
c2e49f70 RA |
437 | |
438 | #define CONFIG_SYS_HID2 HID2_HBE | |
439 | ||
440 | #define CONFIG_SYS_GPIO1_PRELIM | |
441 | #define CONFIG_SYS_GPIO1_DIR 0x00100000 | |
442 | #define CONFIG_SYS_GPIO1_DAT 0x00100000 | |
443 | ||
444 | #define CONFIG_SYS_GPIO2_PRELIM | |
445 | #define CONFIG_SYS_GPIO2_DIR 0x78900000 | |
446 | #define CONFIG_SYS_GPIO2_DAT 0x70100000 | |
447 | ||
448 | #define CONFIG_HIGH_BATS /* High BATs supported */ | |
449 | ||
450 | /* DDR @ 0x00000000 */ | |
72cd4087 | 451 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ |
c2e49f70 RA |
452 | BATL_MEMCOHERENCE) |
453 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ | |
454 | BATU_VS | BATU_VP) | |
455 | ||
456 | /* PCI @ 0x80000000 */ | |
457 | #ifdef CONFIG_PCI | |
842033e6 | 458 | #define CONFIG_PCI_INDIRECT_BRIDGE |
72cd4087 | 459 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \ |
c2e49f70 RA |
460 | BATL_MEMCOHERENCE) |
461 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ | |
462 | BATU_VS | BATU_VP) | |
72cd4087 | 463 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \ |
c2e49f70 RA |
464 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
465 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ | |
466 | BATU_VS | BATU_VP) | |
467 | #else | |
468 | #define CONFIG_SYS_IBAT1L (0) | |
469 | #define CONFIG_SYS_IBAT1U (0) | |
470 | #define CONFIG_SYS_IBAT2L (0) | |
471 | #define CONFIG_SYS_IBAT2U (0) | |
472 | #endif | |
473 | ||
474 | #ifdef CONFIG_MPC83XX_PCI2 | |
72cd4087 | 475 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \ |
c2e49f70 RA |
476 | BATL_MEMCOHERENCE) |
477 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \ | |
478 | BATU_VS | BATU_VP) | |
72cd4087 | 479 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \ |
c2e49f70 RA |
480 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
481 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \ | |
482 | BATU_VS | BATU_VP) | |
483 | #else | |
484 | #define CONFIG_SYS_IBAT3L (0) | |
485 | #define CONFIG_SYS_IBAT3U (0) | |
486 | #define CONFIG_SYS_IBAT4L (0) | |
487 | #define CONFIG_SYS_IBAT4U (0) | |
488 | #endif | |
489 | ||
490 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ | |
72cd4087 | 491 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \ |
c2e49f70 RA |
492 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
493 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \ | |
494 | BATU_VS | BATU_VP) | |
495 | ||
72cd4087 | 496 | #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE) |
c2e49f70 RA |
497 | #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
498 | ||
499 | #if (CONFIG_SYS_DDR_SIZE == 512) | |
500 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ | |
72cd4087 | 501 | BATL_PP_RW | BATL_MEMCOHERENCE) |
c2e49f70 RA |
502 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ |
503 | BATU_BL_256M | BATU_VS | BATU_VP) | |
504 | #else | |
505 | #define CONFIG_SYS_IBAT7L (0) | |
506 | #define CONFIG_SYS_IBAT7U (0) | |
507 | #endif | |
508 | ||
509 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
510 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
511 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
512 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
513 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
514 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
515 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
516 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
517 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
518 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
519 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
520 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
521 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
522 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
523 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
524 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
525 | ||
c2e49f70 RA |
526 | #if defined(CONFIG_CMD_KGDB) |
527 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
c2e49f70 RA |
528 | #endif |
529 | ||
530 | /* | |
531 | * Environment Configuration | |
532 | */ | |
533 | #define CONFIG_ENV_OVERWRITE | |
534 | ||
535 | #if defined(CONFIG_TSEC_ENET) | |
536 | #define CONFIG_HAS_ETH0 | |
537 | #define CONFIG_HAS_ETH1 | |
538 | #endif | |
539 | ||
540 | #define CONFIG_HOSTNAME VME8349 | |
8b3637c6 | 541 | #define CONFIG_ROOTPATH "/tftpboot/rootfs" |
b3f44c21 | 542 | #define CONFIG_BOOTFILE "uImage" |
c2e49f70 | 543 | |
79f516bc | 544 | #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ |
c2e49f70 RA |
545 | |
546 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ | |
547 | #undef CONFIG_BOOTARGS /* boot command will set bootargs */ | |
548 | ||
1dee9be6 | 549 | #define CONFIG_BAUDRATE 9600 |
c2e49f70 RA |
550 | |
551 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
552 | "netdev=eth0\0" \ | |
553 | "hostname=vme8349\0" \ | |
554 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
555 | "nfsroot=${serverip}:${rootpath}\0" \ | |
556 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
557 | "addip=setenv bootargs ${bootargs} " \ | |
558 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
559 | ":${hostname}:${netdev}:off panic=1\0" \ | |
560 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
561 | "flash_nfs=run nfsargs addip addtty;" \ | |
562 | "bootm ${kernel_addr}\0" \ | |
563 | "flash_self=run ramargs addip addtty;" \ | |
564 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
565 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
566 | "bootm\0" \ | |
567 | "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \ | |
568 | "update=protect off fff00000 fff3ffff; " \ | |
569 | "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ | |
570 | "upd=run load update\0" \ | |
79f516bc | 571 | "fdtaddr=780000\0" \ |
c2e49f70 RA |
572 | "fdtfile=vme8349.dtb\0" \ |
573 | "" | |
574 | ||
c7357a2b JH |
575 | #define CONFIG_NFSBOOTCOMMAND \ |
576 | "setenv bootargs root=/dev/nfs rw " \ | |
577 | "nfsroot=$serverip:$rootpath " \ | |
578 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ | |
579 | "$netdev:off " \ | |
580 | "console=$consoledev,$baudrate $othbootargs;" \ | |
581 | "tftp $loadaddr $bootfile;" \ | |
582 | "tftp $fdtaddr $fdtfile;" \ | |
583 | "bootm $loadaddr - $fdtaddr" | |
c2e49f70 RA |
584 | |
585 | #define CONFIG_RAMBOOTCOMMAND \ | |
c7357a2b JH |
586 | "setenv bootargs root=/dev/ram rw " \ |
587 | "console=$consoledev,$baudrate $othbootargs;" \ | |
588 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
589 | "tftp $loadaddr $bootfile;" \ | |
590 | "tftp $fdtaddr $fdtfile;" \ | |
591 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
c2e49f70 RA |
592 | |
593 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
594 | ||
1dee9be6 RA |
595 | #ifndef __ASSEMBLY__ |
596 | int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, | |
597 | unsigned char *buffer, int len); | |
598 | #endif | |
599 | ||
c2e49f70 | 600 | #endif /* __CONFIG_H */ |