[thirdparty/u-boot.git] / include / configs / vme8349.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * esd vme8349 U-Boot configuration file
 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
 *
 * (C) Copyright 2006-2010
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * reinhard.arlt@esd-electronics.de
 * Based on the MPC8349EMDS config.
 */

/*
 * vme8349 board configuration file.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * Top level Makefile configuration choices
 */
#ifdef CONFIG_CADDY2
#define VME_CADDY2
#endif

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1	/* E300 Family */
#define CONFIG_MPC834x		1	/* MPC834x family */
#define CONFIG_MPC8349		1	/* MPC8349 specific */
#define CONFIG_VME8349		1	/* ESD VME8349 board specific */

#define CONFIG_MISC_INIT_R

/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
#undef CONFIG_MPC83XX_PCI2		/* support for 2nd PCI controller */

#define CONFIG_PCI_66M
#ifdef CONFIG_PCI_66M
#define CONFIG_83XX_CLKIN	66000000	/* in Hz */
#else
#define CONFIG_83XX_CLKIN	33000000	/* in Hz */
#endif

#ifndef CONFIG_SYS_CLK_FREQ
#ifdef CONFIG_PCI_66M
#define CONFIG_SYS_CLK_FREQ	66000000
#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_4X1
#else
#define CONFIG_SYS_CLK_FREQ	33000000
#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_8X1
#endif
#endif

#define CONFIG_SYS_IMMR		0xE0000000

#undef CONFIG_SYS_DRAM_TEST			/* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x00100000

/*
 * DDR Setup
 */
#define CONFIG_DDR_ECC			/* only for ECC DDR module */
#define CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
#define CONFIG_SPD_EEPROM
#define SPD_EEPROM_ADDRESS		0x54
#define CONFIG_SYS_READ_SPD		vme8349_read_spd
#define CONFIG_SYS_83XX_DDR_USES_CS0	/* esd; Fsl board uses CS2/CS3 */

/*
 * 32-bit data path mode.
 *
 * Please note that using this mode for devices with the real density of 64-bit
 * effectively reduces the amount of available memory due to the effect of
 * wrapping around while translating address to row/columns, for example in the
 * 256MB module the upper 128MB get aliased with contents of the lower
 * 128MB); normally this define should be used for devices with real 32-bit
 * data path.
 */
#undef CONFIG_DDR_32BIT

#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is sys memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
#define CONFIG_DDR_2T_TIMING
#define CONFIG_SYS_DDRCDR		(DDRCDR_DHC_EN \
					| DDRCDR_ODT \
					| DDRCDR_Q_DRN)
					/* 0x80080001 */

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER			        /* use the CFI driver */
#ifdef VME_CADDY2
#define CONFIG_SYS_FLASH_BASE		0xffc00000	/* start of FLASH   */
#define CONFIG_SYS_FLASH_SIZE		4		/* flash size in MB */
#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | \
					 BR_PS_16 |	/*  16bit */ \
					 BR_MS_GPCM |	/*  MSEL = GPCM */ \
					 BR_V)		/* valid */

#define CONFIG_SYS_OR0_PRELIM		(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
					| OR_GPCM_XAM \
					| OR_GPCM_CSNT \
					| OR_GPCM_ACS_DIV2 \
					| OR_GPCM_XACS \
					| OR_GPCM_SCY_15 \
					| OR_GPCM_TRLX_SET \
					| OR_GPCM_EHTR_SET \
					| OR_GPCM_EAD)
					/* 0xffc06ff7 */
#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_4MB)
#else
#define CONFIG_SYS_FLASH_BASE		0xf8000000	/* start of FLASH   */
#define CONFIG_SYS_FLASH_SIZE		128		/* flash size in MB */
#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | \
					 BR_PS_16 |	/*  16bit */ \
					 BR_MS_GPCM |	/*  MSEL = GPCM */ \
					 BR_V)		/* valid */

#define CONFIG_SYS_OR0_PRELIM		(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
					| OR_GPCM_XAM \
					| OR_GPCM_CSNT \
					| OR_GPCM_ACS_DIV2 \
					| OR_GPCM_XACS \
					| OR_GPCM_SCY_15 \
					| OR_GPCM_TRLX_SET \
					| OR_GPCM_EHTR_SET \
					| OR_GPCM_EAD)
					/* 0xf8006ff7 */
#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_128MB)
#endif
/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */

#define CONFIG_SYS_WINDOW1_BASE		0xf0000000
#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_WINDOW1_BASE \
					| BR_PS_32 \
					| BR_MS_GPCM \
					| BR_V)
					/* 0xF0001801 */
#define CONFIG_SYS_OR1_PRELIM		(OR_AM_256KB \
					| OR_GPCM_SETA)
					/* 0xfffc0208 */
#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_WINDOW1_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_256KB)

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device*/

#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase TO (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write TO (ms) */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xF7000000	/* Initial RAM addr */
#define CONFIG_SYS_INIT_RAM_SIZE		0x1000		/* size */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB */
#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Malloc size */

/*
 * Local Bus LCRR and LBCR regs
 *    LCRR:  no DLL bypass, Clock divider is 4
 * External Local Bus rate is
 *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 */
#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR	0x00000000

#undef CONFIG_SYS_LB_SDRAM	/* if board has SDRAM on local bus */

/*
 * Serial Port
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_SYS_NS16550_COM1		(CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2		(CONFIG_SYS_IMMR + 0x4600)

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */

#define CONFIG_SYS_I2C_8574_ADDR2       0x20    /* I2C1, PCF8574 */

/* TSEC */
#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */

#define CONFIG_SYS_PCI2_MEM_BASE	0xA0000000
#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI2_MMIO_BASE	0xB0000000
#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI2_IO_BASE		0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS		0xE2100000
#define CONFIG_SYS_PCI2_IO_SIZE		0x00100000	/* 1M */

#if defined(CONFIG_PCI)

#define PCI_64BIT
#define PCI_ONE_PCI1
#if defined(PCI_64BIT)
#undef PCI_ALL_PCI1
#undef PCI_TWO_PCI1
#undef PCI_ONE_PCI1
#endif

#ifndef VME_CADDY2
#endif

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
	#define PCI_ENET0_IOADDR	0xFIXME
	#define PCI_ENET0_MEMADDR	0xFIXME
	#define PCI_IDSEL_NUMBER	0xFIXME
#endif

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */

#endif	/* CONFIG_PCI */

/*
 * TSEC configuration
 */

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_GMII			/* MII PHY management */
#define CONFIG_TSEC1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2
#define CONFIG_TSEC2_NAME	"TSEC1"
#define CONFIG_PHY_M88E1111
#define TSEC1_PHY_ADDR		0x08
#define TSEC2_PHY_ADDR		0x10
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME		"TSEC0"

#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */
#ifndef CONFIG_SYS_RAMBOOT
	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0xc0000)
	#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
	#define CONFIG_ENV_SIZE		0x2000

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

#else
	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
	#define CONFIG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO		/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * Command line configuration.
 */
#define CONFIG_SYS_RTC_BUS_NUM  0x01
#define CONFIG_SYS_I2C_RTC_ADDR	0x32
#define CONFIG_RTC_RX8025

/* Pass Ethernet MAC to VxWorks */
#define CONFIG_SYS_VXWORKS_MAC_PTR	0x000043f0

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Init Memory map for Linux*/

#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */

#define CONFIG_SYS_HRCW_LOW (\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_1X1 |\
	HRCWL_CSB_TO_CLKIN |\
	HRCWL_VCO_1X2 |\
	HRCWL_CORE_TO_CSB_2X1)

#if defined(PCI_64BIT)
#define CONFIG_SYS_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_64_BIT_PCI |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_PCI2_ARBITER_DISABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_TSEC1M_IN_GMII |\
	HRCWH_TSEC2M_IN_GMII)
#else
#define CONFIG_SYS_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_32_BIT_PCI |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_PCI2_ARBITER_ENABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_TSEC1M_IN_GMII |\
	HRCWH_TSEC2M_IN_GMII)
#endif

/* System IO Config */
#define CONFIG_SYS_SICRH 0
#define CONFIG_SYS_SICRL SICRL_LDP_A

#define CONFIG_SYS_HID0_INIT	0x000000000
#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
				 HID0_ENABLE_INSTRUCTION_CACHE)

#define CONFIG_SYS_HID2		HID2_HBE

#define CONFIG_SYS_GPIO1_PRELIM
#define CONFIG_SYS_GPIO1_DIR	0x00100000
#define CONFIG_SYS_GPIO1_DAT	0x00100000

#define CONFIG_SYS_GPIO2_PRELIM
#define CONFIG_SYS_GPIO2_DIR	0x78900000
#define CONFIG_SYS_GPIO2_DAT	0x70100000

#define CONFIG_HIGH_BATS		/* High BATs supported */

/* DDR @ 0x00000000 */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
				 BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
				 BATU_VS | BATU_VP)

/* PCI @ 0x80000000 */
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
				 BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
				 BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
				 BATU_VS | BATU_VP)
#else
#define CONFIG_SYS_IBAT1L	(0)
#define CONFIG_SYS_IBAT1U	(0)
#define CONFIG_SYS_IBAT2L	(0)
#define CONFIG_SYS_IBAT2U	(0)
#endif

#ifdef CONFIG_MPC83XX_PCI2
#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
				 BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
				 BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
				 BATU_VS | BATU_VP)
#else
#define CONFIG_SYS_IBAT3L	(0)
#define CONFIG_SYS_IBAT3U	(0)
#define CONFIG_SYS_IBAT4L	(0)
#define CONFIG_SYS_IBAT4U	(0)
#endif

/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_RW | \
				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | \
				 BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#if (CONFIG_SYS_DDR_SIZE == 512)
#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_SDRAM_BASE+0x10000000 | \
				 BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_SDRAM_BASE+0x10000000 | \
				 BATU_BL_256M | BATU_VS | BATU_VP)
#else
#define CONFIG_SYS_IBAT7L	(0)
#define CONFIG_SYS_IBAT7U	(0)
#endif

#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#endif

/*
 * Environment Configuration
 */
#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#endif

#define CONFIG_HOSTNAME		"VME8349"
#define CONFIG_ROOTPATH		"/tftpboot/rootfs"
#define CONFIG_BOOTFILE		"uImage"

#define CONFIG_LOADADDR		800000	/* def location for tftp and bootm */

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=vme8349\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
		"bootm\0"						\
	"load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0"		\
	"update=protect off fff00000 fff3ffff; "			\
		"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
	"upd=run load update\0"						\
	"fdtaddr=780000\0"						\
	"fdtfile=vme8349.dtb\0"						\
	""

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs root=/dev/nfs rw "				\
		"nfsroot=$serverip:$rootpath "				\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
							"$netdev:off "	\
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv bootargs root=/dev/ram rw "				\
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND	"run flash_self"

#ifndef __ASSEMBLY__
int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
		     unsigned char *buffer, int len);
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
c2e49f70 RA	2	/*
	3	* esd vme8349 U-Boot configuration file
	4	* Copyright (c) 2008, 2009 esd gmbh Hannover Germany
	5	*
2ae18241	6	* (C) Copyright 2006-2010
c2e49f70 RA	7	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	8	*
	9	* reinhard.arlt@esd-electronics.de
	10	* Based on the MPC8349EMDS config.
c2e49f70 RA	11	*/
	12
	13	/*
	14	* vme8349 board configuration file.
	15	*/
	16
	17	#ifndef __CONFIG_H
	18	#define __CONFIG_H
	19
1dee9be6 RA	20	/*
	21	* Top level Makefile configuration choices
	22	*/
2ae18241	23	#ifdef CONFIG_CADDY2
1dee9be6 RA	24	#define VME_CADDY2
	25	#endif
	26
c2e49f70 RA	27	/*
	28	* High Level Configuration Options
	29	*/
	30	#define CONFIG_E300 1 /* E300 Family */
c2e49f70 RA	31	#define CONFIG_MPC834x 1 /* MPC834x family */
	32	#define CONFIG_MPC8349 1 /* MPC8349 specific */
	33	#define CONFIG_VME8349 1 /* ESD VME8349 board specific */
	34
1dee9be6 RA	35	#define CONFIG_MISC_INIT_R
1dee9be6 RA	36
c2e49f70 RA	37	/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
	38	#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
	39
2ae18241 WD	40	#define CONFIG_PCI_66M
2ae18241 WD	41	#ifdef CONFIG_PCI_66M
c2e49f70 RA	42	#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
	43	#else
	44	#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
	45	#endif
	46
	47	#ifndef CONFIG_SYS_CLK_FREQ
2ae18241	48	#ifdef CONFIG_PCI_66M
c2e49f70 RA	49	#define CONFIG_SYS_CLK_FREQ 66000000
	50	#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
	51	#else
	52	#define CONFIG_SYS_CLK_FREQ 33000000
	53	#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
	54	#endif
	55	#endif
	56
	57	#define CONFIG_SYS_IMMR 0xE0000000
	58
	59	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
	60	#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
	61	#define CONFIG_SYS_MEMTEST_END 0x00100000
	62
	63	/*
	64	* DDR Setup
	65	*/
	66	#define CONFIG_DDR_ECC /* only for ECC DDR module */
	67	#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
1dee9be6 RA	68	#define CONFIG_SPD_EEPROM
	69	#define SPD_EEPROM_ADDRESS 0x54
	70	#define CONFIG_SYS_READ_SPD vme8349_read_spd
c2e49f70 RA	71	#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
	72
	73	/*
	74	* 32-bit data path mode.
	75	*
	76	* Please note that using this mode for devices with the real density of 64-bit
	77	* effectively reduces the amount of available memory due to the effect of
	78	* wrapping around while translating address to row/columns, for example in the
	79	* 256MB module the upper 128MB get aliased with contents of the lower
	80	* 128MB); normally this define should be used for devices with real 32-bit
	81	* data path.
	82	*/
	83	#undef CONFIG_DDR_32BIT
	84
	85	#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
	86	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
	87	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
2fef4020 JH	88	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
2fef4020 JH	89	\| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
c2e49f70	90	#define CONFIG_DDR_2T_TIMING
2fef4020 JH	91	#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
	92	\| DDRCDR_ODT \
	93	\| DDRCDR_Q_DRN)
	94	/* 0x80080001 */
c2e49f70 RA	95
	96	/*
	97	* FLASH on the Local Bus
	98	*/
	99	#define CONFIG_SYS_FLASH_CFI
	100	#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
1dee9be6 RA	101	#ifdef VME_CADDY2
	102	#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
	103	#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
	104	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \| \
7d6a0982 JH	105	BR_PS_16 \| /* 16bit */ \
	106	BR_MS_GPCM \| /* MSEL = GPCM */ \
	107	BR_V) /* valid */
	108
	109	#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
	110	\| OR_GPCM_XAM \
	111	\| OR_GPCM_CSNT \
	112	\| OR_GPCM_ACS_DIV2 \
	113	\| OR_GPCM_XACS \
	114	\| OR_GPCM_SCY_15 \
	115	\| OR_GPCM_TRLX_SET \
	116	\| OR_GPCM_EHTR_SET \
	117	\| OR_GPCM_EAD)
	118	/* 0xffc06ff7 */
1dee9be6	119	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
7d6a0982	120	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_4MB)
1dee9be6 RA	121	#else
	122	#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
	123	#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
c2e49f70	124	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \| \
7d6a0982 JH	125	BR_PS_16 \| /* 16bit */ \
	126	BR_MS_GPCM \| /* MSEL = GPCM */ \
	127	BR_V) /* valid */
	128
	129	#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
	130	\| OR_GPCM_XAM \
	131	\| OR_GPCM_CSNT \
	132	\| OR_GPCM_ACS_DIV2 \
	133	\| OR_GPCM_XACS \
	134	\| OR_GPCM_SCY_15 \
	135	\| OR_GPCM_TRLX_SET \
	136	\| OR_GPCM_EHTR_SET \
	137	\| OR_GPCM_EAD)
	138	/* 0xf8006ff7 */
c2e49f70	139	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
7d6a0982	140	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_128MB)
1dee9be6 RA	141	#endif
1dee9be6 RA	142	/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
c2e49f70	143
7d6a0982 JH	144	#define CONFIG_SYS_WINDOW1_BASE 0xf0000000
	145	#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \
	146	\| BR_PS_32 \
	147	\| BR_MS_GPCM \
	148	\| BR_V)
	149	/* 0xF0001801 */
	150	#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \
	151	\| OR_GPCM_SETA)
	152	/* 0xfffc0208 */
	153	#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE
	154	#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN \| LBLAWAR_256KB)
c2e49f70 RA	155
	156	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	157	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
	158
	159	#undef CONFIG_SYS_FLASH_CHECKSUM
	160	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
	161	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
	162
c7357a2b	163	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
c2e49f70 RA	164
	165	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	166	#define CONFIG_SYS_RAMBOOT
	167	#else
1dee9be6	168	#undef CONFIG_SYS_RAMBOOT
c2e49f70 RA	169	#endif
	170
	171	#define CONFIG_SYS_INIT_RAM_LOCK 1
	172	#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
553f0982	173	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
c2e49f70	174
553f0982	175	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
25ddd1fb	176	GENERATED_GBL_DATA_SIZE)
c2e49f70 RA	177	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	178
	179	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
c8a90646	180	#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
c2e49f70 RA	181
	182	/*
	183	* Local Bus LCRR and LBCR regs
1dee9be6	184	* LCRR: no DLL bypass, Clock divider is 4
c2e49f70 RA	185	* External Local Bus rate is
	186	* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
	187	*/
c7190f02	188	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
c2e49f70 RA	189	#define CONFIG_SYS_LBC_LBCR 0x00000000
	190
	191	#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
	192
	193	/*
	194	* Serial Port
	195	*/
c2e49f70 RA	196	#define CONFIG_SYS_NS16550_SERIAL
	197	#define CONFIG_SYS_NS16550_REG_SIZE 1
	198	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	199
	200	#define CONFIG_SYS_BAUDRATE_TABLE \
c7357a2b	201	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
c2e49f70 RA	202
	203	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
	204	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
	205
c2e49f70	206	/* I2C */
00f792e0 HS	207	#define CONFIG_SYS_I2C
	208	#define CONFIG_SYS_I2C_FSL
	209	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	210	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	211	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	212	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	213	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	214	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
	215	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
efaf6f1b	216	/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
c2e49f70 RA	217
	218	#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
	219
	220	/* TSEC */
	221	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
	222	#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
	223	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
	224	#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
	225
	226	/*
	227	* General PCI
	228	* Addresses are mapped 1-1.
	229	*/
	230	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
	231	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	232	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
	233	#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
	234	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
	235	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
	236	#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
	237	#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
	238	#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
	239
	240	#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
	241	#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
	242	#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
	243	#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
	244	#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
	245	#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
	246	#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
	247	#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
	248	#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
	249
	250	#if defined(CONFIG_PCI)
	251
	252	#define PCI_64BIT
	253	#define PCI_ONE_PCI1
	254	#if defined(PCI_64BIT)
	255	#undef PCI_ALL_PCI1
	256	#undef PCI_TWO_PCI1
	257	#undef PCI_ONE_PCI1
	258	#endif
	259
1dee9be6	260	#ifndef VME_CADDY2
1dee9be6	261	#endif
c2e49f70 RA	262
	263	#undef CONFIG_EEPRO100
	264	#undef CONFIG_TULIP
	265
	266	#if !defined(CONFIG_PCI_PNP)
	267	#define PCI_ENET0_IOADDR 0xFIXME
	268	#define PCI_ENET0_MEMADDR 0xFIXME
	269	#define PCI_IDSEL_NUMBER 0xFIXME
	270	#endif
	271
1dee9be6 RA	272	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	273	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
	274
c2e49f70 RA	275	#endif /* CONFIG_PCI */
	276
	277	/*
	278	* TSEC configuration
	279	*/
c2e49f70 RA	280
c2e49f70 RA	281	#if defined(CONFIG_TSEC_ENET)
c2e49f70	282
1dee9be6	283	#define CONFIG_GMII /* MII PHY management */
c2e49f70 RA	284	#define CONFIG_TSEC1
	285	#define CONFIG_TSEC1_NAME "TSEC0"
	286	#define CONFIG_TSEC2
	287	#define CONFIG_TSEC2_NAME "TSEC1"
	288	#define CONFIG_PHY_M88E1111
	289	#define TSEC1_PHY_ADDR 0x08
	290	#define TSEC2_PHY_ADDR 0x10
	291	#define TSEC1_PHYIDX 0
	292	#define TSEC2_PHYIDX 0
	293	#define TSEC1_FLAGS TSEC_GIGABIT
	294	#define TSEC2_FLAGS TSEC_GIGABIT
	295
	296	/* Options are: TSEC[0-1] */
	297	#define CONFIG_ETHPRIME "TSEC0"
	298
	299	#endif /* CONFIG_TSEC_ENET */
	300
	301	/*
	302	* Environment
	303	*/
	304	#ifndef CONFIG_SYS_RAMBOOT
c2e49f70 RA	305	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
	306	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
	307	#define CONFIG_ENV_SIZE 0x2000
	308
	309	/* Address and size of Redundant Environment Sector */
	310	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
	311	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
	312
	313	#else
c2e49f70 RA	314	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
	315	#define CONFIG_ENV_SIZE 0x2000
	316	#endif
	317
	318	#define CONFIG_LOADS_ECHO /* echo on for serial download */
	319	#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
	320
	321	/*
	322	* BOOTP options
	323	*/
	324	#define CONFIG_BOOTP_BOOTFILESIZE
c2e49f70 RA	325
	326	/*
	327	* Command line configuration.
	328	*/
c2e49f70 RA	329	#define CONFIG_SYS_RTC_BUS_NUM 0x01
	330	#define CONFIG_SYS_I2C_RTC_ADDR 0x32
	331	#define CONFIG_RTC_RX8025
c2e49f70	332
c2e49f70 RA	333	/* Pass Ethernet MAC to VxWorks */
	334	#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
	335
	336	#undef CONFIG_WATCHDOG /* watchdog disabled */
	337
	338	/*
	339	* Miscellaneous configurable options
	340	*/
c2e49f70	341	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
c2e49f70	342
c2e49f70 RA	343	/*
c2e49f70 RA	344	* For booting Linux, the board info and command line data
9f530d59	345	* have to be in the first 256 MB of memory, since this is
c2e49f70 RA	346	* the maximum mapped by the Linux kernel during initialization.
c2e49f70 RA	347	*/
9f530d59	348	#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
c2e49f70 RA	349
	350	#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
	351
	352	#define CONFIG_SYS_HRCW_LOW (\
	353	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \|\
	354	HRCWL_DDR_TO_SCB_CLK_1X1 \|\
	355	HRCWL_CSB_TO_CLKIN \|\
	356	HRCWL_VCO_1X2 \|\
	357	HRCWL_CORE_TO_CSB_2X1)
	358
	359	#if defined(PCI_64BIT)
	360	#define CONFIG_SYS_HRCW_HIGH (\
	361	HRCWH_PCI_HOST \|\
	362	HRCWH_64_BIT_PCI \|\
	363	HRCWH_PCI1_ARBITER_ENABLE \|\
	364	HRCWH_PCI2_ARBITER_DISABLE \|\
	365	HRCWH_CORE_ENABLE \|\
	366	HRCWH_FROM_0X00000100 \|\
	367	HRCWH_BOOTSEQ_DISABLE \|\
	368	HRCWH_SW_WATCHDOG_DISABLE \|\
	369	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	370	HRCWH_TSEC1M_IN_GMII \|\
	371	HRCWH_TSEC2M_IN_GMII)
	372	#else
	373	#define CONFIG_SYS_HRCW_HIGH (\
	374	HRCWH_PCI_HOST \|\
	375	HRCWH_32_BIT_PCI \|\
	376	HRCWH_PCI1_ARBITER_ENABLE \|\
	377	HRCWH_PCI2_ARBITER_ENABLE \|\
	378	HRCWH_CORE_ENABLE \|\
	379	HRCWH_FROM_0X00000100 \|\
	380	HRCWH_BOOTSEQ_DISABLE \|\
	381	HRCWH_SW_WATCHDOG_DISABLE \|\
	382	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	383	HRCWH_TSEC1M_IN_GMII \|\
	384	HRCWH_TSEC2M_IN_GMII)
	385	#endif
	386
	387	/* System IO Config */
	388	#define CONFIG_SYS_SICRH 0
	389	#define CONFIG_SYS_SICRL SICRL_LDP_A
	390
	391	#define CONFIG_SYS_HID0_INIT 0x000000000
1a2e203b KP	392	#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \| \
1a2e203b KP	393	HID0_ENABLE_INSTRUCTION_CACHE)
c2e49f70 RA	394
	395	#define CONFIG_SYS_HID2 HID2_HBE
	396
	397	#define CONFIG_SYS_GPIO1_PRELIM
	398	#define CONFIG_SYS_GPIO1_DIR 0x00100000
	399	#define CONFIG_SYS_GPIO1_DAT 0x00100000
	400
	401	#define CONFIG_SYS_GPIO2_PRELIM
	402	#define CONFIG_SYS_GPIO2_DIR 0x78900000
	403	#define CONFIG_SYS_GPIO2_DAT 0x70100000
	404
	405	#define CONFIG_HIGH_BATS /* High BATs supported */
	406
	407	/* DDR @ 0x00000000 */
72cd4087	408	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_RW \| \
c2e49f70 RA	409	BATL_MEMCOHERENCE)
	410	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| \
	411	BATU_VS \| BATU_VP)
	412
	413	/* PCI @ 0x80000000 */
	414	#ifdef CONFIG_PCI
842033e6	415	#define CONFIG_PCI_INDIRECT_BRIDGE
72cd4087	416	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \| BATL_PP_RW \| \
c2e49f70 RA	417	BATL_MEMCOHERENCE)
	418	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \| BATU_BL_256M \| \
	419	BATU_VS \| BATU_VP)
72cd4087	420	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \| BATL_PP_RW \| \
c2e49f70 RA	421	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	422	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \| BATU_BL_256M \| \
	423	BATU_VS \| BATU_VP)
	424	#else
	425	#define CONFIG_SYS_IBAT1L (0)
	426	#define CONFIG_SYS_IBAT1U (0)
	427	#define CONFIG_SYS_IBAT2L (0)
	428	#define CONFIG_SYS_IBAT2U (0)
	429	#endif
	430
	431	#ifdef CONFIG_MPC83XX_PCI2
72cd4087	432	#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \| BATL_PP_RW \| \
c2e49f70 RA	433	BATL_MEMCOHERENCE)
	434	#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \| BATU_BL_256M \| \
	435	BATU_VS \| BATU_VP)
72cd4087	436	#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \| BATL_PP_RW \| \
c2e49f70 RA	437	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	438	#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \| BATU_BL_256M \| \
	439	BATU_VS \| BATU_VP)
	440	#else
	441	#define CONFIG_SYS_IBAT3L (0)
	442	#define CONFIG_SYS_IBAT3U (0)
	443	#define CONFIG_SYS_IBAT4L (0)
	444	#define CONFIG_SYS_IBAT4U (0)
	445	#endif
	446
	447	/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
72cd4087	448	#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \| BATL_PP_RW \| \
c2e49f70 RA	449	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	450	#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \| BATU_BL_256M \| \
	451	BATU_VS \| BATU_VP)
	452
72cd4087	453	#define CONFIG_SYS_IBAT6L (0xF0000000 \| BATL_PP_RW \| BATL_MEMCOHERENCE)
c2e49f70 RA	454	#define CONFIG_SYS_IBAT6U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	455
	456	#if (CONFIG_SYS_DDR_SIZE == 512)
	457	#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 \| \
72cd4087	458	BATL_PP_RW \| BATL_MEMCOHERENCE)
c2e49f70 RA	459	#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 \| \
	460	BATU_BL_256M \| BATU_VS \| BATU_VP)
	461	#else
	462	#define CONFIG_SYS_IBAT7L (0)
	463	#define CONFIG_SYS_IBAT7U (0)
	464	#endif
	465
	466	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	467	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	468	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	469	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	470	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	471	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	472	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	473	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
	474	#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
	475	#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
	476	#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
	477	#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
	478	#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
	479	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
	480	#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
	481	#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
	482
c2e49f70 RA	483	#if defined(CONFIG_CMD_KGDB)
c2e49f70 RA	484	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
c2e49f70 RA	485	#endif
	486
	487	/*
	488	* Environment Configuration
	489	*/
	490	#define CONFIG_ENV_OVERWRITE
	491
	492	#if defined(CONFIG_TSEC_ENET)
	493	#define CONFIG_HAS_ETH0
	494	#define CONFIG_HAS_ETH1
	495	#endif
	496
5bc0543d	497	#define CONFIG_HOSTNAME "VME8349"
8b3637c6	498	#define CONFIG_ROOTPATH "/tftpboot/rootfs"
b3f44c21	499	#define CONFIG_BOOTFILE "uImage"
c2e49f70	500
79f516bc	501	#define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
c2e49f70	502
c2e49f70 RA	503	#define CONFIG_EXTRA_ENV_SETTINGS \
	504	"netdev=eth0\0" \
	505	"hostname=vme8349\0" \
	506	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	507	"nfsroot=${serverip}:${rootpath}\0" \
	508	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	509	"addip=setenv bootargs ${bootargs} " \
	510	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	511	":${hostname}:${netdev}:off panic=1\0" \
	512	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	513	"flash_nfs=run nfsargs addip addtty;" \
	514	"bootm ${kernel_addr}\0" \
	515	"flash_self=run ramargs addip addtty;" \
	516	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	517	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
	518	"bootm\0" \
	519	"load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
	520	"update=protect off fff00000 fff3ffff; " \
	521	"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
	522	"upd=run load update\0" \
79f516bc	523	"fdtaddr=780000\0" \
c2e49f70 RA	524	"fdtfile=vme8349.dtb\0" \
	525	""
	526
c7357a2b JH	527	#define CONFIG_NFSBOOTCOMMAND \
	528	"setenv bootargs root=/dev/nfs rw " \
	529	"nfsroot=$serverip:$rootpath " \
	530	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
	531	"$netdev:off " \
	532	"console=$consoledev,$baudrate $othbootargs;" \
	533	"tftp $loadaddr $bootfile;" \
	534	"tftp $fdtaddr $fdtfile;" \
	535	"bootm $loadaddr - $fdtaddr"
c2e49f70 RA	536
c2e49f70 RA	537	#define CONFIG_RAMBOOTCOMMAND \
c7357a2b JH	538	"setenv bootargs root=/dev/ram rw " \
	539	"console=$consoledev,$baudrate $othbootargs;" \
	540	"tftp $ramdiskaddr $ramdiskfile;" \
	541	"tftp $loadaddr $bootfile;" \
	542	"tftp $fdtaddr $fdtfile;" \
	543	"bootm $loadaddr $ramdiskaddr $fdtaddr"
c2e49f70 RA	544
	545	#define CONFIG_BOOTCOMMAND "run flash_self"
	546
1dee9be6 RA	547	#ifndef __ASSEMBLY__
	548	int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
	549	unsigned char *buffer, int len);
	550	#endif
	551
c2e49f70	552	#endif /* __CONFIG_H */