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18a00dfd MV |
1 | /* |
2 | * Voipac PXA270 configuration file | |
3 | * | |
4 | * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
18a00dfd MV |
7 | */ |
8 | ||
f905432c MV |
9 | #ifndef __CONFIG_H |
10 | #define __CONFIG_H | |
18a00dfd MV |
11 | |
12 | /* | |
13 | * High Level Board Configuration Options | |
14 | */ | |
abc20aba | 15 | #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ |
18a00dfd | 16 | #define CONFIG_VPAC270 1 /* Voipac PXA270 board */ |
411b9eaf MV |
17 | #define CONFIG_SYS_TEXT_BASE 0xa0000000 |
18 | ||
19 | #ifdef CONFIG_ONENAND | |
411b9eaf MV |
20 | #define CONFIG_SPL_ONENAND_SUPPORT |
21 | #define CONFIG_SPL_ONENAND_LOAD_ADDR 0x2000 | |
22 | #define CONFIG_SPL_ONENAND_LOAD_SIZE \ | |
23 | (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR) | |
24 | #define CONFIG_SPL_TEXT_BASE 0x5c000000 | |
25 | #define CONFIG_SPL_LDSCRIPT "board/vpac270/u-boot-spl.lds" | |
26 | #endif | |
18a00dfd | 27 | |
18a00dfd MV |
28 | /* |
29 | * Environment settings | |
30 | */ | |
f905432c MV |
31 | #define CONFIG_ENV_OVERWRITE |
32 | #define CONFIG_SYS_MALLOC_LEN (128*1024) | |
720a650c | 33 | #define CONFIG_ARCH_CPU_INIT |
18a00dfd MV |
34 | #define CONFIG_BOOTCOMMAND \ |
35 | "if mmc init && fatload mmc 0 0xa4000000 uImage; then " \ | |
36 | "bootm 0xa4000000; " \ | |
37 | "fi; " \ | |
38 | "if usb reset && fatload usb 0 0xa4000000 uImage; then " \ | |
39 | "bootm 0xa4000000; " \ | |
40 | "fi; " \ | |
f905432c MV |
41 | "if ide reset && fatload ide 0 0xa4000000 uImage; then " \ |
42 | "bootm 0xa4000000; " \ | |
43 | "fi; " \ | |
11934fbf | 44 | "bootm 0x60000;" |
411b9eaf MV |
45 | |
46 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
47 | "update_onenand=" \ | |
48 | "onenand erase 0x0 0x80000 ; " \ | |
49 | "onenand write 0xa0000000 0x0 0x80000" | |
50 | ||
18a00dfd MV |
51 | #define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200" |
52 | #define CONFIG_TIMESTAMP | |
53 | #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ | |
54 | #define CONFIG_CMDLINE_TAG | |
55 | #define CONFIG_SETUP_MEMORY_TAGS | |
18a00dfd | 56 | #define CONFIG_LZMA /* LZMA compression support */ |
411b9eaf | 57 | #define CONFIG_OF_LIBFDT |
18a00dfd MV |
58 | |
59 | /* | |
60 | * Serial Console Configuration | |
61 | */ | |
62 | #define CONFIG_PXA_SERIAL | |
63 | #define CONFIG_FFUART 1 | |
ce6971cd | 64 | #define CONFIG_CONS_INDEX 3 |
18a00dfd | 65 | #define CONFIG_BAUDRATE 115200 |
18a00dfd MV |
66 | |
67 | /* | |
68 | * Bootloader Components Configuration | |
69 | */ | |
70 | #include <config_cmd_default.h> | |
71 | ||
72 | #define CONFIG_CMD_NET | |
73 | #define CONFIG_CMD_ENV | |
74 | #undef CONFIG_CMD_IMLS | |
75 | #define CONFIG_CMD_MMC | |
76 | #define CONFIG_CMD_USB | |
77 | #undef CONFIG_LCD | |
78 | #define CONFIG_CMD_IDE | |
79 | ||
f97e9c65 | 80 | #ifdef CONFIG_ONENAND |
18a00dfd MV |
81 | #undef CONFIG_CMD_FLASH |
82 | #define CONFIG_CMD_ONENAND | |
83 | #else | |
84 | #define CONFIG_CMD_FLASH | |
85 | #undef CONFIG_CMD_ONENAND | |
86 | #endif | |
87 | ||
88 | /* | |
89 | * Networking Configuration | |
90 | * chip on the Voipac PXA270 board | |
91 | */ | |
92 | #ifdef CONFIG_CMD_NET | |
93 | #define CONFIG_CMD_PING | |
94 | #define CONFIG_CMD_DHCP | |
95 | ||
18a00dfd | 96 | #define CONFIG_DRIVER_DM9000 1 |
f905432c MV |
97 | #define CONFIG_DM9000_BASE 0x08000300 /* CS2 */ |
98 | #define DM9000_IO (CONFIG_DM9000_BASE) | |
99 | #define DM9000_DATA (CONFIG_DM9000_BASE + 4) | |
18a00dfd MV |
100 | #define CONFIG_NET_RETRY_COUNT 10 |
101 | ||
102 | #define CONFIG_BOOTP_BOOTFILESIZE | |
103 | #define CONFIG_BOOTP_BOOTPATH | |
104 | #define CONFIG_BOOTP_GATEWAY | |
105 | #define CONFIG_BOOTP_HOSTNAME | |
106 | #endif | |
107 | ||
108 | /* | |
109 | * MMC Card Configuration | |
110 | */ | |
111 | #ifdef CONFIG_CMD_MMC | |
112 | #define CONFIG_MMC | |
5d877f42 MV |
113 | #define CONFIG_GENERIC_MMC |
114 | #define CONFIG_PXA_MMC_GENERIC | |
18a00dfd MV |
115 | #define CONFIG_SYS_MMC_BASE 0xF0000000 |
116 | #define CONFIG_CMD_FAT | |
f905432c | 117 | #define CONFIG_CMD_EXT2 |
18a00dfd MV |
118 | #define CONFIG_DOS_PARTITION |
119 | #endif | |
120 | ||
121 | /* | |
122 | * KGDB | |
123 | */ | |
124 | #ifdef CONFIG_CMD_KGDB | |
f905432c | 125 | #define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ |
18a00dfd MV |
126 | #endif |
127 | ||
128 | /* | |
129 | * HUSH Shell Configuration | |
130 | */ | |
131 | #define CONFIG_SYS_HUSH_PARSER 1 | |
18a00dfd | 132 | |
f905432c | 133 | #define CONFIG_SYS_LONGHELP |
18a00dfd | 134 | #ifdef CONFIG_SYS_HUSH_PARSER |
f905432c | 135 | #define CONFIG_SYS_PROMPT "$ " |
18a00dfd | 136 | #else |
18a00dfd | 137 | #endif |
f905432c MV |
138 | #define CONFIG_SYS_CBSIZE 256 |
139 | #define CONFIG_SYS_PBSIZE \ | |
140 | (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
141 | #define CONFIG_SYS_MAXARGS 16 | |
142 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
18a00dfd | 143 | #define CONFIG_SYS_DEVICE_NULLDEV 1 |
7c7204db MV |
144 | #define CONFIG_CMDLINE_EDITING 1 |
145 | #define CONFIG_AUTO_COMPLETE 1 | |
18a00dfd MV |
146 | |
147 | /* | |
148 | * Clock Configuration | |
149 | */ | |
f905432c | 150 | #define CONFIG_SYS_CPUSPEED 0x190 /* 312MHz */ |
18a00dfd | 151 | |
18a00dfd MV |
152 | |
153 | /* | |
154 | * DRAM Map | |
155 | */ | |
f905432c | 156 | #define CONFIG_NR_DRAM_BANKS 2 /* 2 banks of DRAM */ |
18a00dfd MV |
157 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ |
158 | #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ | |
f905432c | 159 | |
f97e9c65 | 160 | #ifdef CONFIG_RAM_256M |
18a00dfd MV |
161 | #define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */ |
162 | #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ | |
f905432c | 163 | #endif |
18a00dfd MV |
164 | |
165 | #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ | |
f97e9c65 | 166 | #ifdef CONFIG_RAM_256M |
18a00dfd | 167 | #define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */ |
f905432c MV |
168 | #else |
169 | #define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */ | |
170 | #endif | |
18a00dfd | 171 | |
f905432c MV |
172 | #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ |
173 | #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ | |
18a00dfd | 174 | |
451a0c39 | 175 | #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 |
6ef6eb91 | 176 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
411b9eaf | 177 | #define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 |
18a00dfd MV |
178 | |
179 | /* | |
180 | * NOR FLASH | |
181 | */ | |
11934fbf | 182 | #define CONFIG_SYS_MONITOR_BASE 0x0 |
411b9eaf | 183 | #define CONFIG_SYS_MONITOR_LEN 0x80000 |
11934fbf MK |
184 | #define CONFIG_ENV_ADDR \ |
185 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
3e43c749 MV |
186 | #define CONFIG_ENV_SIZE 0x20000 |
187 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
11934fbf | 188 | |
18a00dfd MV |
189 | #if defined(CONFIG_CMD_FLASH) /* NOR */ |
190 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
f905432c | 191 | |
f97e9c65 | 192 | #ifdef CONFIG_RAM_256M |
18a00dfd | 193 | #define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */ |
f905432c | 194 | #endif |
18a00dfd MV |
195 | |
196 | #define CONFIG_SYS_FLASH_CFI | |
197 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
198 | ||
199 | #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) | |
f97e9c65 | 200 | #ifdef CONFIG_RAM_256M |
18a00dfd MV |
201 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 |
202 | #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } | |
f905432c MV |
203 | #else |
204 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
205 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 | |
206 | #endif | |
18a00dfd MV |
207 | |
208 | #define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) | |
209 | #define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) | |
210 | ||
211 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
212 | #define CONFIG_SYS_FLASH_PROTECTION 1 | |
213 | ||
f905432c | 214 | #define CONFIG_ENV_IS_IN_FLASH 1 |
11934fbf | 215 | |
18a00dfd MV |
216 | #elif defined(CONFIG_CMD_ONENAND) /* OneNAND */ |
217 | #define CONFIG_SYS_NO_FLASH | |
218 | #define CONFIG_SYS_ONENAND_BASE 0x00000000 | |
f905432c | 219 | |
18a00dfd MV |
220 | #define CONFIG_ENV_IS_IN_ONENAND 1 |
221 | ||
222 | #else /* No flash */ | |
223 | #define CONFIG_SYS_NO_FLASH | |
50dea462 | 224 | #define CONFIG_ENV_IS_NOWHERE |
18a00dfd MV |
225 | #endif |
226 | ||
18a00dfd MV |
227 | /* |
228 | * IDE | |
229 | */ | |
230 | #ifdef CONFIG_CMD_IDE | |
231 | #define CONFIG_LBA48 | |
232 | #undef CONFIG_IDE_LED | |
233 | #undef CONFIG_IDE_RESET | |
234 | ||
b417260d MV |
235 | #define __io |
236 | ||
f905432c MV |
237 | #define CONFIG_SYS_IDE_MAXBUS 1 |
238 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
18a00dfd | 239 | |
f905432c MV |
240 | #define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000 |
241 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 | |
18a00dfd | 242 | |
f905432c MV |
243 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x120 |
244 | #define CONFIG_SYS_ATA_REG_OFFSET 0x120 | |
245 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x120 | |
18a00dfd MV |
246 | |
247 | #define CONFIG_SYS_ATA_STRIDE 2 | |
248 | #endif | |
249 | ||
250 | /* | |
251 | * GPIO settings | |
252 | */ | |
253 | #define CONFIG_SYS_GPSR0_VAL 0x01308800 | |
254 | #define CONFIG_SYS_GPSR1_VAL 0x00cf0000 | |
255 | #define CONFIG_SYS_GPSR2_VAL 0x922ac000 | |
256 | #define CONFIG_SYS_GPSR3_VAL 0x0161e800 | |
257 | ||
258 | #define CONFIG_SYS_GPCR0_VAL 0x00010000 | |
259 | #define CONFIG_SYS_GPCR1_VAL 0x0 | |
260 | #define CONFIG_SYS_GPCR2_VAL 0x0 | |
261 | #define CONFIG_SYS_GPCR3_VAL 0x0 | |
262 | ||
263 | #define CONFIG_SYS_GPDR0_VAL 0xcbb18800 | |
264 | #define CONFIG_SYS_GPDR1_VAL 0xfccfa981 | |
265 | #define CONFIG_SYS_GPDR2_VAL 0x922affff | |
266 | #define CONFIG_SYS_GPDR3_VAL 0x0161e904 | |
267 | ||
268 | #define CONFIG_SYS_GAFR0_L_VAL 0x00100000 | |
269 | #define CONFIG_SYS_GAFR0_U_VAL 0xa5da8510 | |
270 | #define CONFIG_SYS_GAFR1_L_VAL 0x6992901a | |
271 | #define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a0aa | |
272 | #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa | |
273 | #define CONFIG_SYS_GAFR2_U_VAL 0x4109a401 | |
274 | #define CONFIG_SYS_GAFR3_L_VAL 0x54010310 | |
275 | #define CONFIG_SYS_GAFR3_U_VAL 0x00025401 | |
276 | ||
277 | #define CONFIG_SYS_PSSR_VAL 0x30 | |
278 | ||
279 | /* | |
280 | * Clock settings | |
281 | */ | |
282 | #define CONFIG_SYS_CKEN 0x00500240 | |
283 | #define CONFIG_SYS_CCCR 0x02000290 | |
284 | ||
285 | /* | |
286 | * Memory settings | |
287 | */ | |
4efd6925 | 288 | #define CONFIG_SYS_MSC0_VAL 0x3ffc95f9 |
18a00dfd MV |
289 | #define CONFIG_SYS_MSC1_VAL 0x02ccf974 |
290 | #define CONFIG_SYS_MSC2_VAL 0x00000000 | |
f97e9c65 | 291 | #ifdef CONFIG_RAM_256M |
18a00dfd | 292 | #define CONFIG_SYS_MDCNFG_VAL 0x8ad30ad3 |
f905432c MV |
293 | #else |
294 | #define CONFIG_SYS_MDCNFG_VAL 0x88000ad3 | |
295 | #endif | |
18a00dfd MV |
296 | #define CONFIG_SYS_MDREFR_VAL 0x201fe01e |
297 | #define CONFIG_SYS_MDMRS_VAL 0x00000000 | |
298 | #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 | |
299 | #define CONFIG_SYS_SXCNFG_VAL 0x40044004 | |
18a00dfd MV |
300 | |
301 | /* | |
302 | * PCMCIA and CF Interfaces | |
303 | */ | |
304 | #define CONFIG_SYS_MECR_VAL 0x00000001 | |
305 | #define CONFIG_SYS_MCMEM0_VAL 0x00014307 | |
306 | #define CONFIG_SYS_MCMEM1_VAL 0x00014307 | |
307 | #define CONFIG_SYS_MCATT0_VAL 0x0001c787 | |
308 | #define CONFIG_SYS_MCATT1_VAL 0x0001c787 | |
309 | #define CONFIG_SYS_MCIO0_VAL 0x0001430f | |
310 | #define CONFIG_SYS_MCIO1_VAL 0x0001430f | |
311 | ||
312 | /* | |
313 | * LCD | |
314 | */ | |
315 | #ifdef CONFIG_LCD | |
f905432c | 316 | #define CONFIG_VOIPAC_LCD |
18a00dfd MV |
317 | #endif |
318 | ||
319 | /* | |
320 | * USB | |
321 | */ | |
f905432c | 322 | #ifdef CONFIG_CMD_USB |
18a00dfd MV |
323 | #define CONFIG_USB_OHCI_NEW |
324 | #define CONFIG_SYS_USB_OHCI_CPU_INIT | |
325 | #define CONFIG_SYS_USB_OHCI_BOARD_INIT | |
326 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 | |
327 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 | |
328 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "vpac270" | |
329 | #define CONFIG_USB_STORAGE | |
330 | #endif | |
331 | ||
332 | #endif /* __CONFIG_H */ |