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0f8c9768 | 1 | /* |
8a316c9b SR |
2 | * (C) Copyright 2000-2005 |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
0f8c9768 | 4 | * |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
0f8c9768 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | * (easy to change) | |
18 | */ | |
19 | ||
20 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ | |
095b8a37 | 21 | #define CONFIG_WALNUT 1 /* ...on a WALNUT board */ |
2ae18241 WD |
22 | /* ...or on a SYCAMORE board */ |
23 | ||
24 | #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 | |
0f8c9768 | 25 | |
72675dc6 SR |
26 | /* |
27 | * Include common defines/options for all AMCC eval boards | |
28 | */ | |
29 | #define CONFIG_HOSTNAME walnut | |
30 | #include "amcc-common.h" | |
31 | ||
c837dcb1 | 32 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
0f8c9768 | 33 | |
095b8a37 | 34 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ |
0f8c9768 | 35 | |
72675dc6 SR |
36 | /* |
37 | * Default environment variables | |
38 | */ | |
39 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
40 | CONFIG_AMCC_DEF_ENV \ | |
41 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
42 | CONFIG_AMCC_DEF_ENV_PPC_OLD \ | |
43 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
8a316c9b SR |
44 | "kernel_addr=fff80000\0" \ |
45 | "ramdisk_addr=fff80000\0" \ | |
8a316c9b | 46 | "" |
0f8c9768 | 47 | |
095b8a37 | 48 | #define CONFIG_PHY_ADDR 1 /* PHY address */ |
a00eccfe | 49 | #define CONFIG_HAS_ETH0 1 |
4f92ed5f | 50 | |
0f8c9768 WD |
51 | #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */ |
52 | ||
dca3b3d6 | 53 | /* |
72675dc6 | 54 | * Commands additional to the ones defined in amcc-common.h |
dca3b3d6 | 55 | */ |
dca3b3d6 | 56 | #define CONFIG_CMD_DATE |
dca3b3d6 | 57 | #define CONFIG_CMD_PCI |
dca3b3d6 JL |
58 | #define CONFIG_CMD_SDRAM |
59 | #define CONFIG_CMD_SNTP | |
60 | ||
0f8c9768 WD |
61 | #define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ |
62 | ||
0f8c9768 | 63 | /* |
6d0f6bcf JCPV |
64 | * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. |
65 | * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. | |
66 | * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. | |
0f8c9768 WD |
67 | * The Linux BASE_BAUD define should match this configuration. |
68 | * baseBaud = cpuClock/(uartDivisor*16) | |
6d0f6bcf | 69 | * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, |
0f8c9768 WD |
70 | * set Linux BASE_BAUD to 403200. |
71 | */ | |
550650dd | 72 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
6d0f6bcf JCPV |
73 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ |
74 | #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ | |
75 | #define CONFIG_SYS_BASE_BAUD 691200 | |
0f8c9768 | 76 | |
8a316c9b SR |
77 | /*----------------------------------------------------------------------- |
78 | * I2C stuff | |
79 | *----------------------------------------------------------------------- | |
80 | */ | |
880540de | 81 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 |
0f8c9768 | 82 | |
6d0f6bcf JCPV |
83 | #define CONFIG_SYS_I2C_MULTI_EEPROMS |
84 | #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) | |
85 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
86 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
87 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
4f92ed5f | 88 | |
0f8c9768 WD |
89 | /*----------------------------------------------------------------------- |
90 | * PCI stuff | |
91 | *----------------------------------------------------------------------- | |
92 | */ | |
095b8a37 WD |
93 | #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ |
94 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
95 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
96 | ||
97 | #define CONFIG_PCI /* include pci support */ | |
842033e6 | 98 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
095b8a37 WD |
99 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ |
100 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
101 | /* resource configuration */ | |
8a316c9b | 102 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
0f8c9768 | 103 | |
6d0f6bcf JCPV |
104 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
105 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ | |
106 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
107 | #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ | |
108 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
109 | #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ | |
110 | #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ | |
111 | #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
0f8c9768 | 112 | |
0f8c9768 WD |
113 | /*----------------------------------------------------------------------- |
114 | * Start addresses for the final memory configuration | |
115 | * (Set up by the startup code) | |
0f8c9768 | 116 | */ |
6d0f6bcf | 117 | #define CONFIG_SYS_FLASH_BASE 0xFFF80000 |
8a316c9b SR |
118 | |
119 | /* | |
120 | * Define here the location of the environment variables (FLASH or NVRAM). | |
121 | * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only | |
095b8a37 | 122 | * supported for backward compatibility. |
8a316c9b SR |
123 | */ |
124 | #if 1 | |
5a1aceb0 | 125 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
8a316c9b | 126 | #else |
9314cee6 | 127 | #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ |
8a316c9b | 128 | #endif |
0f8c9768 | 129 | |
0f8c9768 WD |
130 | /*----------------------------------------------------------------------- |
131 | * FLASH organization | |
132 | */ | |
6d0f6bcf | 133 | #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ |
095b8a37 | 134 | #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ |
8a316c9b | 135 | |
6d0f6bcf JCPV |
136 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
137 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
0f8c9768 | 138 | |
6d0f6bcf JCPV |
139 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
140 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
0f8c9768 | 141 | |
6d0f6bcf | 142 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
8a316c9b | 143 | |
6d0f6bcf JCPV |
144 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 |
145 | #define CONFIG_SYS_FLASH_ADDR1 0x2aaa | |
146 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned char | |
8a316c9b | 147 | |
5a1aceb0 | 148 | #ifdef CONFIG_ENV_IS_IN_FLASH |
0e8d1586 | 149 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
6d0f6bcf | 150 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) |
0e8d1586 | 151 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
8a316c9b SR |
152 | |
153 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
154 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
155 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
5a1aceb0 | 156 | #endif /* CONFIG_ENV_IS_IN_FLASH */ |
8a316c9b | 157 | |
0f8c9768 WD |
158 | /*----------------------------------------------------------------------- |
159 | * NVRAM organization | |
160 | */ | |
6d0f6bcf JCPV |
161 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ |
162 | #define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */ | |
0f8c9768 | 163 | |
9314cee6 | 164 | #ifdef CONFIG_ENV_IS_IN_NVRAM |
0e8d1586 JCPV |
165 | #define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ |
166 | #define CONFIG_ENV_ADDR \ | |
6d0f6bcf | 167 | (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */ |
0f8c9768 | 168 | #endif |
8a316c9b | 169 | |
8a316c9b SR |
170 | /*----------------------------------------------------------------------- |
171 | * External Bus Controller (EBC) Setup | |
0f8c9768 WD |
172 | */ |
173 | ||
8a316c9b | 174 | /* Memory Bank 0 (Flash Bank 0) initialization */ |
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_EBC_PB0AP 0x9B015480 |
176 | #define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ | |
8a316c9b | 177 | |
6d0f6bcf JCPV |
178 | #define CONFIG_SYS_EBC_PB1AP 0x02815480 |
179 | #define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
8a316c9b | 180 | |
6d0f6bcf JCPV |
181 | #define CONFIG_SYS_EBC_PB2AP 0x04815A80 |
182 | #define CONFIG_SYS_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ | |
0f8c9768 | 183 | |
6d0f6bcf JCPV |
184 | #define CONFIG_SYS_EBC_PB3AP 0x01815280 |
185 | #define CONFIG_SYS_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ | |
0f8c9768 | 186 | |
6d0f6bcf JCPV |
187 | #define CONFIG_SYS_EBC_PB7AP 0x01815280 |
188 | #define CONFIG_SYS_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ | |
8a316c9b SR |
189 | |
190 | /*----------------------------------------------------------------------- | |
191 | * External peripheral base address | |
192 | *----------------------------------------------------------------------- | |
193 | */ | |
6d0f6bcf JCPV |
194 | #define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000 |
195 | #define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000 | |
196 | #define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000 | |
0f8c9768 WD |
197 | |
198 | /*----------------------------------------------------------------------- | |
8a316c9b | 199 | * Definitions for initial stack pointer and data area |
0f8c9768 | 200 | */ |
6d0f6bcf | 201 | #define CONFIG_SYS_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */ |
0f8c9768 | 202 | |
6d0f6bcf | 203 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */ |
553f0982 | 204 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ |
25ddd1fb | 205 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 206 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
0f8c9768 WD |
207 | |
208 | /*----------------------------------------------------------------------- | |
209 | * Definitions for Serial Presence Detect EEPROM address | |
210 | * (to get SDRAM settings) | |
211 | */ | |
095b8a37 | 212 | #define SPD_EEPROM_ADDRESS 0x50 |
0f8c9768 | 213 | |
0f8c9768 | 214 | #endif /* __CONFIG_H */ |