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47173483 FE |
1 | /* |
2 | * Copyright (C) 2016 NXP Semiconductors | |
3 | * | |
4 | * Configuration settings for the i.MX7S Warp board. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #ifndef __WARP7_CONFIG_H | |
10 | #define __WARP7_CONFIG_H | |
11 | ||
47173483 FE |
12 | #include "mx7_common.h" |
13 | ||
14 | #define PHYS_SDRAM_SIZE SZ_512M | |
15 | ||
01f512bc FE |
16 | #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR |
17 | ||
6baa2616 | 18 | /* Size of malloc() pool */ |
67ef2c13 | 19 | #define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) |
6baa2616 | 20 | |
47173483 FE |
21 | /* MMC Config*/ |
22 | #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR | |
23 | #define CONFIG_SUPPORT_EMMC_BOOT | |
24 | #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE | |
25 | #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 | |
26 | ||
27 | #define CONFIG_DFU_ENV_SETTINGS \ | |
67ef2c13 | 28 | "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \ |
47173483 FE |
29 | |
30 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
31 | CONFIG_DFU_ENV_SETTINGS \ | |
32 | "script=boot.scr\0" \ | |
33 | "image=zImage\0" \ | |
34 | "console=ttymxc0\0" \ | |
25aaebdb | 35 | "ethact=usb_ether\0" \ |
47173483 FE |
36 | "fdt_high=0xffffffff\0" \ |
37 | "initrd_high=0xffffffff\0" \ | |
ed395226 | 38 | "fdt_file=imx7s-warp.dtb\0" \ |
47173483 FE |
39 | "fdt_addr=0x83000000\0" \ |
40 | "boot_fdt=try\0" \ | |
41 | "ip_dyn=yes\0" \ | |
42 | "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ | |
43 | "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ | |
ca4f338e | 44 | "finduuid=part uuid mmc 0:2 uuid\0" \ |
47173483 | 45 | "mmcargs=setenv bootargs console=${console},${baudrate} " \ |
ca4f338e | 46 | "root=PARTUUID=${uuid} rootwait rw\0" \ |
47173483 FE |
47 | "loadbootscript=" \ |
48 | "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ | |
49 | "bootscript=echo Running bootscript from mmc ...; " \ | |
50 | "source\0" \ | |
51 | "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ | |
52 | "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ | |
53 | "mmcboot=echo Booting from mmc ...; " \ | |
ca4f338e | 54 | "run finduuid; " \ |
47173483 FE |
55 | "run mmcargs; " \ |
56 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ | |
57 | "if run loadfdt; then " \ | |
58 | "bootz ${loadaddr} - ${fdt_addr}; " \ | |
59 | "else " \ | |
60 | "if test ${boot_fdt} = try; then " \ | |
61 | "bootz; " \ | |
62 | "else " \ | |
63 | "echo WARN: Cannot load the DT; " \ | |
64 | "fi; " \ | |
65 | "fi; " \ | |
66 | "else " \ | |
67 | "bootz; " \ | |
68 | "fi;\0" \ | |
69 | ||
70 | #define CONFIG_BOOTCOMMAND \ | |
71 | "mmc dev ${mmcdev};" \ | |
72 | "mmc dev ${mmcdev}; if mmc rescan; then " \ | |
73 | "if run loadbootscript; then " \ | |
74 | "run bootscript; " \ | |
75 | "else " \ | |
76 | "if run loadimage; then " \ | |
77 | "run mmcboot; " \ | |
78 | "fi; " \ | |
79 | "fi; " \ | |
80 | "fi" | |
81 | ||
47173483 FE |
82 | #define CONFIG_SYS_MEMTEST_START 0x80000000 |
83 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) | |
84 | ||
85 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
86 | #define CONFIG_SYS_HZ 1000 | |
87 | ||
88 | #define CONFIG_STACKSIZE SZ_128K | |
89 | ||
90 | /* Physical Memory Map */ | |
91 | #define CONFIG_NR_DRAM_BANKS 1 | |
92 | #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR | |
93 | ||
94 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM | |
95 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
96 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
97 | ||
98 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
99 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
100 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
101 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
102 | ||
7d301a59 VM |
103 | /* I2C configs */ |
104 | #define CONFIG_SYS_I2C | |
105 | #define CONFIG_SYS_I2C_MXC | |
106 | #define CONFIG_SYS_I2C_MXC_I2C1 | |
107 | #define CONFIG_SYS_I2C_SPEED 100000 | |
108 | ||
109 | /* PMIC */ | |
110 | #define CONFIG_POWER | |
111 | #define CONFIG_POWER_I2C | |
112 | #define CONFIG_POWER_PFUZE3000 | |
113 | #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 | |
114 | ||
e856bdcf | 115 | /* environment organization */ |
47173483 FE |
116 | #define CONFIG_ENV_SIZE SZ_8K |
117 | #define CONFIG_ENV_IS_IN_MMC | |
118 | ||
119 | #define CONFIG_ENV_OFFSET (8 * SZ_64K) | |
120 | #define CONFIG_SYS_FSL_USDHC_NUM 1 | |
121 | ||
122 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
123 | #define CONFIG_SYS_MMC_ENV_PART 0 | |
47173483 FE |
124 | |
125 | /* USB Configs */ | |
47173483 FE |
126 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
127 | ||
128 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) | |
129 | #define CONFIG_MXC_USB_FLAGS 0 | |
130 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG1 port enabled */ | |
131 | ||
132 | #define CONFIG_IMX_THERMAL | |
133 | ||
47173483 | 134 | #define CONFIG_USBD_HS |
47173483 | 135 | |
47173483 | 136 | #define CONFIG_USB_FUNCTION_MASS_STORAGE |
47173483 FE |
137 | |
138 | /* USB Device Firmware Update support */ | |
47173483 FE |
139 | #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M |
140 | #define DFU_DEFAULT_POLL_TIMEOUT 300 | |
141 | ||
25aaebdb KH |
142 | #define CONFIG_USB_ETHER |
143 | #define CONFIG_USB_ETH_CDC | |
144 | #define CONFIG_USB_ETH_RNDIS | |
145 | #define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00" | |
146 | #define CONFIG_USBNET_DEV_ADDR "de:ad:be:af:00:01" | |
147 | ||
47173483 | 148 | #endif |