[people/ms/u-boot.git] / include / configs / woodburn_common.h

/*
 * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
 *
 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
 *
 * Configuration for the woodburn board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __WOODBURN_COMMON_CONFIG_H
#define __WOODBURN_COMMON_CONFIG_H

#include <asm/arch/imx-regs.h>

 /* High Level Configuration Options */
#define CONFIG_MX35
#define CONFIG_MX35_HCLK_FREQ	24000000
#define CONFIG_SYS_FSL_CLK

#define CONFIG_SYS_DCACHE_OFF

#define CONFIG_MACH_TYPE		MACH_TYPE_FLEA3

/* This is required to setup the ESDC controller */

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)

/*
 * Hardware drivers
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
#define CONFIG_SYS_SPD_BUS_NUM		0
#define CONFIG_MXC_SPI
#define CONFIG_MXC_GPIO

/* PMIC Controller */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_FSL
#define CONFIG_POWER_FSL_MC13892
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR	0x8
#define CONFIG_RTC_MC13XXX

/* mmc driver */
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR	0
#define CONFIG_SYS_FSL_ESDHC_NUM	1

/*
 * UART (console)
 */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE	UART1_BASE

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX	1

/*
 * Command definition
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_DNS

#define CONFIG_MXC_GPIO

#define CONFIG_NET_RETRY_COUNT	100


#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */

/*
 * Ethernet on SOC (FEC)
 */
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE	FEC_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR	0x1

#define CONFIG_MII
#define CONFIG_DISCOVER_PHY

#define CONFIG_ARP_TIMEOUT	200UL

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP	/* undef to save memory */
#define CONFIG_CMDLINE_EDITING

#define CONFIG_AUTO_COMPLETE

#define CONFIG_SYS_MEMTEST_START	0	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x10000

#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1
#define PHYS_SDRAM_1		CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE	(256 * 1024 * 1024)

#define CONFIG_SYS_SDRAM_BASE		CSD0_BASE_ADDR

#define CONFIG_SYS_GBL_DATA_OFFSET	(LOW_LEVEL_SRAM_STACK - \
						IRAM_BASE_ADDR - \
						GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR		(IRAM_BASE_ADDR + \
					CONFIG_SYS_GBL_DATA_OFFSET)

/*
 * MTD Command for mtdparts
 */
#define CONFIG_MTD_DEVICE
#define CONFIG_FLASH_CFI_MTD
#define CONFIG_MTD_PARTITIONS

/*
 * FLASH and environment organization
 */
#define CONFIG_SYS_FLASH_BASE		CS0_BASE_ADDR
#define CONFIG_SYS_MAX_FLASH_BANKS 1	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512	/* max number of sectors on one chip */
/* Monitor at beginning of flash */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)

#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE

#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
				CONFIG_SYS_MONITOR_LEN)

/*
 * CFI FLASH driver setup
 */
#define CONFIG_SYS_FLASH_CFI		/* Flash memory is CFI compliant */
#define CONFIG_FLASH_CFI_DRIVER

/* A non-standard buffered write algorithm */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* faster */
#define CONFIG_SYS_FLASH_PROTECTION	/* Use hardware sector protection */

/*
 * NAND FLASH driver setup
 */
#define CONFIG_NAND_MXC_V1_1
#define CONFIG_MXC_NAND_REGS_BASE	(NFC_BASE_ADDR)
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		(NFC_BASE_ADDR)
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_LARGEPAGE

#define CONFIG_SYS_NAND_ONFI_DETECTION

/*
 * Default environment and default scripts
 * to update uboot and load kernel
 */

#define CONFIG_HOSTNAME woodburn
#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip_sta=setenv bootargs ${bootargs} "			\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
		"else run addip_sta;fi\0"	\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"addtty=setenv bootargs ${bootargs}"				\
		" console=ttymxc0,${baudrate}\0"			\
	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
	"loadaddr=80800000\0"						\
	"kernel_addr_r=80800000\0"					\
	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
	"ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0"	\
	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr}\0"				\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
		"run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr_r}\0"				\
	"net_self_load=tftp ${kernel_addr_r} ${bootfile};"		\
		"tftp ${ramdisk_addr_r} ${ramdisk_file};\0"		\
	"net_self=if run net_self_load;then "				\
		"run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
		"else echo Images not loades;fi\0"			\
	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0"		\
	"load=tftp ${loadaddr} ${u-boot}\0"				\
	"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0"		\
	"update=protect off ${uboot_addr} +80000;"			\
		"erase ${uboot_addr} +80000;"				\
		"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0"		\
	"upd=if run load;then echo Updating u-boot;if run update;"	\
		"then echo U-Boot updated;"				\
			"else echo Error updating u-boot !;"		\
			"echo Board without bootloader !!;"		\
		"fi;"							\
		"else echo U-Boot not downloaded..exiting;fi\0"		\
	"bootcmd=run net_nfs\0"

#endif				/* __CONFIG_H */
Commit	Line	Data
d81b27a2 SB	1	/*
	2	* (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
	3	*
	4	* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
	5	*
	6	* Configuration for the woodburn board.
	7	*
3765b3e7	8	* SPDX-License-Identifier: GPL-2.0+
d81b27a2 SB	9	*/
	10
	11	#ifndef __WOODBURN_COMMON_CONFIG_H
	12	#define __WOODBURN_COMMON_CONFIG_H
	13
	14	#include <asm/arch/imx-regs.h>
	15
	16	/* High Level Configuration Options */
d81b27a2 SB	17	#define CONFIG_MX35
d81b27a2 SB	18	#define CONFIG_MX35_HCLK_FREQ 24000000
18fb0e3c	19	#define CONFIG_SYS_FSL_CLK
d81b27a2 SB	20
d81b27a2 SB	21	#define CONFIG_SYS_DCACHE_OFF
d81b27a2	22
d81b27a2 SB	23	#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
	24
	25	/* This is required to setup the ESDC controller */
	26
	27	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	28	#define CONFIG_REVISION_TAG
	29	#define CONFIG_SETUP_MEMORY_TAGS
	30	#define CONFIG_INITRD_TAG
	31
	32	/*
	33	* Size of malloc() pool
	34	*/
	35	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
	36
	37	/*
	38	* Hardware drivers
	39	*/
b089d039	40	#define CONFIG_SYS_I2C
b089d039	41	#define CONFIG_SYS_I2C_MXC
03544c66 AA	42	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
03544c66 AA	43	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e	44	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
b089d039	45	#define CONFIG_SYS_SPD_BUS_NUM 0
d81b27a2 SB	46	#define CONFIG_MXC_SPI
	47	#define CONFIG_MXC_GPIO
	48
	49	/* PMIC Controller */
05a860c2 SB	50	#define CONFIG_POWER
	51	#define CONFIG_POWER_I2C
	52	#define CONFIG_POWER_FSL
913702ca	53	#define CONFIG_POWER_FSL_MC13892
d81b27a2 SB	54	#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
	55	#define CONFIG_RTC_MC13XXX
	56
d81b27a2	57	/* mmc driver */
d81b27a2 SB	58	#define CONFIG_FSL_ESDHC
	59	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
	60	#define CONFIG_SYS_FSL_ESDHC_NUM 1
	61
	62	/*
	63	* UART (console)
	64	*/
	65	#define CONFIG_MXC_UART
	66	#define CONFIG_MXC_UART_BASE UART1_BASE
	67
	68	/* allow to overwrite serial and ethaddr */
	69	#define CONFIG_ENV_OVERWRITE
	70	#define CONFIG_CONS_INDEX 1
d81b27a2 SB	71
	72	/*
	73	* Command definition
	74	*/
d81b27a2 SB	75	#define CONFIG_BOOTP_SUBNETMASK
	76	#define CONFIG_BOOTP_GATEWAY
	77	#define CONFIG_BOOTP_DNS
	78
d81b27a2 SB	79	#define CONFIG_MXC_GPIO
	80
	81	#define CONFIG_NET_RETRY_COUNT 100
	82
d81b27a2 SB	83
	84	#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
	85
d81b27a2 SB	86	/*
	87	* Ethernet on SOC (FEC)
	88	*/
	89	#define CONFIG_FEC_MXC
	90	#define IMX_FEC_BASE FEC_BASE_ADDR
d81b27a2 SB	91	#define CONFIG_FEC_MXC_PHYADDR 0x1
	92
	93	#define CONFIG_MII
	94	#define CONFIG_DISCOVER_PHY
	95
	96	#define CONFIG_ARP_TIMEOUT 200UL
	97
	98	/*
	99	* Miscellaneous configurable options
	100	*/
	101	#define CONFIG_SYS_LONGHELP /* undef to save memory */
d81b27a2	102	#define CONFIG_CMDLINE_EDITING
d81b27a2 SB	103
d81b27a2 SB	104	#define CONFIG_AUTO_COMPLETE
d81b27a2 SB	105
	106	#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
	107	#define CONFIG_SYS_MEMTEST_END 0x10000
	108
d81b27a2 SB	109	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
d81b27a2 SB	110
d81b27a2 SB	111	/*
	112	* Physical Memory Map
	113	*/
	114	#define CONFIG_NR_DRAM_BANKS 1
	115	#define PHYS_SDRAM_1 CSD0_BASE_ADDR
	116	#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
	117
	118	#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR
	119
	120	#define CONFIG_SYS_GBL_DATA_OFFSET (LOW_LEVEL_SRAM_STACK - \
	121	IRAM_BASE_ADDR - \
	122	GENERATED_GBL_DATA_SIZE)
	123	#define CONFIG_SYS_INIT_SP_ADDR (IRAM_BASE_ADDR + \
	124	CONFIG_SYS_GBL_DATA_OFFSET)
	125
	126	/*
	127	* MTD Command for mtdparts
	128	*/
d81b27a2 SB	129	#define CONFIG_MTD_DEVICE
	130	#define CONFIG_FLASH_CFI_MTD
	131	#define CONFIG_MTD_PARTITIONS
d81b27a2 SB	132
	133	/*
	134	* FLASH and environment organization
	135	*/
	136	#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
	137	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	138	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
	139	/* Monitor at beginning of flash */
	140	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	141	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
	142
	143	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
	144	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
	145
	146	/* Address and size of Redundant Environment Sector */
	147	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
	148	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	149
	150	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
	151	CONFIG_SYS_MONITOR_LEN)
	152
d81b27a2 SB	153	/*
	154	* CFI FLASH driver setup
	155	*/
	156	#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
	157	#define CONFIG_FLASH_CFI_DRIVER
	158
	159	/* A non-standard buffered write algorithm */
	160	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */
	161	#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
	162
	163	/*
	164	* NAND FLASH driver setup
	165	*/
d81b27a2 SB	166	#define CONFIG_NAND_MXC_V1_1
	167	#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
	168	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	169	#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
	170	#define CONFIG_MXC_NAND_HWECC
	171	#define CONFIG_SYS_NAND_LARGEPAGE
	172
d81b27a2 SB	173	#define CONFIG_SYS_NAND_ONFI_DETECTION
	174
	175	/*
	176	* Default environment and default scripts
	177	* to update uboot and load kernel
	178	*/
d81b27a2 SB	179
	180	#define CONFIG_HOSTNAME woodburn
	181	#define CONFIG_EXTRA_ENV_SETTINGS \
	182	"netdev=eth0\0" \
	183	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	184	"nfsroot=${serverip}:${rootpath}\0" \
	185	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	186	"addip_sta=setenv bootargs ${bootargs} " \
	187	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	188	":${hostname}:${netdev}:off panic=1\0" \
	189	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
	190	"addip=if test -n ${ipdyn};then run addip_dyn;" \
	191	"else run addip_sta;fi\0" \
	192	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	193	"addtty=setenv bootargs ${bootargs}" \
	194	" console=ttymxc0,${baudrate}\0" \
	195	"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
	196	"loadaddr=80800000\0" \
	197	"kernel_addr_r=80800000\0" \
4a8c3f69 AG	198	"hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
	199	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
	200	"ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \
d81b27a2 SB	201	"flash_self=run ramargs addip addtty addmtd addmisc;" \
	202	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	203	"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
	204	"bootm ${kernel_addr}\0" \
	205	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
	206	"run nfsargs addip addtty addmtd addmisc;" \
	207	"bootm ${kernel_addr_r}\0" \
	208	"net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
	209	"tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
	210	"net_self=if run net_self_load;then " \
	211	"run ramargs addip addtty addmtd addmisc;" \
	212	"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
	213	"else echo Images not loades;fi\0" \
4a8c3f69	214	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
d81b27a2	215	"load=tftp ${loadaddr} ${u-boot}\0" \
4a8c3f69	216	"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
d81b27a2 SB	217	"update=protect off ${uboot_addr} +80000;" \
	218	"erase ${uboot_addr} +80000;" \
	219	"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
	220	"upd=if run load;then echo Updating u-boot;if run update;" \
	221	"then echo U-Boot updated;" \
	222	"else echo Error updating u-boot !;" \
	223	"echo Board without bootloader !!;" \
	224	"fi;" \
	225	"else echo U-Boot not downloaded..exiting;fi\0" \
	226	"bootcmd=run net_nfs\0"
	227
	228	#endif /* __CONFIG_H */