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d81b27a2 SB |
1 | /* |
2 | * (C) Copyright 2011, Stefano Babic <sbabic@denx.de> | |
3 | * | |
4 | * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * Configuration for the woodburn board. | |
7 | * | |
3765b3e7 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
d81b27a2 SB |
9 | */ |
10 | ||
11 | #ifndef __WOODBURN_COMMON_CONFIG_H | |
12 | #define __WOODBURN_COMMON_CONFIG_H | |
13 | ||
14 | #include <asm/arch/imx-regs.h> | |
15 | ||
16 | /* High Level Configuration Options */ | |
d81b27a2 SB |
17 | #define CONFIG_MX35 |
18 | #define CONFIG_MX35_HCLK_FREQ 24000000 | |
18fb0e3c | 19 | #define CONFIG_SYS_FSL_CLK |
d81b27a2 SB |
20 | |
21 | #define CONFIG_SYS_DCACHE_OFF | |
d81b27a2 | 22 | |
d81b27a2 SB |
23 | #define CONFIG_MACH_TYPE MACH_TYPE_FLEA3 |
24 | ||
25 | /* This is required to setup the ESDC controller */ | |
26 | ||
27 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
28 | #define CONFIG_REVISION_TAG | |
29 | #define CONFIG_SETUP_MEMORY_TAGS | |
30 | #define CONFIG_INITRD_TAG | |
31 | ||
32 | /* | |
33 | * Size of malloc() pool | |
34 | */ | |
35 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) | |
36 | ||
37 | /* | |
38 | * Hardware drivers | |
39 | */ | |
b089d039 | 40 | #define CONFIG_SYS_I2C |
41 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
42 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
43 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
f8cb101e | 44 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
b089d039 | 45 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
d81b27a2 SB |
46 | #define CONFIG_MXC_SPI |
47 | #define CONFIG_MXC_GPIO | |
48 | ||
49 | /* PMIC Controller */ | |
05a860c2 SB |
50 | #define CONFIG_POWER |
51 | #define CONFIG_POWER_I2C | |
52 | #define CONFIG_POWER_FSL | |
913702ca | 53 | #define CONFIG_POWER_FSL_MC13892 |
d81b27a2 SB |
54 | #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 |
55 | #define CONFIG_RTC_MC13XXX | |
56 | ||
d81b27a2 | 57 | /* mmc driver */ |
d81b27a2 SB |
58 | #define CONFIG_FSL_ESDHC |
59 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
60 | #define CONFIG_SYS_FSL_ESDHC_NUM 1 | |
61 | ||
62 | /* | |
63 | * UART (console) | |
64 | */ | |
65 | #define CONFIG_MXC_UART | |
66 | #define CONFIG_MXC_UART_BASE UART1_BASE | |
67 | ||
68 | /* allow to overwrite serial and ethaddr */ | |
69 | #define CONFIG_ENV_OVERWRITE | |
70 | #define CONFIG_CONS_INDEX 1 | |
d81b27a2 SB |
71 | |
72 | /* | |
73 | * Command definition | |
74 | */ | |
d81b27a2 | 75 | #define CONFIG_CMD_DATE |
d81b27a2 SB |
76 | #define CONFIG_BOOTP_SUBNETMASK |
77 | #define CONFIG_BOOTP_GATEWAY | |
78 | #define CONFIG_BOOTP_DNS | |
79 | ||
80 | #define CONFIG_CMD_NAND | |
d81b27a2 | 81 | |
d81b27a2 SB |
82 | #define CONFIG_MXC_GPIO |
83 | ||
84 | #define CONFIG_NET_RETRY_COUNT 100 | |
85 | ||
d81b27a2 SB |
86 | |
87 | #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ | |
88 | ||
d81b27a2 SB |
89 | /* |
90 | * Ethernet on SOC (FEC) | |
91 | */ | |
92 | #define CONFIG_FEC_MXC | |
93 | #define IMX_FEC_BASE FEC_BASE_ADDR | |
94 | #define CONFIG_PHYLIB | |
95 | #define CONFIG_PHY_MICREL | |
96 | #define CONFIG_FEC_MXC_PHYADDR 0x1 | |
97 | ||
98 | #define CONFIG_MII | |
99 | #define CONFIG_DISCOVER_PHY | |
100 | ||
101 | #define CONFIG_ARP_TIMEOUT 200UL | |
102 | ||
103 | /* | |
104 | * Miscellaneous configurable options | |
105 | */ | |
106 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
d81b27a2 | 107 | #define CONFIG_CMDLINE_EDITING |
d81b27a2 SB |
108 | |
109 | #define CONFIG_AUTO_COMPLETE | |
110 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
111 | /* Print Buffer Size */ | |
112 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
113 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
114 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
115 | ||
116 | #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ | |
117 | #define CONFIG_SYS_MEMTEST_END 0x10000 | |
118 | ||
d81b27a2 SB |
119 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
120 | ||
d81b27a2 SB |
121 | /* |
122 | * Stack sizes | |
123 | * | |
124 | * The stack sizes are set up in start.S using the settings below | |
125 | */ | |
126 | #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ | |
127 | ||
128 | /* | |
129 | * Physical Memory Map | |
130 | */ | |
131 | #define CONFIG_NR_DRAM_BANKS 1 | |
132 | #define PHYS_SDRAM_1 CSD0_BASE_ADDR | |
133 | #define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) | |
134 | ||
135 | #define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR | |
136 | ||
137 | #define CONFIG_SYS_GBL_DATA_OFFSET (LOW_LEVEL_SRAM_STACK - \ | |
138 | IRAM_BASE_ADDR - \ | |
139 | GENERATED_GBL_DATA_SIZE) | |
140 | #define CONFIG_SYS_INIT_SP_ADDR (IRAM_BASE_ADDR + \ | |
141 | CONFIG_SYS_GBL_DATA_OFFSET) | |
142 | ||
143 | /* | |
144 | * MTD Command for mtdparts | |
145 | */ | |
146 | #define CONFIG_CMD_MTDPARTS | |
147 | #define CONFIG_MTD_DEVICE | |
148 | #define CONFIG_FLASH_CFI_MTD | |
149 | #define CONFIG_MTD_PARTITIONS | |
150 | #define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0" | |
151 | #define MTDPARTS_DEFAULT "mtdparts=mxc_nand:50m(root1)," \ | |
152 | "32m(rootfb)," \ | |
153 | "64m(pcache)," \ | |
154 | "64m(app1)," \ | |
155 | "10m(app2),-(spool);" \ | |
156 | "physmap-flash.0:512k(u-boot),64k(env1)," \ | |
157 | "64k(env2),3776k(kernel1),3776k(kernel2)" | |
158 | ||
159 | /* | |
160 | * FLASH and environment organization | |
161 | */ | |
162 | #define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR | |
163 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
164 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
165 | /* Monitor at beginning of flash */ | |
166 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
167 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
168 | ||
169 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) | |
170 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE | |
171 | ||
172 | /* Address and size of Redundant Environment Sector */ | |
173 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) | |
174 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
175 | ||
176 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ | |
177 | CONFIG_SYS_MONITOR_LEN) | |
178 | ||
179 | #define CONFIG_ENV_IS_IN_FLASH | |
180 | ||
181 | /* | |
182 | * CFI FLASH driver setup | |
183 | */ | |
184 | #define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ | |
185 | #define CONFIG_FLASH_CFI_DRIVER | |
186 | ||
187 | /* A non-standard buffered write algorithm */ | |
188 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */ | |
189 | #define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */ | |
190 | ||
191 | /* | |
192 | * NAND FLASH driver setup | |
193 | */ | |
194 | #define CONFIG_NAND_MXC | |
195 | #define CONFIG_NAND_MXC_V1_1 | |
196 | #define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR) | |
197 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
198 | #define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR) | |
199 | #define CONFIG_MXC_NAND_HWECC | |
200 | #define CONFIG_SYS_NAND_LARGEPAGE | |
201 | ||
202 | #if 0 | |
203 | #define CONFIG_MTD_DEBUG | |
204 | #define CONFIG_MTD_DEBUG_VERBOSE 7 | |
205 | #endif | |
206 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
207 | ||
208 | /* | |
209 | * Default environment and default scripts | |
210 | * to update uboot and load kernel | |
211 | */ | |
d81b27a2 SB |
212 | |
213 | #define CONFIG_HOSTNAME woodburn | |
214 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
215 | "netdev=eth0\0" \ | |
216 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
217 | "nfsroot=${serverip}:${rootpath}\0" \ | |
218 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
219 | "addip_sta=setenv bootargs ${bootargs} " \ | |
220 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
221 | ":${hostname}:${netdev}:off panic=1\0" \ | |
222 | "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ | |
223 | "addip=if test -n ${ipdyn};then run addip_dyn;" \ | |
224 | "else run addip_sta;fi\0" \ | |
225 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ | |
226 | "addtty=setenv bootargs ${bootargs}" \ | |
227 | " console=ttymxc0,${baudrate}\0" \ | |
228 | "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ | |
229 | "loadaddr=80800000\0" \ | |
230 | "kernel_addr_r=80800000\0" \ | |
4a8c3f69 AG |
231 | "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ |
232 | "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ | |
233 | "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \ | |
d81b27a2 SB |
234 | "flash_self=run ramargs addip addtty addmtd addmisc;" \ |
235 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
236 | "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ | |
237 | "bootm ${kernel_addr}\0" \ | |
238 | "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ | |
239 | "run nfsargs addip addtty addmtd addmisc;" \ | |
240 | "bootm ${kernel_addr_r}\0" \ | |
241 | "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \ | |
242 | "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \ | |
243 | "net_self=if run net_self_load;then " \ | |
244 | "run ramargs addip addtty addmtd addmisc;" \ | |
245 | "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ | |
246 | "else echo Images not loades;fi\0" \ | |
4a8c3f69 | 247 | "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \ |
d81b27a2 | 248 | "load=tftp ${loadaddr} ${u-boot}\0" \ |
4a8c3f69 | 249 | "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ |
d81b27a2 SB |
250 | "update=protect off ${uboot_addr} +80000;" \ |
251 | "erase ${uboot_addr} +80000;" \ | |
252 | "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ | |
253 | "upd=if run load;then echo Updating u-boot;if run update;" \ | |
254 | "then echo U-Boot updated;" \ | |
255 | "else echo Error updating u-boot !;" \ | |
256 | "echo Board without bootloader !!;" \ | |
257 | "fi;" \ | |
258 | "else echo U-Boot not downloaded..exiting;fi\0" \ | |
259 | "bootcmd=run net_nfs\0" | |
260 | ||
261 | #endif /* __CONFIG_H */ |