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1 | /* |
2 | * (C) Copyright 2009 | |
3 | * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com> | |
4 | * | |
5 | * Copyright (C) 2012 Stefan Roese <sr@denx.de> | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
995b72dd SR |
8 | */ |
9 | ||
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
13 | /* | |
14 | * High Level Configuration Options | |
15 | * (easy to change) | |
16 | */ | |
17 | #define CONFIG_SPEAR600 /* SPEAr600 SoC */ | |
18 | #define CONFIG_X600 /* on X600 board */ | |
5822f5ae | 19 | #define CONFIG_SYS_GENERIC_BOARD |
995b72dd SR |
20 | |
21 | #include <asm/arch/hardware.h> | |
22 | ||
23 | /* Timer, HZ specific defines */ | |
995b72dd SR |
24 | #define CONFIG_SYS_HZ_CLOCK 8300000 |
25 | ||
26 | #define CONFIG_SYS_TEXT_BASE 0x00800040 | |
27 | #define CONFIG_SYS_FLASH_BASE 0xf8000000 | |
28 | /* Reserve 8KiB for SPL */ | |
29 | #define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */ | |
30 | #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO | |
31 | #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ | |
32 | CONFIG_SYS_SPL_LEN) | |
33 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
34 | #define CONFIG_SYS_MONITOR_LEN 0x60000 | |
35 | ||
36 | #define CONFIG_ENV_IS_IN_FLASH | |
37 | ||
38 | /* Serial Configuration (PL011) */ | |
39 | #define CONFIG_SYS_SERIAL0 0xD0000000 | |
40 | #define CONFIG_SYS_SERIAL1 0xD0080000 | |
41 | #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ | |
42 | (void *)CONFIG_SYS_SERIAL1 } | |
43 | #define CONFIG_PL011_SERIAL | |
44 | #define CONFIG_PL011_CLOCK (48 * 1000 * 1000) | |
45 | #define CONFIG_CONS_INDEX 0 | |
46 | #define CONFIG_BAUDRATE 115200 | |
47 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ | |
48 | 57600, 115200 } | |
49 | #define CONFIG_SYS_LOADS_BAUD_CHANGE | |
50 | ||
51 | /* NOR FLASH config options */ | |
52 | #define CONFIG_ST_SMI | |
53 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
54 | #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 | |
55 | #define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE } | |
56 | #define CONFIG_SYS_MAX_FLASH_SECT 128 | |
57 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
58 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) | |
59 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) | |
60 | ||
61 | /* NAND FLASH config options */ | |
62 | #define CONFIG_NAND_FSMC | |
63 | #define CONFIG_SYS_NAND_SELF_INIT | |
64 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
65 | #define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE | |
66 | #define CONFIG_MTD_ECC_SOFT | |
67 | #define CONFIG_SYS_FSMC_NAND_8BIT | |
68 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
69 | ||
70 | /* UBI/UBI config options */ | |
71 | #define CONFIG_MTD_DEVICE | |
72 | #define CONFIG_MTD_PARTITIONS | |
73 | #define CONFIG_RBTREE | |
74 | ||
75 | /* Ethernet config options */ | |
76 | #define CONFIG_MII | |
995b72dd | 77 | #define CONFIG_NET_MULTI |
1a78d28d | 78 | #define CONFIG_PHYLIB |
995b72dd | 79 | #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ |
995b72dd SR |
80 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
81 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
82 | ||
83 | #define CONFIG_SPEAR_GPIO | |
84 | ||
85 | /* I2C config options */ | |
678398b1 SR |
86 | #define CONFIG_SYS_I2C |
87 | #define CONFIG_SYS_I2C_DW | |
f93f589c | 88 | #define CONFIG_SYS_I2C_BASE 0xD0200000 |
995b72dd SR |
89 | #define CONFIG_SYS_I2C_SPEED 400000 |
90 | #define CONFIG_SYS_I2C_SLAVE 0x02 | |
91 | #define CONFIG_I2C_CHIPADDRESS 0x50 | |
92 | ||
93 | #define CONFIG_RTC_M41T62 1 | |
94 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
95 | ||
96 | /* FPGA config options */ | |
97 | #define CONFIG_FPGA | |
98 | #define CONFIG_FPGA_XILINX | |
99 | #define CONFIG_FPGA_SPARTAN3 | |
100 | #define CONFIG_FPGA_COUNT 1 | |
101 | ||
102 | /* | |
103 | * Command support defines | |
104 | */ | |
105 | #define CONFIG_CMD_CACHE | |
106 | #define CONFIG_CMD_DATE | |
107 | #define CONFIG_CMD_DHCP | |
108 | #define CONFIG_CMD_ENV | |
109 | #define CONFIG_CMD_FPGA | |
64e809af | 110 | #define CONFIG_CMD_FPGA_LOADMK |
995b72dd SR |
111 | #define CONFIG_CMD_GPIO |
112 | #define CONFIG_CMD_I2C | |
113 | #define CONFIG_CMD_MEMORY | |
114 | #define CONFIG_CMD_MII | |
115 | #define CONFIG_CMD_MTDPARTS | |
116 | #define CONFIG_CMD_NAND | |
117 | #define CONFIG_CMD_NET | |
118 | #define CONFIG_CMD_PING | |
119 | #define CONFIG_CMD_RUN | |
120 | #define CONFIG_CMD_SAVES | |
121 | #define CONFIG_CMD_UBI | |
122 | #define CONFIG_CMD_UBIFS | |
123 | #define CONFIG_LZO | |
124 | ||
125 | /* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
126 | #include <config_cmd_default.h> | |
127 | ||
128 | #define CONFIG_BOOTDELAY 3 | |
129 | ||
130 | #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ | |
131 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
132 | ||
133 | /* | |
134 | * U-Boot Environment placing definitions. | |
135 | */ | |
136 | #define CONFIG_ENV_SECT_SIZE 0x00010000 | |
137 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ | |
138 | CONFIG_SYS_MONITOR_LEN) | |
139 | #define CONFIG_ENV_SIZE 0x02000 | |
140 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ | |
141 | CONFIG_ENV_SECT_SIZE) | |
142 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
143 | ||
144 | /* Miscellaneous configurable options */ | |
145 | #define CONFIG_ARCH_CPU_INIT | |
146 | #define CONFIG_DISPLAY_CPUINFO | |
147 | #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 | |
148 | #define CONFIG_CMDLINE_TAG | |
149 | #define CONFIG_OF_LIBFDT /* enable passing of devicetree */ | |
150 | #define CONFIG_SETUP_MEMORY_TAGS | |
151 | #define CONFIG_MISC_INIT_R | |
152 | #define CONFIG_BOARD_LATE_INIT | |
153 | #define CONFIG_LOOPW /* enable loopw command */ | |
154 | #define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ | |
155 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
156 | #define CONFIG_AUTOBOOT_KEYED | |
157 | #define CONFIG_AUTOBOOT_STOP_STR " " | |
158 | #define CONFIG_AUTOBOOT_PROMPT \ | |
159 | "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay | |
160 | ||
161 | #define CONFIG_SYS_MEMTEST_START 0x00800000 | |
162 | #define CONFIG_SYS_MEMTEST_END 0x04000000 | |
163 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) | |
164 | #define CONFIG_IDENT_STRING "-SPEAr" | |
165 | #define CONFIG_SYS_LONGHELP | |
166 | #define CONFIG_SYS_PROMPT "X600> " | |
167 | #define CONFIG_CMDLINE_EDITING | |
168 | #define CONFIG_SYS_CBSIZE 256 | |
169 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
170 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
171 | #define CONFIG_SYS_MAXARGS 16 | |
172 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
173 | #define CONFIG_SYS_LOAD_ADDR 0x00800000 | |
174 | #define CONFIG_SYS_CONSOLE_INFO_QUIET | |
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175 | |
176 | /* Use last 2 lwords in internal SRAM for bootcounter */ | |
177 | #define CONFIG_BOOTCOUNT_LIMIT | |
178 | #define CONFIG_SYS_BOOTCOUNT_ADDR 0xd2801ff8 | |
179 | ||
180 | #define CONFIG_HOSTNAME x600 | |
181 | #define CONFIG_UBI_PART ubi0 | |
182 | #define CONFIG_UBIFS_VOLUME rootfs | |
183 | ||
995b72dd SR |
184 | #define MTDIDS_DEFAULT "nand0=nand" |
185 | #define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)" | |
186 | ||
187 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
188 | "u-boot_addr=1000000\0" \ | |
4a8c3f69 | 189 | "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0" \ |
995b72dd | 190 | "load=tftp ${u-boot_addr} ${u-boot}\0" \ |
4a8c3f69 AG |
191 | "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ |
192 | " +${filesize};" \ | |
193 | "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \ | |
194 | "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \ | |
995b72dd | 195 | " ${filesize};" \ |
4a8c3f69 | 196 | "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ |
995b72dd SR |
197 | " +${filesize}\0" \ |
198 | "upd=run load update\0" \ | |
4a8c3f69 AG |
199 | "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \ |
200 | "part=" __stringify(CONFIG_UBI_PART) "\0" \ | |
201 | "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \ | |
995b72dd SR |
202 | "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ |
203 | "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ | |
204 | " ${filesize}\0" \ | |
205 | "upd_ubifs=run load_ubifs update_ubifs\0" \ | |
206 | "init_ubifs=nand erase.part ubi0;ubi part ${part};" \ | |
207 | "ubi create ${vol} 4000000\0" \ | |
208 | "netdev=eth0\0" \ | |
209 | "rootpath=/opt/eldk-4.2/arm\0" \ | |
210 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
211 | "nfsroot=${serverip}:${rootpath}\0" \ | |
212 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
213 | "boot_part=0\0" \ | |
214 | "altbootcmd=if test $boot_part -eq 0;then " \ | |
215 | "echo Switching to partition 1!;" \ | |
216 | "setenv boot_part 1;" \ | |
217 | "else; " \ | |
218 | "echo Switching to partition 0!;" \ | |
219 | "setenv boot_part 0;" \ | |
220 | "fi;" \ | |
221 | "saveenv;boot\0" \ | |
222 | "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \ | |
223 | "root=ubi0:rootfs rootfstype=ubifs\0" \ | |
4a8c3f69 | 224 | "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ |
995b72dd SR |
225 | "kernel_fs=/boot/uImage \0" \ |
226 | "kernel_addr=1000000\0" \ | |
4a8c3f69 AG |
227 | "dtb=" __stringify(CONFIG_HOSTNAME) "/" \ |
228 | __stringify(CONFIG_HOSTNAME) ".dtb\0" \ | |
229 | "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \ | |
995b72dd SR |
230 | "dtb_addr=1800000\0" \ |
231 | "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ | |
232 | "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ | |
233 | "addip=setenv bootargs ${bootargs} " \ | |
234 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
235 | ":${hostname}:${netdev}:off panic=1\0" \ | |
236 | "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \ | |
237 | "${baudrate}\0" \ | |
238 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ | |
239 | "net_nfs=run load_dtb load_kernel; " \ | |
240 | "run nfsargs addip addcon addmtd addmisc;" \ | |
241 | "bootm ${kernel_addr} - ${dtb_addr}\0" \ | |
242 | "mtdids=" MTDIDS_DEFAULT "\0" \ | |
243 | "mtdparts=" MTDPARTS_DEFAULT "\0" \ | |
244 | "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ | |
245 | " addcon addmisc addmtd;" \ | |
246 | "bootm ${kernel_addr} - ${dtb_addr}\0" \ | |
949a7710 | 247 | "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \ |
995b72dd SR |
248 | "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ |
249 | "ubifsload ${dtb_addr} ${dtb_fs};\0" \ | |
250 | "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ | |
251 | "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \ | |
252 | "bootcmd=run nand_ubifs\0" \ | |
253 | "\0" | |
254 | ||
255 | /* Stack sizes */ | |
256 | #define CONFIG_STACKSIZE (512 * 1024) | |
257 | ||
258 | /* Physical Memory Map */ | |
259 | #define CONFIG_NR_DRAM_BANKS 1 | |
260 | #define PHYS_SDRAM_1 0x00000000 | |
261 | #define PHYS_SDRAM_1_MAXSIZE 0x40000000 | |
262 | ||
263 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
264 | #define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000 | |
265 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 | |
266 | ||
267 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
268 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
269 | ||
270 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
271 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
272 | ||
273 | /* | |
274 | * SPL related defines | |
275 | */ | |
995b72dd SR |
276 | #define CONFIG_SPL_TEXT_BASE 0xd2800b00 |
277 | #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear" | |
278 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds" | |
279 | ||
280 | #define CONFIG_SPL_SERIAL_SUPPORT | |
281 | #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */ | |
282 | #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */ | |
283 | #define CONFIG_SPL_NO_PRINTF | |
284 | ||
285 | /* | |
286 | * Please select/define only one of the following | |
287 | * Each definition corresponds to a supported DDR chip. | |
288 | * DDR configuration is based on the following selection | |
289 | */ | |
290 | #define CONFIG_DDR_MT47H64M16 1 | |
291 | #define CONFIG_DDR_MT47H32M16 0 | |
292 | #define CONFIG_DDR_MT47H128M8 0 | |
293 | ||
294 | /* | |
295 | * Synchronous/Asynchronous operation of DDR | |
296 | * | |
297 | * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation | |
298 | * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation | |
299 | * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation | |
300 | */ | |
301 | #define CONFIG_DDR_2HCLK 1 | |
302 | #define CONFIG_DDR_HCLK 0 | |
303 | #define CONFIG_DDR_PLL2 0 | |
304 | ||
305 | /* | |
306 | * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported | |
307 | * or not. Modify/Add to only these macros to define new boot types | |
308 | */ | |
309 | #define USB_BOOT_SUPPORTED 0 | |
310 | #define PCIE_BOOT_SUPPORTED 0 | |
311 | #define SNOR_BOOT_SUPPORTED 1 | |
312 | #define NAND_BOOT_SUPPORTED 1 | |
313 | #define PNOR_BOOT_SUPPORTED 0 | |
314 | #define TFTP_BOOT_SUPPORTED 0 | |
315 | #define UART_BOOT_SUPPORTED 0 | |
316 | #define SPI_BOOT_SUPPORTED 0 | |
317 | #define I2C_BOOT_SUPPORTED 0 | |
318 | #define MMC_BOOT_SUPPORTED 0 | |
319 | ||
320 | #endif /* __CONFIG_H */ |