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995b72dd SR |
1 | /* |
2 | * (C) Copyright 2009 | |
3 | * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com> | |
4 | * | |
2fbdbda1 | 5 | * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de> |
995b72dd | 6 | * |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
995b72dd SR |
8 | */ |
9 | ||
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
13 | /* | |
14 | * High Level Configuration Options | |
15 | * (easy to change) | |
16 | */ | |
17 | #define CONFIG_SPEAR600 /* SPEAr600 SoC */ | |
18 | #define CONFIG_X600 /* on X600 board */ | |
19 | ||
20 | #include <asm/arch/hardware.h> | |
21 | ||
22 | /* Timer, HZ specific defines */ | |
995b72dd SR |
23 | #define CONFIG_SYS_HZ_CLOCK 8300000 |
24 | ||
25 | #define CONFIG_SYS_TEXT_BASE 0x00800040 | |
26 | #define CONFIG_SYS_FLASH_BASE 0xf8000000 | |
27 | /* Reserve 8KiB for SPL */ | |
28 | #define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */ | |
29 | #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO | |
30 | #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ | |
31 | CONFIG_SYS_SPL_LEN) | |
285e266b | 32 | #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE |
995b72dd SR |
33 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
34 | #define CONFIG_SYS_MONITOR_LEN 0x60000 | |
35 | ||
995b72dd SR |
36 | /* Serial Configuration (PL011) */ |
37 | #define CONFIG_SYS_SERIAL0 0xD0000000 | |
38 | #define CONFIG_SYS_SERIAL1 0xD0080000 | |
39 | #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ | |
40 | (void *)CONFIG_SYS_SERIAL1 } | |
41 | #define CONFIG_PL011_SERIAL | |
42 | #define CONFIG_PL011_CLOCK (48 * 1000 * 1000) | |
43 | #define CONFIG_CONS_INDEX 0 | |
995b72dd SR |
44 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ |
45 | 57600, 115200 } | |
46 | #define CONFIG_SYS_LOADS_BAUD_CHANGE | |
47 | ||
48 | /* NOR FLASH config options */ | |
49 | #define CONFIG_ST_SMI | |
50 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
51 | #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 | |
52 | #define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE } | |
53 | #define CONFIG_SYS_MAX_FLASH_SECT 128 | |
54 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
55 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) | |
56 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) | |
57 | ||
58 | /* NAND FLASH config options */ | |
59 | #define CONFIG_NAND_FSMC | |
60 | #define CONFIG_SYS_NAND_SELF_INIT | |
61 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
62 | #define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE | |
63 | #define CONFIG_MTD_ECC_SOFT | |
64 | #define CONFIG_SYS_FSMC_NAND_8BIT | |
65 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
0ddc5a2d | 66 | #define CONFIG_NAND_ECC_BCH |
995b72dd SR |
67 | |
68 | /* UBI/UBI config options */ | |
69 | #define CONFIG_MTD_DEVICE | |
70 | #define CONFIG_MTD_PARTITIONS | |
995b72dd SR |
71 | |
72 | /* Ethernet config options */ | |
73 | #define CONFIG_MII | |
995b72dd | 74 | #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ |
995b72dd | 75 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
995b72dd SR |
76 | |
77 | #define CONFIG_SPEAR_GPIO | |
78 | ||
79 | /* I2C config options */ | |
678398b1 | 80 | #define CONFIG_SYS_I2C |
f93f589c | 81 | #define CONFIG_SYS_I2C_BASE 0xD0200000 |
995b72dd SR |
82 | #define CONFIG_SYS_I2C_SPEED 400000 |
83 | #define CONFIG_SYS_I2C_SLAVE 0x02 | |
84 | #define CONFIG_I2C_CHIPADDRESS 0x50 | |
85 | ||
86 | #define CONFIG_RTC_M41T62 1 | |
87 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
88 | ||
89 | /* FPGA config options */ | |
90 | #define CONFIG_FPGA | |
91 | #define CONFIG_FPGA_XILINX | |
92 | #define CONFIG_FPGA_SPARTAN3 | |
93 | #define CONFIG_FPGA_COUNT 1 | |
94 | ||
285e266b | 95 | /* USB EHCI options */ |
285e266b | 96 | #define CONFIG_USB_EHCI_SPEAR |
285e266b SR |
97 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
98 | ||
285e266b SR |
99 | /* Filesystem support (for USB key) */ |
100 | #define CONFIG_SUPPORT_VFAT | |
285e266b | 101 | |
995b72dd | 102 | |
995b72dd SR |
103 | /* |
104 | * U-Boot Environment placing definitions. | |
105 | */ | |
106 | #define CONFIG_ENV_SECT_SIZE 0x00010000 | |
107 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ | |
108 | CONFIG_SYS_MONITOR_LEN) | |
109 | #define CONFIG_ENV_SIZE 0x02000 | |
110 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ | |
111 | CONFIG_ENV_SECT_SIZE) | |
112 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
113 | ||
114 | /* Miscellaneous configurable options */ | |
115 | #define CONFIG_ARCH_CPU_INIT | |
995b72dd SR |
116 | #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 |
117 | #define CONFIG_CMDLINE_TAG | |
995b72dd SR |
118 | #define CONFIG_SETUP_MEMORY_TAGS |
119 | #define CONFIG_MISC_INIT_R | |
995b72dd | 120 | #define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ |
995b72dd SR |
121 | |
122 | #define CONFIG_SYS_MEMTEST_START 0x00800000 | |
123 | #define CONFIG_SYS_MEMTEST_END 0x04000000 | |
285e266b | 124 | #define CONFIG_SYS_MALLOC_LEN (8 << 20) |
995b72dd | 125 | #define CONFIG_SYS_LONGHELP |
995b72dd | 126 | #define CONFIG_CMDLINE_EDITING |
285e266b | 127 | #define CONFIG_AUTO_COMPLETE |
995b72dd | 128 | #define CONFIG_SYS_LOAD_ADDR 0x00800000 |
995b72dd SR |
129 | |
130 | /* Use last 2 lwords in internal SRAM for bootcounter */ | |
131 | #define CONFIG_BOOTCOUNT_LIMIT | |
2fbdbda1 SR |
132 | #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SRAM_BASE + \ |
133 | CONFIG_SRAM_SIZE) | |
995b72dd SR |
134 | |
135 | #define CONFIG_HOSTNAME x600 | |
136 | #define CONFIG_UBI_PART ubi0 | |
137 | #define CONFIG_UBIFS_VOLUME rootfs | |
138 | ||
995b72dd SR |
139 | #define MTDIDS_DEFAULT "nand0=nand" |
140 | #define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)" | |
141 | ||
142 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
143 | "u-boot_addr=1000000\0" \ | |
4a8c3f69 | 144 | "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0" \ |
995b72dd | 145 | "load=tftp ${u-boot_addr} ${u-boot}\0" \ |
4a8c3f69 AG |
146 | "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ |
147 | " +${filesize};" \ | |
148 | "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \ | |
149 | "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \ | |
995b72dd | 150 | " ${filesize};" \ |
4a8c3f69 | 151 | "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ |
995b72dd SR |
152 | " +${filesize}\0" \ |
153 | "upd=run load update\0" \ | |
4a8c3f69 AG |
154 | "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \ |
155 | "part=" __stringify(CONFIG_UBI_PART) "\0" \ | |
156 | "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \ | |
995b72dd SR |
157 | "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ |
158 | "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ | |
159 | " ${filesize}\0" \ | |
160 | "upd_ubifs=run load_ubifs update_ubifs\0" \ | |
161 | "init_ubifs=nand erase.part ubi0;ubi part ${part};" \ | |
162 | "ubi create ${vol} 4000000\0" \ | |
163 | "netdev=eth0\0" \ | |
164 | "rootpath=/opt/eldk-4.2/arm\0" \ | |
165 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
166 | "nfsroot=${serverip}:${rootpath}\0" \ | |
167 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
168 | "boot_part=0\0" \ | |
169 | "altbootcmd=if test $boot_part -eq 0;then " \ | |
170 | "echo Switching to partition 1!;" \ | |
171 | "setenv boot_part 1;" \ | |
172 | "else; " \ | |
173 | "echo Switching to partition 0!;" \ | |
174 | "setenv boot_part 0;" \ | |
175 | "fi;" \ | |
176 | "saveenv;boot\0" \ | |
177 | "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \ | |
178 | "root=ubi0:rootfs rootfstype=ubifs\0" \ | |
4a8c3f69 | 179 | "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ |
995b72dd SR |
180 | "kernel_fs=/boot/uImage \0" \ |
181 | "kernel_addr=1000000\0" \ | |
4a8c3f69 AG |
182 | "dtb=" __stringify(CONFIG_HOSTNAME) "/" \ |
183 | __stringify(CONFIG_HOSTNAME) ".dtb\0" \ | |
184 | "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \ | |
995b72dd SR |
185 | "dtb_addr=1800000\0" \ |
186 | "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ | |
187 | "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ | |
188 | "addip=setenv bootargs ${bootargs} " \ | |
189 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
190 | ":${hostname}:${netdev}:off panic=1\0" \ | |
191 | "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \ | |
192 | "${baudrate}\0" \ | |
193 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ | |
194 | "net_nfs=run load_dtb load_kernel; " \ | |
195 | "run nfsargs addip addcon addmtd addmisc;" \ | |
196 | "bootm ${kernel_addr} - ${dtb_addr}\0" \ | |
197 | "mtdids=" MTDIDS_DEFAULT "\0" \ | |
198 | "mtdparts=" MTDPARTS_DEFAULT "\0" \ | |
199 | "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ | |
200 | " addcon addmisc addmtd;" \ | |
201 | "bootm ${kernel_addr} - ${dtb_addr}\0" \ | |
949a7710 | 202 | "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \ |
995b72dd SR |
203 | "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ |
204 | "ubifsload ${dtb_addr} ${dtb_fs};\0" \ | |
205 | "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ | |
206 | "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \ | |
207 | "bootcmd=run nand_ubifs\0" \ | |
208 | "\0" | |
209 | ||
995b72dd SR |
210 | /* Physical Memory Map */ |
211 | #define CONFIG_NR_DRAM_BANKS 1 | |
212 | #define PHYS_SDRAM_1 0x00000000 | |
213 | #define PHYS_SDRAM_1_MAXSIZE 0x40000000 | |
214 | ||
215 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
2fbdbda1 SR |
216 | #define CONFIG_SRAM_BASE 0xd2800000 |
217 | /* Preserve the last 2 lwords for the boot-counter */ | |
218 | #define CONFIG_SRAM_SIZE ((8 << 10) - 0x8) | |
219 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE | |
220 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE | |
995b72dd SR |
221 | |
222 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
223 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
224 | ||
225 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
226 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
227 | ||
228 | /* | |
229 | * SPL related defines | |
230 | */ | |
2fbdbda1 SR |
231 | #define CONFIG_SPL_TEXT_BASE 0xd2800b00 |
232 | #define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00) | |
995b72dd | 233 | #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear" |
995b72dd | 234 | |
2fbdbda1 | 235 | #define CONFIG_SPL_FRAMEWORK |
995b72dd SR |
236 | |
237 | /* | |
238 | * Please select/define only one of the following | |
239 | * Each definition corresponds to a supported DDR chip. | |
240 | * DDR configuration is based on the following selection | |
241 | */ | |
242 | #define CONFIG_DDR_MT47H64M16 1 | |
243 | #define CONFIG_DDR_MT47H32M16 0 | |
244 | #define CONFIG_DDR_MT47H128M8 0 | |
245 | ||
246 | /* | |
247 | * Synchronous/Asynchronous operation of DDR | |
248 | * | |
249 | * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation | |
250 | * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation | |
251 | * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation | |
252 | */ | |
253 | #define CONFIG_DDR_2HCLK 1 | |
254 | #define CONFIG_DDR_HCLK 0 | |
255 | #define CONFIG_DDR_PLL2 0 | |
256 | ||
257 | /* | |
258 | * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported | |
259 | * or not. Modify/Add to only these macros to define new boot types | |
260 | */ | |
261 | #define USB_BOOT_SUPPORTED 0 | |
262 | #define PCIE_BOOT_SUPPORTED 0 | |
263 | #define SNOR_BOOT_SUPPORTED 1 | |
264 | #define NAND_BOOT_SUPPORTED 1 | |
265 | #define PNOR_BOOT_SUPPORTED 0 | |
266 | #define TFTP_BOOT_SUPPORTED 0 | |
267 | #define UART_BOOT_SUPPORTED 0 | |
268 | #define SPI_BOOT_SUPPORTED 0 | |
269 | #define I2C_BOOT_SUPPORTED 0 | |
270 | #define MMC_BOOT_SUPPORTED 0 | |
271 | ||
272 | #endif /* __CONFIG_H */ |