[thirdparty/u-boot.git] / include / configs / x600.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2009, STMicroelectronics - All Rights Reserved
 * Author(s): Vipin Kumar, <vipin.kumar@st.com> for STMicroelectronics.
 *
 * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de>
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_SPEAR600				/* SPEAr600 SoC */
#define CONFIG_X600				/* on X600 board */

#include <asm/arch/hardware.h>

/* Timer, HZ specific defines */
#define CONFIG_SYS_HZ_CLOCK			8300000

#define CONFIG_SYS_FLASH_BASE			0xf8000000
/* Reserve 8KiB for SPL */
#define CONFIG_SPL_PAD_TO			8192	/* decimal for 'dd' */
#define CONFIG_SYS_SPL_LEN			CONFIG_SPL_PAD_TO
#define CONFIG_SYS_UBOOT_BASE			(CONFIG_SYS_FLASH_BASE + \
						 CONFIG_SYS_SPL_LEN)
#define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN			0x60000

/* Serial Configuration (PL011) */
#define CONFIG_SYS_SERIAL0			0xD0000000
#define CONFIG_SYS_SERIAL1			0xD0080000
#define CONFIG_PL01x_PORTS			{ (void *)CONFIG_SYS_SERIAL0, \
						(void *)CONFIG_SYS_SERIAL1 }
#define CONFIG_PL011_CLOCK			(48 * 1000 * 1000)
#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, \
						  57600, 115200 }
#define CONFIG_SYS_LOADS_BAUD_CHANGE

/* NOR FLASH config options */
#define CONFIG_ST_SMI
#define CONFIG_SYS_MAX_FLASH_BANKS		1
#define CONFIG_SYS_FLASH_BANK_SIZE		0x01000000
#define CONFIG_SYS_FLASH_ADDR_BASE		{ CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_MAX_FLASH_SECT		128
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_ERASE_TOUT		(3 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT		(3 * CONFIG_SYS_HZ)

/* NAND FLASH config options */
#define CONFIG_NAND_FSMC
#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define CONFIG_SYS_NAND_BASE			CONFIG_FSMC_NAND_BASE
#define CONFIG_MTD_ECC_SOFT
#define CONFIG_SYS_FSMC_NAND_8BIT
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_NAND_ECC_BCH

/* UBI/UBI config options */

/* Ethernet config options */
#define CONFIG_PHY_RESET_DELAY			10000		/* in usec */

#define CONFIG_SPEAR_GPIO

/* I2C config options */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_BASE			0xD0200000
#define CONFIG_SYS_I2C_SPEED			400000
#define CONFIG_SYS_I2C_SLAVE			0x02
#define CONFIG_I2C_CHIPADDRESS			0x50

#define CONFIG_SYS_I2C_RTC_ADDR	0x68

/* FPGA config options */
#define CONFIG_FPGA_COUNT	1

/* USB EHCI options */
#define CONFIG_USB_EHCI_SPEAR
#define CONFIG_USB_MAX_CONTROLLER_COUNT	2

/*
 * U-Boot Environment placing definitions.
 */

/* Miscellaneous configurable options */
#define CONFIG_BOOT_PARAMS_ADDR			0x00000100
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS

#define CONFIG_SYS_MALLOC_LEN			(8 << 20)
#define CONFIG_SYS_LOAD_ADDR			0x00800000

#define CONFIG_HOSTNAME				"x600"
#define CONFIG_UBI_PART				ubi0
#define CONFIG_UBIFS_VOLUME			rootfs

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"u-boot_addr=1000000\0"						\
	"u-boot=" CONFIG_HOSTNAME "/u-boot.spr\0"		\
	"load=tftp ${u-boot_addr} ${u-boot}\0"				\
	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
		" +${filesize};"					\
		"erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
		"cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \
		" ${filesize};"						\
		"protect on " __stringify(CONFIG_SYS_MONITOR_BASE)	\
		" +${filesize}\0"					\
	"upd=run load update\0"						\
	"ubifs=" CONFIG_HOSTNAME "/ubifs.img\0"		\
	"part=" __stringify(CONFIG_UBI_PART) "\0"			\
	"vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0"			\
	"load_ubifs=tftp ${kernel_addr} ${ubifs}\0"			\
	"update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}"	\
		" ${filesize}\0"					\
	"upd_ubifs=run load_ubifs update_ubifs\0"			\
	"init_ubifs=nand erase.part ubi0;ubi part ${part};"		\
		"ubi create ${vol} 4000000\0"				\
	"netdev=eth0\0"							\
	"rootpath=/opt/eldk-4.2/arm\0"					\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"boot_part=0\0"							\
	"altbootcmd=if test $boot_part -eq 0;then "			\
			"echo Switching to partition 1!;"		\
			"setenv boot_part 1;"				\
		"else; "						\
			"echo Switching to partition 0!;"		\
			"setenv boot_part 0;"				\
		"fi;"							\
		"saveenv;boot\0"					\
	"ubifsargs=set bootargs ubi.mtd=ubi${boot_part} "		\
		"root=ubi0:rootfs rootfstype=ubifs\0"			\
	"kernel=" CONFIG_HOSTNAME "/uImage\0"		\
	"kernel_fs=/boot/uImage \0"					\
	"kernel_addr=1000000\0"						\
	"dtb=" CONFIG_HOSTNAME "/"				\
		CONFIG_HOSTNAME ".dtb\0"			\
	"dtb_fs=/boot/" CONFIG_HOSTNAME ".dtb\0"		\
	"dtb_addr=1800000\0"						\
	"load_kernel=tftp ${kernel_addr} ${kernel}\0"			\
	"load_dtb=tftp ${dtb_addr} ${dtb}\0"				\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addcon=setenv bootargs ${bootargs} console=ttyAMA0,"		\
		"${baudrate}\0"						\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"net_nfs=run load_dtb load_kernel; "				\
		"run nfsargs addip addcon addmtd addmisc;"		\
		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"					\
	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"				\
	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip"		\
		" addcon addmisc addmtd;"				\
		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
	"ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0"	\
	"ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};"		\
		"ubifsload ${dtb_addr} ${dtb_fs};\0"			\
	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon "	\
		"addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0"	\
	"bootcmd=run nand_ubifs\0"					\
	"\0"

/* Physical Memory Map */
#define PHYS_SDRAM_1				0x00000000
#define PHYS_SDRAM_1_MAXSIZE			0x40000000

#define CONFIG_SYS_SDRAM_BASE			PHYS_SDRAM_1
#define CONFIG_SRAM_BASE			0xd2800000
/* Preserve the last 2 lwords for the boot-counter */
#define CONFIG_SRAM_SIZE			((8 << 10) - 0x8)
#define CONFIG_SYS_INIT_RAM_ADDR		CONFIG_SRAM_BASE
#define CONFIG_SYS_INIT_RAM_SIZE		CONFIG_SRAM_SIZE

#define CONFIG_SYS_INIT_SP_OFFSET		\
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

#define CONFIG_SYS_INIT_SP_ADDR			\
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

/*
 * SPL related defines
 */
#define CONFIG_SPL_MAX_SIZE		(CONFIG_SRAM_SIZE - 0xb00)
#define	CONFIG_SPL_START_S_PATH	"arch/arm/cpu/arm926ejs/spear"

/*
 * Please select/define only one of the following
 * Each definition corresponds to a supported DDR chip.
 * DDR configuration is based on the following selection
 */
#define CONFIG_DDR_MT47H64M16		1
#define CONFIG_DDR_MT47H32M16		0
#define CONFIG_DDR_MT47H128M8		0

/*
 * Synchronous/Asynchronous operation of DDR
 *
 * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
 * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
 * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
 */
#define CONFIG_DDR_2HCLK		1
#define CONFIG_DDR_HCLK			0
#define CONFIG_DDR_PLL2			0

/*
 * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
 * or not. Modify/Add to only these macros to define new boot types
 */
#define USB_BOOT_SUPPORTED		0
#define PCIE_BOOT_SUPPORTED		0
#define SNOR_BOOT_SUPPORTED		1
#define NAND_BOOT_SUPPORTED		1
#define PNOR_BOOT_SUPPORTED		0
#define TFTP_BOOT_SUPPORTED		0
#define UART_BOOT_SUPPORTED		0
#define SPI_BOOT_SUPPORTED		0
#define I2C_BOOT_SUPPORTED		0
#define MMC_BOOT_SUPPORTED		0

#endif  /* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
995b72dd	2	/*
e36591c3 PC	3	* Copyright (C) 2009, STMicroelectronics - All Rights Reserved
e36591c3 PC	4	* Author(s): Vipin Kumar, <vipin.kumar@st.com> for STMicroelectronics.
995b72dd	5	*
2fbdbda1	6	* Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de>
995b72dd SR	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	/*
	13	* High Level Configuration Options
	14	* (easy to change)
	15	*/
	16	#define CONFIG_SPEAR600 /* SPEAr600 SoC */
	17	#define CONFIG_X600 /* on X600 board */
	18
	19	#include <asm/arch/hardware.h>
	20
	21	/* Timer, HZ specific defines */
995b72dd SR	22	#define CONFIG_SYS_HZ_CLOCK 8300000
995b72dd SR	23
995b72dd SR	24	#define CONFIG_SYS_FLASH_BASE 0xf8000000
	25	/* Reserve 8KiB for SPL */
	26	#define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */
	27	#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
	28	#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
	29	CONFIG_SYS_SPL_LEN)
	30	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	31	#define CONFIG_SYS_MONITOR_LEN 0x60000
	32
995b72dd SR	33	/* Serial Configuration (PL011) */
	34	#define CONFIG_SYS_SERIAL0 0xD0000000
	35	#define CONFIG_SYS_SERIAL1 0xD0080000
	36	#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \
	37	(void *)CONFIG_SYS_SERIAL1 }
995b72dd	38	#define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
995b72dd SR	39	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
	40	57600, 115200 }
	41	#define CONFIG_SYS_LOADS_BAUD_CHANGE
	42
	43	/* NOR FLASH config options */
	44	#define CONFIG_ST_SMI
	45	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	46	#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
	47	#define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE }
	48	#define CONFIG_SYS_MAX_FLASH_SECT 128
	49	#define CONFIG_SYS_FLASH_EMPTY_INFO
	50	#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
	51	#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
	52
	53	/* NAND FLASH config options */
	54	#define CONFIG_NAND_FSMC
	55	#define CONFIG_SYS_NAND_SELF_INIT
	56	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	57	#define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE
	58	#define CONFIG_MTD_ECC_SOFT
	59	#define CONFIG_SYS_FSMC_NAND_8BIT
	60	#define CONFIG_SYS_NAND_ONFI_DETECTION
0ddc5a2d	61	#define CONFIG_NAND_ECC_BCH
995b72dd SR	62
995b72dd SR	63	/* UBI/UBI config options */
995b72dd SR	64
995b72dd SR	65	/* Ethernet config options */
995b72dd	66	#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
995b72dd SR	67
	68	#define CONFIG_SPEAR_GPIO
	69
	70	/* I2C config options */
678398b1	71	#define CONFIG_SYS_I2C
f93f589c	72	#define CONFIG_SYS_I2C_BASE 0xD0200000
995b72dd SR	73	#define CONFIG_SYS_I2C_SPEED 400000
	74	#define CONFIG_SYS_I2C_SLAVE 0x02
	75	#define CONFIG_I2C_CHIPADDRESS 0x50
	76
995b72dd SR	77	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	78
	79	/* FPGA config options */
995b72dd SR	80	#define CONFIG_FPGA_COUNT 1
995b72dd SR	81
285e266b	82	/* USB EHCI options */
285e266b	83	#define CONFIG_USB_EHCI_SPEAR
285e266b SR	84	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
285e266b SR	85
995b72dd SR	86	/*
	87	* U-Boot Environment placing definitions.
	88	*/
995b72dd SR	89
995b72dd SR	90	/* Miscellaneous configurable options */
995b72dd SR	91	#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
995b72dd SR	92	#define CONFIG_CMDLINE_TAG
995b72dd	93	#define CONFIG_SETUP_MEMORY_TAGS
995b72dd	94
285e266b	95	#define CONFIG_SYS_MALLOC_LEN (8 << 20)
995b72dd	96	#define CONFIG_SYS_LOAD_ADDR 0x00800000
995b72dd	97
5bc0543d	98	#define CONFIG_HOSTNAME "x600"
995b72dd SR	99	#define CONFIG_UBI_PART ubi0
	100	#define CONFIG_UBIFS_VOLUME rootfs
	101
995b72dd SR	102	#define CONFIG_EXTRA_ENV_SETTINGS \
995b72dd SR	103	"u-boot_addr=1000000\0" \
5bc0543d	104	"u-boot=" CONFIG_HOSTNAME "/u-boot.spr\0" \
995b72dd	105	"load=tftp ${u-boot_addr} ${u-boot}\0" \
4a8c3f69 AG	106	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
	107	" +${filesize};" \
	108	"erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
	109	"cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \
995b72dd	110	" ${filesize};" \
4a8c3f69	111	"protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
995b72dd SR	112	" +${filesize}\0" \
995b72dd SR	113	"upd=run load update\0" \
5bc0543d	114	"ubifs=" CONFIG_HOSTNAME "/ubifs.img\0" \
4a8c3f69 AG	115	"part=" __stringify(CONFIG_UBI_PART) "\0" \
4a8c3f69 AG	116	"vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \
995b72dd SR	117	"load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \
	118	"update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \
	119	" ${filesize}\0" \
	120	"upd_ubifs=run load_ubifs update_ubifs\0" \
	121	"init_ubifs=nand erase.part ubi0;ubi part ${part};" \
	122	"ubi create ${vol} 4000000\0" \
	123	"netdev=eth0\0" \
	124	"rootpath=/opt/eldk-4.2/arm\0" \
	125	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	126	"nfsroot=${serverip}:${rootpath}\0" \
	127	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	128	"boot_part=0\0" \
	129	"altbootcmd=if test $boot_part -eq 0;then " \
	130	"echo Switching to partition 1!;" \
	131	"setenv boot_part 1;" \
	132	"else; " \
	133	"echo Switching to partition 0!;" \
	134	"setenv boot_part 0;" \
	135	"fi;" \
	136	"saveenv;boot\0" \
	137	"ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \
	138	"root=ubi0:rootfs rootfstype=ubifs\0" \
5bc0543d	139	"kernel=" CONFIG_HOSTNAME "/uImage\0" \
995b72dd SR	140	"kernel_fs=/boot/uImage \0" \
995b72dd SR	141	"kernel_addr=1000000\0" \
5bc0543d MS	142	"dtb=" CONFIG_HOSTNAME "/" \
	143	CONFIG_HOSTNAME ".dtb\0" \
	144	"dtb_fs=/boot/" CONFIG_HOSTNAME ".dtb\0" \
995b72dd SR	145	"dtb_addr=1800000\0" \
	146	"load_kernel=tftp ${kernel_addr} ${kernel}\0" \
	147	"load_dtb=tftp ${dtb_addr} ${dtb}\0" \
	148	"addip=setenv bootargs ${bootargs} " \
	149	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	150	":${hostname}:${netdev}:off panic=1\0" \
	151	"addcon=setenv bootargs ${bootargs} console=ttyAMA0," \
	152	"${baudrate}\0" \
	153	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	154	"net_nfs=run load_dtb load_kernel; " \
	155	"run nfsargs addip addcon addmtd addmisc;" \
	156	"bootm ${kernel_addr} - ${dtb_addr}\0" \
43ede0bc TR	157	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
43ede0bc TR	158	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
995b72dd SR	159	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \
	160	" addcon addmisc addmtd;" \
	161	"bootm ${kernel_addr} - ${dtb_addr}\0" \
949a7710	162	"ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \
995b72dd SR	163	"ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \
	164	"ubifsload ${dtb_addr} ${dtb_fs};\0" \
	165	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \
	166	"addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \
	167	"bootcmd=run nand_ubifs\0" \
	168	"\0"
	169
995b72dd	170	/* Physical Memory Map */
995b72dd SR	171	#define PHYS_SDRAM_1 0x00000000
	172	#define PHYS_SDRAM_1_MAXSIZE 0x40000000
	173
	174	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
2fbdbda1 SR	175	#define CONFIG_SRAM_BASE 0xd2800000
	176	/* Preserve the last 2 lwords for the boot-counter */
	177	#define CONFIG_SRAM_SIZE ((8 << 10) - 0x8)
	178	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE
	179	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE
995b72dd SR	180
	181	#define CONFIG_SYS_INIT_SP_OFFSET \
	182	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	183
	184	#define CONFIG_SYS_INIT_SP_ADDR \
	185	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	186
	187	/*
	188	* SPL related defines
	189	*/
2fbdbda1	190	#define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00)
995b72dd	191	#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear"
995b72dd	192
995b72dd SR	193	/*
	194	* Please select/define only one of the following
	195	* Each definition corresponds to a supported DDR chip.
	196	* DDR configuration is based on the following selection
	197	*/
	198	#define CONFIG_DDR_MT47H64M16 1
	199	#define CONFIG_DDR_MT47H32M16 0
	200	#define CONFIG_DDR_MT47H128M8 0
	201
	202	/*
	203	* Synchronous/Asynchronous operation of DDR
	204	*
	205	* Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
	206	* Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
	207	* Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
	208	*/
	209	#define CONFIG_DDR_2HCLK 1
	210	#define CONFIG_DDR_HCLK 0
	211	#define CONFIG_DDR_PLL2 0
	212
	213	/*
	214	* xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
	215	* or not. Modify/Add to only these macros to define new boot types
	216	*/
	217	#define USB_BOOT_SUPPORTED 0
	218	#define PCIE_BOOT_SUPPORTED 0
	219	#define SNOR_BOOT_SUPPORTED 1
	220	#define NAND_BOOT_SUPPORTED 1
	221	#define PNOR_BOOT_SUPPORTED 0
	222	#define TFTP_BOOT_SUPPORTED 0
	223	#define UART_BOOT_SUPPORTED 0
	224	#define SPI_BOOT_SUPPORTED 0
	225	#define I2C_BOOT_SUPPORTED 0
	226	#define MMC_BOOT_SUPPORTED 0
	227
	228	#endif /* __CONFIG_H */