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4ec3a7f0 | 1 | /* |
414eec35 WD |
2 | * (C) Copyright 2004-2005 |
3 | * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> | |
4 | * | |
4ec3a7f0 WD |
5 | * (C) Copyright 2004 |
6 | * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com | |
7 | * | |
8 | * (C) Copyright 2002 | |
9 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.ne | |
10 | * | |
11 | * (C) Copyright 2002 | |
12 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
13 | * Marius Groeger <mgroeger@sysgo.de> | |
14 | * | |
15 | * Configuation settings for the xaeniax board. | |
16 | * | |
3765b3e7 | 17 | * SPDX-License-Identifier: GPL-2.0+ |
4ec3a7f0 WD |
18 | */ |
19 | ||
20 | #ifndef __CONFIG_H | |
21 | #define __CONFIG_H | |
22 | ||
4ec3a7f0 WD |
23 | /* |
24 | * High Level Configuration Options | |
25 | * (easy to change) | |
26 | */ | |
abc20aba | 27 | #define CONFIG_CPU_PXA25X 1 /* This is an PXA255 CPU */ |
4ec3a7f0 | 28 | #define CONFIG_XAENIAX 1 /* on a xaeniax board */ |
1123d412 | 29 | #define CONFIG_SYS_TEXT_BASE 0x0 |
4ec3a7f0 | 30 | |
9660e442 | 31 | #define CONFIG_BOARD_LATE_INIT |
4ec3a7f0 | 32 | |
b3acb6cd | 33 | /* we will never enable dcache, because we have to setup MMU first */ |
e47f2db5 | 34 | #define CONFIG_SYS_DCACHE_OFF |
b3acb6cd | 35 | |
4ec3a7f0 WD |
36 | /* |
37 | * select serial console configuration | |
38 | */ | |
379be585 | 39 | #define CONFIG_PXA_SERIAL |
4ec3a7f0 | 40 | #define CONFIG_BTUART 1 /* we use BTUART on XAENIAX */ |
ce6971cd | 41 | #define CONFIG_CONS_INDEX 4 |
4ec3a7f0 WD |
42 | |
43 | /* allow to overwrite serial and ethaddr */ | |
44 | #define CONFIG_ENV_OVERWRITE | |
45 | ||
414eec35 WD |
46 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
47 | ||
4ec3a7f0 WD |
48 | #define CONFIG_BAUDRATE 115200 |
49 | ||
079a136c JL |
50 | /* |
51 | * BOOTP options | |
52 | */ | |
53 | #define CONFIG_BOOTP_BOOTFILESIZE | |
54 | #define CONFIG_BOOTP_BOOTPATH | |
55 | #define CONFIG_BOOTP_GATEWAY | |
56 | #define CONFIG_BOOTP_HOSTNAME | |
57 | ||
58 | ||
dca3b3d6 JL |
59 | /* |
60 | * Command line configuration. | |
61 | */ | |
62 | #include <config_cmd_default.h> | |
63 | ||
64 | #define CONFIG_CMD_DHCP | |
65 | #define CONFIG_CMD_DIAG | |
66 | #define CONFIG_CMD_NFS | |
67 | #define CONFIG_CMD_SDRAM | |
68 | #define CONFIG_CMD_SNTP | |
69 | ||
70 | #undef CONFIG_CMD_DTT | |
71 | ||
4ec3a7f0 WD |
72 | |
73 | #define CONFIG_ETHADDR 08:00:3e:26:0a:5b | |
74 | #define CONFIG_NETMASK 255.255.255.0 | |
75 | #define CONFIG_IPADDR 192.168.68.201 | |
76 | #define CONFIG_SERVERIP 192.168.68.62 | |
77 | ||
78 | #define CONFIG_BOOTDELAY 3 | |
79 | #define CONFIG_BOOTCOMMAND "bootm 0x00100000" | |
80 | #define CONFIG_BOOTARGS "console=ttyS1,115200" | |
14699a22 | 81 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
53677ef1 | 82 | #define CONFIG_SETUP_MEMORY_TAGS 1 |
14699a22 | 83 | #define CONFIG_INITRD_TAG 1 |
4ec3a7f0 | 84 | |
dca3b3d6 | 85 | #if defined(CONFIG_CMD_KGDB) |
4ec3a7f0 | 86 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
4ec3a7f0 WD |
87 | #endif |
88 | ||
89 | /* | |
90 | * Size of malloc() pool; this lives below the uppermost 128 KiB which are | |
91 | * used for the RAM copy of the uboot code | |
92 | */ | |
6d0f6bcf | 93 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
4ec3a7f0 WD |
94 | |
95 | /* | |
96 | * Miscellaneous configurable options | |
97 | */ | |
6d0f6bcf JCPV |
98 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
99 | #define CONFIG_SYS_HUSH_PARSER 1 | |
4ec3a7f0 | 100 | |
4ec3a7f0 | 101 | |
6d0f6bcf JCPV |
102 | #ifdef CONFIG_SYS_HUSH_PARSER |
103 | #define CONFIG_SYS_PROMPT "u-boot$ " /* Monitor Command Prompt */ | |
4ec3a7f0 | 104 | #else |
6d0f6bcf | 105 | #define CONFIG_SYS_PROMPT "u-boot=> " /* Monitor Command Prompt */ |
4ec3a7f0 | 106 | #endif |
6d0f6bcf JCPV |
107 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
108 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
109 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
110 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
111 | #define CONFIG_SYS_DEVICE_NULLDEV 1 | |
4ec3a7f0 | 112 | |
6d0f6bcf JCPV |
113 | #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ |
114 | #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ | |
4ec3a7f0 | 115 | |
6d0f6bcf | 116 | #define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */ |
4ec3a7f0 | 117 | |
6d0f6bcf | 118 | #define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */ |
4ec3a7f0 WD |
119 | |
120 | /* | |
121 | * Physical Memory Map | |
122 | */ | |
123 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks (partition) of DRAM */ | |
124 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ | |
125 | #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ | |
126 | #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ | |
127 | #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ | |
128 | #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ | |
129 | #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ | |
130 | #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ | |
131 | #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ | |
132 | ||
133 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
134 | #define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ | |
135 | #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ | |
136 | #define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ | |
137 | #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ | |
138 | ||
6d0f6bcf JCPV |
139 | #define CONFIG_SYS_DRAM_BASE 0xa0000000 |
140 | #define CONFIG_SYS_DRAM_SIZE 0x04000000 | |
4ec3a7f0 | 141 | |
6d0f6bcf | 142 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
4ec3a7f0 | 143 | |
6ef6eb91 | 144 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
00d5ec93 | 145 | #define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 |
6ef6eb91 | 146 | |
4ec3a7f0 WD |
147 | /* |
148 | * FLASH and environment organization | |
149 | */ | |
6d0f6bcf JCPV |
150 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
151 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ | |
4ec3a7f0 WD |
152 | |
153 | /* timeout values are in ticks */ | |
6d0f6bcf JCPV |
154 | #define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
155 | #define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ | |
4ec3a7f0 WD |
156 | |
157 | /* FIXME */ | |
5a1aceb0 | 158 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
159 | #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector */ |
160 | #define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ | |
4ec3a7f0 | 161 | |
4ec3a7f0 WD |
162 | /* |
163 | * SMSC91C111 Network Card | |
164 | */ | |
7194ab80 | 165 | #define CONFIG_SMC91111 1 |
1f6d4258 | 166 | #define CONFIG_SMC91111_BASE 0x10000300 /* chip select 3 */ |
4ec3a7f0 WD |
167 | #define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */ |
168 | #undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ | |
169 | #undef CONFIG_SHOW_ACTIVITY | |
170 | #define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ | |
171 | ||
172 | /* | |
173 | * GPIO settings | |
174 | */ | |
175 | ||
176 | /* | |
177 | * GP05 == nUSBReset is 1 | |
178 | * GP10 == CFReset is 1 | |
179 | * GP13 == nCFDataEnable is 1 | |
180 | * GP14 == nCFAddrEnable is 1 | |
181 | * GP15 == nCS1 is 1 | |
182 | * GP21 == ComBrdReset is 1 | |
183 | * GP24 == SFRM is 1 | |
184 | * GP25 == TXD is 1 | |
185 | * GP31 == SYNC is 1 | |
186 | * GP33 == nCS5 is 1 | |
187 | * GP39 == FFTXD is 1 | |
188 | * GP41 == RTS is 1 | |
189 | * GP43 == BTTXD is 1 | |
190 | * GP45 == BTRTS is 1 | |
191 | * GP47 == TXD is 1 | |
192 | * GP48 == nPOE is 1 | |
193 | * GP49 == nPWE is 1 | |
194 | * GP50 == nPIOR is 1 | |
195 | * GP51 == nPIOW is 1 | |
196 | * GP52 == nPCE[1] is 1 | |
197 | * GP53 == nPCE[2] is 1 | |
198 | * GP54 == nPSKTSEL is 1 | |
199 | * GP55 == nPREG is 1 | |
200 | * GP78 == nCS2 is 1 | |
201 | * GP79 == nCS3 is 1 | |
202 | * GP80 == nCS4 is 1 | |
203 | * GP82 == NSSPSFRM is 1 | |
204 | * GP83 == NSSPTXD is 1 | |
205 | */ | |
6d0f6bcf JCPV |
206 | #define CONFIG_SYS_GPSR0_VAL 0x8320E420 |
207 | #define CONFIG_SYS_GPSR1_VAL 0x00FFAA82 | |
208 | #define CONFIG_SYS_GPSR2_VAL 0x000DC000 | |
4ec3a7f0 WD |
209 | |
210 | /* | |
211 | * GP03 == LANReset is 0 | |
212 | * GP06 == USBWakeUp is 0 | |
213 | * GP11 == USBControl is 0 | |
214 | * GP12 == Buzzer is 0 | |
215 | * GP16 == PWM0 is 0 | |
216 | * GP17 == PWM1 is 0 | |
217 | * GP23 == SCLK is 0 | |
218 | * GP30 == SDATA_OUT is 0 | |
219 | * GP81 == NSSPCLK is 0 | |
220 | */ | |
6d0f6bcf JCPV |
221 | #define CONFIG_SYS_GPCR0_VAL 0x40C31848 |
222 | #define CONFIG_SYS_GPCR1_VAL 0x00000000 | |
223 | #define CONFIG_SYS_GPCR2_VAL 0x00020000 | |
4ec3a7f0 WD |
224 | |
225 | /* | |
226 | * GP00 == CPUWakeUpUSB is input | |
227 | * GP01 == GP reset is input | |
228 | * GP02 == LANInterrupt is input | |
229 | * GP03 == LANReset is output | |
230 | * GP04 == USBInterrupt is input | |
231 | * GP05 == nUSBReset is output | |
232 | * GP06 == USBWakeUp is output | |
233 | * GP07 == CFReady/nBusy is input | |
234 | * GP08 == nCFCardDetect1 is input | |
235 | * GP09 == nCFCardDetect2 is input | |
236 | * GP10 == nCFReset is output | |
237 | * GP11 == USBControl is output | |
238 | * GP12 == Buzzer is output | |
239 | * GP13 == CFDataEnable is output | |
240 | * GP14 == CFAddressEnable is output | |
241 | * GP15 == nCS1 is output | |
242 | * GP16 == PWM0 is output | |
243 | * GP17 == PWM1 is output | |
244 | * GP18 == RDY is input | |
245 | * GP19 == ReaderReady is input | |
246 | * GP20 == ReaderReset is input | |
247 | * GP21 == ComBrdReset is output | |
248 | * GP23 == SCLK is output | |
249 | * GP24 == SFRM is output | |
250 | * GP25 == TXD is output | |
251 | * GP26 == RXD is input | |
252 | * GP27 == EXTCLK is input | |
253 | * GP28 == BITCLK is output | |
254 | * GP29 == SDATA_IN0 is input | |
255 | * GP30 == SDATA_OUT is output | |
256 | * GP31 == SYNC is output | |
257 | * GP32 == SYSSCLK is output | |
258 | * GP33 == nCS5 is output | |
259 | * GP34 == FFRXD is input | |
260 | * GP35 == CTS is input | |
261 | * GP36 == DCD is input | |
262 | * GP37 == DSR is input | |
263 | * GP38 == RI is input | |
264 | * GP39 == FFTXD is output | |
265 | * GP40 == DTR is output | |
266 | * GP41 == RTS is output | |
267 | * GP42 == BTRXD is input | |
268 | * GP43 == BTTXD is output | |
269 | * GP44 == BTCTS is input | |
270 | * GP45 == BTRTS is output | |
271 | * GP46 == RXD is input | |
272 | * GP47 == TXD is output | |
273 | * GP48 == nPOE is output | |
274 | * GP49 == nPWE is output | |
275 | * GP50 == nPIOR is output | |
276 | * GP51 == nPIOW is output | |
277 | * GP52 == nPCE[1] is output | |
278 | * GP53 == nPCE[2] is output | |
279 | * GP54 == nPSKTSEL is output | |
280 | * GP55 == nPREG is output | |
281 | * GP56 == nPWAIT is input | |
282 | * GP57 == nPIOS16 is input | |
283 | * GP58 == LDD[0] is output | |
284 | * GP59 == LDD[1] is output | |
285 | * GP60 == LDD[2] is output | |
286 | * GP61 == LDD[3] is output | |
287 | * GP62 == LDD[4] is output | |
288 | * GP63 == LDD[5] is output | |
289 | * GP64 == LDD[6] is output | |
290 | * GP65 == LDD[7] is output | |
291 | * GP66 == LDD[8] is output | |
292 | * GP67 == LDD[9] is output | |
293 | * GP68 == LDD[10] is output | |
294 | * GP69 == LDD[11] is output | |
295 | * GP70 == LDD[12] is output | |
296 | * GP71 == LDD[13] is output | |
297 | * GP72 == LDD[14] is output | |
298 | * GP73 == LDD[15] is output | |
299 | * GP74 == LCD_FCLK is output | |
300 | * GP75 == LCD_LCLK is output | |
301 | * GP76 == LCD_PCLK is output | |
302 | * GP77 == LCD_ACBIAS is output | |
303 | * GP78 == nCS2 is output | |
304 | * GP79 == nCS3 is output | |
305 | * GP80 == nCS4 is output | |
306 | * GP81 == NSSPCLK is output | |
307 | * GP82 == NSSPSFRM is output | |
308 | * GP83 == NSSPTXD is output | |
309 | * GP84 == NSSPRXD is input | |
310 | */ | |
6d0f6bcf JCPV |
311 | #define CONFIG_SYS_GPDR0_VAL 0xD3E3FC68 |
312 | #define CONFIG_SYS_GPDR1_VAL 0xFCFFAB83 | |
313 | #define CONFIG_SYS_GPDR2_VAL 0x000FFFFF | |
4ec3a7f0 WD |
314 | |
315 | /* | |
316 | * GP01 == GP reset is AF01 | |
317 | * GP15 == nCS1 is AF10 | |
318 | * GP16 == PWM0 is AF10 | |
319 | * GP17 == PWM1 is AF10 | |
320 | * GP18 == RDY is AF01 | |
321 | * GP23 == SCLK is AF10 | |
322 | * GP24 == SFRM is AF10 | |
323 | * GP25 == TXD is AF10 | |
324 | * GP26 == RXD is AF01 | |
325 | * GP27 == EXTCLK is AF01 | |
326 | * GP28 == BITCLK is AF01 | |
327 | * GP29 == SDATA_IN0 is AF10 | |
328 | * GP30 == SDATA_OUT is AF01 | |
329 | * GP31 == SYNC is AF01 | |
330 | * GP32 == SYSCLK is AF01 | |
331 | * GP33 == nCS5 is AF10 | |
332 | * GP34 == FFRXD is AF01 | |
333 | * GP35 == CTS is AF01 | |
334 | * GP36 == DCD is AF01 | |
335 | * GP37 == DSR is AF01 | |
336 | * GP38 == RI is AF01 | |
337 | * GP39 == FFTXD is AF10 | |
338 | * GP40 == DTR is AF10 | |
339 | * GP41 == RTS is AF10 | |
340 | * GP42 == BTRXD is AF01 | |
341 | * GP43 == BTTXD is AF10 | |
342 | * GP44 == BTCTS is AF01 | |
343 | * GP45 == BTRTS is AF10 | |
344 | * GP46 == RXD is AF10 | |
345 | * GP47 == TXD is AF01 | |
346 | * GP48 == nPOE is AF10 | |
347 | * GP49 == nPWE is AF10 | |
348 | * GP50 == nPIOR is AF10 | |
349 | * GP51 == nPIOW is AF10 | |
350 | * GP52 == nPCE[1] is AF10 | |
351 | * GP53 == nPCE[2] is AF10 | |
352 | * GP54 == nPSKTSEL is AF10 | |
353 | * GP55 == nPREG is AF10 | |
354 | * GP56 == nPWAIT is AF01 | |
355 | * GP57 == nPIOS16 is AF01 | |
356 | * GP58 == LDD[0] is AF10 | |
357 | * GP59 == LDD[1] is AF10 | |
358 | * GP60 == LDD[2] is AF10 | |
359 | * GP61 == LDD[3] is AF10 | |
360 | * GP62 == LDD[4] is AF10 | |
361 | * GP63 == LDD[5] is AF10 | |
362 | * GP64 == LDD[6] is AF10 | |
363 | * GP65 == LDD[7] is AF10 | |
364 | * GP66 == LDD[8] is AF10 | |
365 | * GP67 == LDD[9] is AF10 | |
366 | * GP68 == LDD[10] is AF10 | |
367 | * GP69 == LDD[11] is AF10 | |
368 | * GP70 == LDD[12] is AF10 | |
369 | * GP71 == LDD[13] is AF10 | |
370 | * GP72 == LDD[14] is AF10 | |
371 | * GP73 == LDD[15] is AF10 | |
372 | * GP74 == LCD_FCLK is AF10 | |
373 | * GP75 == LCD_LCLK is AF10 | |
374 | * GP76 == LCD_PCLK is AF10 | |
375 | * GP77 == LCD_ACBIAS is AF10 | |
376 | * GP78 == nCS2 is AF10 | |
377 | * GP79 == nCS3 is AF10 | |
378 | * GP80 == nCS4 is AF10 | |
379 | * GP81 == NSSPCLK is AF01 | |
380 | * GP82 == NSSPSFRM is AF01 | |
381 | * GP83 == NSSPTXD is AF01 | |
382 | * GP84 == NSSPRXD is AF10 | |
383 | */ | |
6d0f6bcf JCPV |
384 | #define CONFIG_SYS_GAFR0_L_VAL 0x80000004 |
385 | #define CONFIG_SYS_GAFR0_U_VAL 0x595A801A | |
386 | #define CONFIG_SYS_GAFR1_L_VAL 0x699A9559 | |
387 | #define CONFIG_SYS_GAFR1_U_VAL 0xAAA5AAAA | |
388 | #define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA | |
389 | #define CONFIG_SYS_GAFR2_U_VAL 0x00000256 | |
4ec3a7f0 WD |
390 | |
391 | /* | |
392 | * clock settings | |
393 | */ | |
394 | /* RDH = 1 | |
395 | * PH = 0 | |
396 | * VFS = 0 | |
397 | * BFS = 0 | |
398 | * SSS = 0 | |
399 | */ | |
6d0f6bcf | 400 | #define CONFIG_SYS_PSSR_VAL 0x00000030 |
4ec3a7f0 | 401 | |
1123d412 MV |
402 | #define CONFIG_SYS_CKEN 0x00000080 /* */ |
403 | #define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */ | |
404 | #define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 | |
4ec3a7f0 WD |
405 | |
406 | ||
407 | /* | |
408 | * Memory settings | |
409 | * | |
410 | * This is the configuration for nCS0/1 -> flash banks | |
411 | * configuration for nCS1 : | |
412 | * [31] 0 - | |
413 | * [30:28] 000 - | |
414 | * [27:24] 0000 - | |
415 | * [23:20] 0000 - | |
416 | * [19] 0 - | |
417 | * [18:16] 000 - | |
418 | * configuration for nCS0: | |
419 | * [15] 0 - Slower Device | |
420 | * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns | |
421 | * [11:08] 0011 - Address to data valid in bursts: (3+1)*MemClk = 40 ns | |
422 | * [07:04] 1111 - " for first access: (23+2)*MemClk = 250 ns (fixme 12+2?) | |
423 | * [03] 0 - 32 Bit bus width | |
424 | * [02:00] 010 - burst OF 4 ROM or FLASH | |
425 | */ | |
6d0f6bcf | 426 | #define CONFIG_SYS_MSC0_VAL 0x000023D2 |
4ec3a7f0 WD |
427 | |
428 | /* This is the configuration for nCS2/3 -> USB controller, LAN | |
429 | * configuration for nCS3: LAN | |
430 | * [31] 0 - Slower Device | |
431 | * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns | |
432 | * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns | |
433 | * [23:20] 0010 - RDF3: Address for first access: (2+1)*MemClk = 30 ns | |
434 | * [19] 0 - 32 Bit bus width | |
435 | * [18:16] 100 - variable latency I/O | |
436 | * configuration for nCS2: USB | |
437 | * [15] 1 - Faster Device | |
438 | * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns | |
439 | * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns | |
440 | * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns | |
452f6740 | 441 | * [03] 1 - 16 Bit bus width |
4ec3a7f0 WD |
442 | * [02:00] 100 - variable latency I/O |
443 | */ | |
6d0f6bcf | 444 | #define CONFIG_SYS_MSC1_VAL 0x1224A26C |
4ec3a7f0 WD |
445 | |
446 | /* This is the configuration for nCS4/5 -> LAN | |
447 | * configuration for nCS5: | |
448 | * [31] 0 - | |
449 | * [30:28] 000 - | |
450 | * [27:24] 0000 - | |
451 | * [23:20] 0000 - | |
452 | * [19] 0 - | |
453 | * [18:16] 000 - | |
454 | * configuration for nCS4: LAN | |
455 | * [15] 1 - Faster Device | |
456 | * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns | |
457 | * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns | |
458 | * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns | |
459 | * [03] 0 - 32 Bit bus width | |
460 | * [02:00] 100 - variable latency I/O | |
461 | */ | |
6d0f6bcf | 462 | #define CONFIG_SYS_MSC2_VAL 0x00001224 |
4ec3a7f0 WD |
463 | |
464 | /* MDCNFG: SDRAM Configuration Register | |
465 | * | |
466 | * [31:29] 000 - reserved | |
467 | * [28] 0 - no SA1111 compatiblity mode | |
468 | * [27] 0 - latch return data with return clock | |
469 | * [26] 0 - alternate addressing for pair 2/3 | |
470 | * [25:24] 00 - timings | |
471 | * [23] 0 - internal banks in lower partition 2/3 (not used) | |
472 | * [22:21] 00 - row address bits for partition 2/3 (not used) | |
473 | * [20:19] 00 - column address bits for partition 2/3 (not used) | |
474 | * [18] 0 - SDRAM partition 2/3 width is 32 bit | |
475 | * [17] 0 - SDRAM partition 3 disabled | |
476 | * [16] 0 - SDRAM partition 2 disabled | |
477 | * [15:13] 000 - reserved | |
478 | * [12] 0 - no SA1111 compatiblity mode | |
479 | * [11] 1 - latch return data with return clock | |
480 | * [10] 0 - no alternate addressing for pair 0/1 | |
481 | * [09:08] 10 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk | |
482 | * [7] 1 - 4 internal banks in lower partition pair | |
483 | * [06:05] 10 - 13 row address bits for partition 0/1 | |
484 | * [04:03] 01 - 9 column address bits for partition 0/1 | |
485 | * [02] 0 - SDRAM partition 0/1 width is 32 bit | |
486 | * [01] 0 - disable SDRAM partition 1 | |
487 | * [00] 1 - enable SDRAM partition 0 | |
488 | */ | |
489 | /* use the configuration above but disable partition 0 */ | |
6d0f6bcf | 490 | #define CONFIG_SYS_MDCNFG_VAL 0x00000AC9 |
4ec3a7f0 WD |
491 | |
492 | /* MDREFR: SDRAM Refresh Control Register | |
493 | * | |
494 | * [32:26] 0 - reserved | |
495 | * [25] 0 - K2FREE: not free running | |
496 | * [24] 0 - K1FREE: not free running | |
497 | * [23] 0 - K0FREE: not free running | |
498 | * [22] 0 - SLFRSH: self refresh disabled | |
499 | * [21] 0 - reserved | |
500 | * [20] 1 - APD: auto power down | |
501 | * [19] 0 - K2DB2: SDCLK2 is MemClk | |
502 | * [18] 0 - K2RUN: disable SDCLK2 | |
503 | * [17] 0 - K1DB2: SDCLK1 is MemClk | |
504 | * [16] 1 - K1RUN: enable SDCLK1 | |
505 | * [15] 1 - E1PIN: SDRAM clock enable | |
506 | * [14] 0 - K0DB2: SDCLK0 is MemClk | |
507 | * [13] 0 - K0RUN: disable SDCLK0 | |
508 | * [12] 0 - E0PIN: disable SDCKE0 | |
509 | * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 | |
510 | */ | |
6d0f6bcf | 511 | #define CONFIG_SYS_MDREFR_VAL 0x00138018 /* mh: was 0x00118018 */ |
4ec3a7f0 WD |
512 | |
513 | /* MDMRS: Mode Register Set Configuration Register | |
514 | * | |
515 | * [31] 0 - reserved | |
516 | * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) | |
517 | * [22:20] 011 - MDCL2: SDRAM2/3 Cas Latency. (not used) | |
518 | * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) | |
519 | * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) | |
520 | * [15] 0 - reserved | |
521 | * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. | |
522 | * [06:04] 011 - MDCL0: SDRAM0/1 Cas Latency. | |
523 | * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. | |
524 | * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. | |
525 | */ | |
6d0f6bcf | 526 | #define CONFIG_SYS_MDMRS_VAL 0x00320032 |
4ec3a7f0 | 527 | |
1123d412 MV |
528 | #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 |
529 | #define CONFIG_SYS_SXCNFG_VAL 0x00000000 | |
530 | ||
4ec3a7f0 WD |
531 | /* |
532 | * PCMCIA and CF Interfaces | |
533 | */ | |
6d0f6bcf JCPV |
534 | #define CONFIG_SYS_MECR_VAL 0x00000000 |
535 | #define CONFIG_SYS_MCMEM0_VAL 0x00010504 | |
536 | #define CONFIG_SYS_MCMEM1_VAL 0x00010504 | |
537 | #define CONFIG_SYS_MCATT0_VAL 0x00010504 | |
538 | #define CONFIG_SYS_MCATT1_VAL 0x00010504 | |
539 | #define CONFIG_SYS_MCIO0_VAL 0x00004715 | |
540 | #define CONFIG_SYS_MCIO1_VAL 0x00004715 | |
4ec3a7f0 WD |
541 | |
542 | ||
543 | #endif /* __CONFIG_H */ |