]>
Commit | Line | Data |
---|---|---|
4ec3a7f0 | 1 | /* |
414eec35 WD |
2 | * (C) Copyright 2004-2005 |
3 | * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> | |
4 | * | |
4ec3a7f0 WD |
5 | * (C) Copyright 2004 |
6 | * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com | |
7 | * | |
8 | * (C) Copyright 2002 | |
9 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.ne | |
10 | * | |
11 | * (C) Copyright 2002 | |
12 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
13 | * Marius Groeger <mgroeger@sysgo.de> | |
14 | * | |
15 | * Configuation settings for the xaeniax board. | |
16 | * | |
17 | * See file CREDITS for list of people who contributed to this | |
18 | * project. | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or | |
21 | * modify it under the terms of the GNU General Public License as | |
22 | * published by the Free Software Foundation; either version 2 of | |
23 | * the License, or (at your option) any later version. | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | * | |
30 | * You should have received a copy of the GNU General Public License | |
31 | * along with this program; if not, write to the Free Software | |
32 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
33 | * MA 02111-1307 USA | |
34 | */ | |
35 | ||
36 | #ifndef __CONFIG_H | |
37 | #define __CONFIG_H | |
38 | ||
4ec3a7f0 WD |
39 | /* |
40 | * High Level Configuration Options | |
41 | * (easy to change) | |
42 | */ | |
43 | #define CONFIG_PXA250 1 /* This is an PXA255 CPU */ | |
44 | #define CONFIG_XAENIAX 1 /* on a xaeniax board */ | |
45 | ||
46 | ||
47 | #define BOARD_LATE_INIT 1 | |
48 | ||
49 | ||
50 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ | |
51 | ||
52 | /* | |
53 | * select serial console configuration | |
54 | */ | |
55 | #define CONFIG_BTUART 1 /* we use BTUART on XAENIAX */ | |
56 | ||
57 | ||
58 | /* allow to overwrite serial and ethaddr */ | |
59 | #define CONFIG_ENV_OVERWRITE | |
60 | ||
414eec35 WD |
61 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
62 | ||
4ec3a7f0 WD |
63 | #define CONFIG_BAUDRATE 115200 |
64 | ||
65 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */ | |
66 | ||
4ec3a7f0 | 67 | |
079a136c JL |
68 | /* |
69 | * BOOTP options | |
70 | */ | |
71 | #define CONFIG_BOOTP_BOOTFILESIZE | |
72 | #define CONFIG_BOOTP_BOOTPATH | |
73 | #define CONFIG_BOOTP_GATEWAY | |
74 | #define CONFIG_BOOTP_HOSTNAME | |
75 | ||
76 | ||
dca3b3d6 JL |
77 | /* |
78 | * Command line configuration. | |
79 | */ | |
80 | #include <config_cmd_default.h> | |
81 | ||
82 | #define CONFIG_CMD_DHCP | |
83 | #define CONFIG_CMD_DIAG | |
84 | #define CONFIG_CMD_NFS | |
85 | #define CONFIG_CMD_SDRAM | |
86 | #define CONFIG_CMD_SNTP | |
87 | ||
88 | #undef CONFIG_CMD_DTT | |
89 | ||
4ec3a7f0 WD |
90 | |
91 | #define CONFIG_ETHADDR 08:00:3e:26:0a:5b | |
92 | #define CONFIG_NETMASK 255.255.255.0 | |
93 | #define CONFIG_IPADDR 192.168.68.201 | |
94 | #define CONFIG_SERVERIP 192.168.68.62 | |
95 | ||
96 | #define CONFIG_BOOTDELAY 3 | |
97 | #define CONFIG_BOOTCOMMAND "bootm 0x00100000" | |
98 | #define CONFIG_BOOTARGS "console=ttyS1,115200" | |
14699a22 | 99 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
53677ef1 | 100 | #define CONFIG_SETUP_MEMORY_TAGS 1 |
14699a22 | 101 | #define CONFIG_INITRD_TAG 1 |
4ec3a7f0 | 102 | |
dca3b3d6 | 103 | #if defined(CONFIG_CMD_KGDB) |
4ec3a7f0 WD |
104 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
105 | #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ | |
106 | #endif | |
107 | ||
108 | /* | |
109 | * Size of malloc() pool; this lives below the uppermost 128 KiB which are | |
110 | * used for the RAM copy of the uboot code | |
111 | */ | |
112 | #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) | |
113 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
114 | ||
115 | /* | |
116 | * Miscellaneous configurable options | |
117 | */ | |
118 | #define CFG_LONGHELP /* undef to save memory */ | |
119 | #define CFG_HUSH_PARSER 1 | |
120 | ||
121 | #define CFG_PROMPT_HUSH_PS2 "> " | |
122 | ||
123 | #ifdef CFG_HUSH_PARSER | |
124 | #define CFG_PROMPT "u-boot$ " /* Monitor Command Prompt */ | |
125 | #else | |
126 | #define CFG_PROMPT "u-boot=> " /* Monitor Command Prompt */ | |
127 | #endif | |
128 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
129 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
130 | #define CFG_MAXARGS 16 /* max number of command args */ | |
131 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
132 | #define CFG_DEVICE_NULLDEV 1 | |
133 | ||
134 | #define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ | |
135 | #define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ | |
136 | ||
137 | #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ | |
138 | ||
139 | #define CFG_LOAD_ADDR 0xa1000000 /* default load address */ | |
140 | ||
141 | #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ | |
142 | #define CFG_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */ | |
143 | ||
144 | /* | |
145 | * Physical Memory Map | |
146 | */ | |
147 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks (partition) of DRAM */ | |
148 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ | |
149 | #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ | |
150 | #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ | |
151 | #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ | |
152 | #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ | |
153 | #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ | |
154 | #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ | |
155 | #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ | |
156 | ||
157 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
158 | #define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ | |
159 | #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ | |
160 | #define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ | |
161 | #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ | |
162 | ||
163 | #define CFG_DRAM_BASE 0xa0000000 | |
164 | #define CFG_DRAM_SIZE 0x04000000 | |
165 | ||
166 | #define CFG_FLASH_BASE PHYS_FLASH_1 | |
167 | ||
168 | /* | |
169 | * FLASH and environment organization | |
170 | */ | |
171 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
172 | #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ | |
173 | ||
174 | /* timeout values are in ticks */ | |
175 | #define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ | |
176 | #define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ | |
177 | ||
178 | /* FIXME */ | |
179 | #define CFG_ENV_IS_IN_FLASH 1 | |
180 | #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector */ | |
181 | #define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ | |
182 | ||
183 | /* | |
184 | * Stack sizes | |
185 | * | |
186 | * The stack sizes are set up in start.S using the settings below | |
187 | */ | |
188 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
189 | #ifdef CONFIG_USE_IRQ | |
190 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
191 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
192 | #endif | |
193 | ||
194 | /* | |
195 | * SMSC91C111 Network Card | |
196 | */ | |
197 | #define CONFIG_DRIVER_SMC91111 1 | |
1f6d4258 | 198 | #define CONFIG_SMC91111_BASE 0x10000300 /* chip select 3 */ |
4ec3a7f0 WD |
199 | #define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */ |
200 | #undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ | |
201 | #undef CONFIG_SHOW_ACTIVITY | |
202 | #define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ | |
203 | ||
204 | /* | |
205 | * GPIO settings | |
206 | */ | |
207 | ||
208 | /* | |
209 | * GP05 == nUSBReset is 1 | |
210 | * GP10 == CFReset is 1 | |
211 | * GP13 == nCFDataEnable is 1 | |
212 | * GP14 == nCFAddrEnable is 1 | |
213 | * GP15 == nCS1 is 1 | |
214 | * GP21 == ComBrdReset is 1 | |
215 | * GP24 == SFRM is 1 | |
216 | * GP25 == TXD is 1 | |
217 | * GP31 == SYNC is 1 | |
218 | * GP33 == nCS5 is 1 | |
219 | * GP39 == FFTXD is 1 | |
220 | * GP41 == RTS is 1 | |
221 | * GP43 == BTTXD is 1 | |
222 | * GP45 == BTRTS is 1 | |
223 | * GP47 == TXD is 1 | |
224 | * GP48 == nPOE is 1 | |
225 | * GP49 == nPWE is 1 | |
226 | * GP50 == nPIOR is 1 | |
227 | * GP51 == nPIOW is 1 | |
228 | * GP52 == nPCE[1] is 1 | |
229 | * GP53 == nPCE[2] is 1 | |
230 | * GP54 == nPSKTSEL is 1 | |
231 | * GP55 == nPREG is 1 | |
232 | * GP78 == nCS2 is 1 | |
233 | * GP79 == nCS3 is 1 | |
234 | * GP80 == nCS4 is 1 | |
235 | * GP82 == NSSPSFRM is 1 | |
236 | * GP83 == NSSPTXD is 1 | |
237 | */ | |
238 | #define CFG_GPSR0_VAL 0x8320E420 | |
239 | #define CFG_GPSR1_VAL 0x00FFAA82 | |
240 | #define CFG_GPSR2_VAL 0x000DC000 | |
241 | ||
242 | /* | |
243 | * GP03 == LANReset is 0 | |
244 | * GP06 == USBWakeUp is 0 | |
245 | * GP11 == USBControl is 0 | |
246 | * GP12 == Buzzer is 0 | |
247 | * GP16 == PWM0 is 0 | |
248 | * GP17 == PWM1 is 0 | |
249 | * GP23 == SCLK is 0 | |
250 | * GP30 == SDATA_OUT is 0 | |
251 | * GP81 == NSSPCLK is 0 | |
252 | */ | |
452f6740 | 253 | #define CFG_GPCR0_VAL 0x40C31848 |
4ec3a7f0 WD |
254 | #define CFG_GPCR1_VAL 0x00000000 |
255 | #define CFG_GPCR2_VAL 0x00020000 | |
256 | ||
257 | /* | |
258 | * GP00 == CPUWakeUpUSB is input | |
259 | * GP01 == GP reset is input | |
260 | * GP02 == LANInterrupt is input | |
261 | * GP03 == LANReset is output | |
262 | * GP04 == USBInterrupt is input | |
263 | * GP05 == nUSBReset is output | |
264 | * GP06 == USBWakeUp is output | |
265 | * GP07 == CFReady/nBusy is input | |
266 | * GP08 == nCFCardDetect1 is input | |
267 | * GP09 == nCFCardDetect2 is input | |
268 | * GP10 == nCFReset is output | |
269 | * GP11 == USBControl is output | |
270 | * GP12 == Buzzer is output | |
271 | * GP13 == CFDataEnable is output | |
272 | * GP14 == CFAddressEnable is output | |
273 | * GP15 == nCS1 is output | |
274 | * GP16 == PWM0 is output | |
275 | * GP17 == PWM1 is output | |
276 | * GP18 == RDY is input | |
277 | * GP19 == ReaderReady is input | |
278 | * GP20 == ReaderReset is input | |
279 | * GP21 == ComBrdReset is output | |
280 | * GP23 == SCLK is output | |
281 | * GP24 == SFRM is output | |
282 | * GP25 == TXD is output | |
283 | * GP26 == RXD is input | |
284 | * GP27 == EXTCLK is input | |
285 | * GP28 == BITCLK is output | |
286 | * GP29 == SDATA_IN0 is input | |
287 | * GP30 == SDATA_OUT is output | |
288 | * GP31 == SYNC is output | |
289 | * GP32 == SYSSCLK is output | |
290 | * GP33 == nCS5 is output | |
291 | * GP34 == FFRXD is input | |
292 | * GP35 == CTS is input | |
293 | * GP36 == DCD is input | |
294 | * GP37 == DSR is input | |
295 | * GP38 == RI is input | |
296 | * GP39 == FFTXD is output | |
297 | * GP40 == DTR is output | |
298 | * GP41 == RTS is output | |
299 | * GP42 == BTRXD is input | |
300 | * GP43 == BTTXD is output | |
301 | * GP44 == BTCTS is input | |
302 | * GP45 == BTRTS is output | |
303 | * GP46 == RXD is input | |
304 | * GP47 == TXD is output | |
305 | * GP48 == nPOE is output | |
306 | * GP49 == nPWE is output | |
307 | * GP50 == nPIOR is output | |
308 | * GP51 == nPIOW is output | |
309 | * GP52 == nPCE[1] is output | |
310 | * GP53 == nPCE[2] is output | |
311 | * GP54 == nPSKTSEL is output | |
312 | * GP55 == nPREG is output | |
313 | * GP56 == nPWAIT is input | |
314 | * GP57 == nPIOS16 is input | |
315 | * GP58 == LDD[0] is output | |
316 | * GP59 == LDD[1] is output | |
317 | * GP60 == LDD[2] is output | |
318 | * GP61 == LDD[3] is output | |
319 | * GP62 == LDD[4] is output | |
320 | * GP63 == LDD[5] is output | |
321 | * GP64 == LDD[6] is output | |
322 | * GP65 == LDD[7] is output | |
323 | * GP66 == LDD[8] is output | |
324 | * GP67 == LDD[9] is output | |
325 | * GP68 == LDD[10] is output | |
326 | * GP69 == LDD[11] is output | |
327 | * GP70 == LDD[12] is output | |
328 | * GP71 == LDD[13] is output | |
329 | * GP72 == LDD[14] is output | |
330 | * GP73 == LDD[15] is output | |
331 | * GP74 == LCD_FCLK is output | |
332 | * GP75 == LCD_LCLK is output | |
333 | * GP76 == LCD_PCLK is output | |
334 | * GP77 == LCD_ACBIAS is output | |
335 | * GP78 == nCS2 is output | |
336 | * GP79 == nCS3 is output | |
337 | * GP80 == nCS4 is output | |
338 | * GP81 == NSSPCLK is output | |
339 | * GP82 == NSSPSFRM is output | |
340 | * GP83 == NSSPTXD is output | |
341 | * GP84 == NSSPRXD is input | |
342 | */ | |
343 | #define CFG_GPDR0_VAL 0xD3E3FC68 | |
344 | #define CFG_GPDR1_VAL 0xFCFFAB83 | |
345 | #define CFG_GPDR2_VAL 0x000FFFFF | |
346 | ||
347 | /* | |
348 | * GP01 == GP reset is AF01 | |
349 | * GP15 == nCS1 is AF10 | |
350 | * GP16 == PWM0 is AF10 | |
351 | * GP17 == PWM1 is AF10 | |
352 | * GP18 == RDY is AF01 | |
353 | * GP23 == SCLK is AF10 | |
354 | * GP24 == SFRM is AF10 | |
355 | * GP25 == TXD is AF10 | |
356 | * GP26 == RXD is AF01 | |
357 | * GP27 == EXTCLK is AF01 | |
358 | * GP28 == BITCLK is AF01 | |
359 | * GP29 == SDATA_IN0 is AF10 | |
360 | * GP30 == SDATA_OUT is AF01 | |
361 | * GP31 == SYNC is AF01 | |
362 | * GP32 == SYSCLK is AF01 | |
363 | * GP33 == nCS5 is AF10 | |
364 | * GP34 == FFRXD is AF01 | |
365 | * GP35 == CTS is AF01 | |
366 | * GP36 == DCD is AF01 | |
367 | * GP37 == DSR is AF01 | |
368 | * GP38 == RI is AF01 | |
369 | * GP39 == FFTXD is AF10 | |
370 | * GP40 == DTR is AF10 | |
371 | * GP41 == RTS is AF10 | |
372 | * GP42 == BTRXD is AF01 | |
373 | * GP43 == BTTXD is AF10 | |
374 | * GP44 == BTCTS is AF01 | |
375 | * GP45 == BTRTS is AF10 | |
376 | * GP46 == RXD is AF10 | |
377 | * GP47 == TXD is AF01 | |
378 | * GP48 == nPOE is AF10 | |
379 | * GP49 == nPWE is AF10 | |
380 | * GP50 == nPIOR is AF10 | |
381 | * GP51 == nPIOW is AF10 | |
382 | * GP52 == nPCE[1] is AF10 | |
383 | * GP53 == nPCE[2] is AF10 | |
384 | * GP54 == nPSKTSEL is AF10 | |
385 | * GP55 == nPREG is AF10 | |
386 | * GP56 == nPWAIT is AF01 | |
387 | * GP57 == nPIOS16 is AF01 | |
388 | * GP58 == LDD[0] is AF10 | |
389 | * GP59 == LDD[1] is AF10 | |
390 | * GP60 == LDD[2] is AF10 | |
391 | * GP61 == LDD[3] is AF10 | |
392 | * GP62 == LDD[4] is AF10 | |
393 | * GP63 == LDD[5] is AF10 | |
394 | * GP64 == LDD[6] is AF10 | |
395 | * GP65 == LDD[7] is AF10 | |
396 | * GP66 == LDD[8] is AF10 | |
397 | * GP67 == LDD[9] is AF10 | |
398 | * GP68 == LDD[10] is AF10 | |
399 | * GP69 == LDD[11] is AF10 | |
400 | * GP70 == LDD[12] is AF10 | |
401 | * GP71 == LDD[13] is AF10 | |
402 | * GP72 == LDD[14] is AF10 | |
403 | * GP73 == LDD[15] is AF10 | |
404 | * GP74 == LCD_FCLK is AF10 | |
405 | * GP75 == LCD_LCLK is AF10 | |
406 | * GP76 == LCD_PCLK is AF10 | |
407 | * GP77 == LCD_ACBIAS is AF10 | |
408 | * GP78 == nCS2 is AF10 | |
409 | * GP79 == nCS3 is AF10 | |
410 | * GP80 == nCS4 is AF10 | |
411 | * GP81 == NSSPCLK is AF01 | |
412 | * GP82 == NSSPSFRM is AF01 | |
413 | * GP83 == NSSPTXD is AF01 | |
414 | * GP84 == NSSPRXD is AF10 | |
415 | */ | |
416 | #define CFG_GAFR0_L_VAL 0x80000004 | |
417 | #define CFG_GAFR0_U_VAL 0x595A801A | |
418 | #define CFG_GAFR1_L_VAL 0x699A9559 | |
419 | #define CFG_GAFR1_U_VAL 0xAAA5AAAA | |
420 | #define CFG_GAFR2_L_VAL 0xAAAAAAAA | |
421 | #define CFG_GAFR2_U_VAL 0x00000256 | |
422 | ||
423 | /* | |
424 | * clock settings | |
425 | */ | |
426 | /* RDH = 1 | |
427 | * PH = 0 | |
428 | * VFS = 0 | |
429 | * BFS = 0 | |
430 | * SSS = 0 | |
431 | */ | |
432 | #define CFG_PSSR_VAL 0x00000030 | |
433 | ||
434 | #define CFG_CKEN_VAL 0x00000080 /* */ | |
435 | #define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */ | |
436 | ||
437 | ||
438 | /* | |
439 | * Memory settings | |
440 | * | |
441 | * This is the configuration for nCS0/1 -> flash banks | |
442 | * configuration for nCS1 : | |
443 | * [31] 0 - | |
444 | * [30:28] 000 - | |
445 | * [27:24] 0000 - | |
446 | * [23:20] 0000 - | |
447 | * [19] 0 - | |
448 | * [18:16] 000 - | |
449 | * configuration for nCS0: | |
450 | * [15] 0 - Slower Device | |
451 | * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns | |
452 | * [11:08] 0011 - Address to data valid in bursts: (3+1)*MemClk = 40 ns | |
453 | * [07:04] 1111 - " for first access: (23+2)*MemClk = 250 ns (fixme 12+2?) | |
454 | * [03] 0 - 32 Bit bus width | |
455 | * [02:00] 010 - burst OF 4 ROM or FLASH | |
456 | */ | |
457 | #define CFG_MSC0_VAL 0x000023D2 | |
458 | ||
459 | /* This is the configuration for nCS2/3 -> USB controller, LAN | |
460 | * configuration for nCS3: LAN | |
461 | * [31] 0 - Slower Device | |
462 | * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns | |
463 | * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns | |
464 | * [23:20] 0010 - RDF3: Address for first access: (2+1)*MemClk = 30 ns | |
465 | * [19] 0 - 32 Bit bus width | |
466 | * [18:16] 100 - variable latency I/O | |
467 | * configuration for nCS2: USB | |
468 | * [15] 1 - Faster Device | |
469 | * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns | |
470 | * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns | |
471 | * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns | |
452f6740 | 472 | * [03] 1 - 16 Bit bus width |
4ec3a7f0 WD |
473 | * [02:00] 100 - variable latency I/O |
474 | */ | |
452f6740 | 475 | #define CFG_MSC1_VAL 0x1224A26C |
4ec3a7f0 WD |
476 | |
477 | /* This is the configuration for nCS4/5 -> LAN | |
478 | * configuration for nCS5: | |
479 | * [31] 0 - | |
480 | * [30:28] 000 - | |
481 | * [27:24] 0000 - | |
482 | * [23:20] 0000 - | |
483 | * [19] 0 - | |
484 | * [18:16] 000 - | |
485 | * configuration for nCS4: LAN | |
486 | * [15] 1 - Faster Device | |
487 | * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns | |
488 | * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns | |
489 | * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns | |
490 | * [03] 0 - 32 Bit bus width | |
491 | * [02:00] 100 - variable latency I/O | |
492 | */ | |
493 | #define CFG_MSC2_VAL 0x00001224 | |
494 | ||
495 | /* MDCNFG: SDRAM Configuration Register | |
496 | * | |
497 | * [31:29] 000 - reserved | |
498 | * [28] 0 - no SA1111 compatiblity mode | |
499 | * [27] 0 - latch return data with return clock | |
500 | * [26] 0 - alternate addressing for pair 2/3 | |
501 | * [25:24] 00 - timings | |
502 | * [23] 0 - internal banks in lower partition 2/3 (not used) | |
503 | * [22:21] 00 - row address bits for partition 2/3 (not used) | |
504 | * [20:19] 00 - column address bits for partition 2/3 (not used) | |
505 | * [18] 0 - SDRAM partition 2/3 width is 32 bit | |
506 | * [17] 0 - SDRAM partition 3 disabled | |
507 | * [16] 0 - SDRAM partition 2 disabled | |
508 | * [15:13] 000 - reserved | |
509 | * [12] 0 - no SA1111 compatiblity mode | |
510 | * [11] 1 - latch return data with return clock | |
511 | * [10] 0 - no alternate addressing for pair 0/1 | |
512 | * [09:08] 10 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk | |
513 | * [7] 1 - 4 internal banks in lower partition pair | |
514 | * [06:05] 10 - 13 row address bits for partition 0/1 | |
515 | * [04:03] 01 - 9 column address bits for partition 0/1 | |
516 | * [02] 0 - SDRAM partition 0/1 width is 32 bit | |
517 | * [01] 0 - disable SDRAM partition 1 | |
518 | * [00] 1 - enable SDRAM partition 0 | |
519 | */ | |
520 | /* use the configuration above but disable partition 0 */ | |
521 | #define CFG_MDCNFG_VAL 0x00000AC9 | |
522 | ||
523 | /* MDREFR: SDRAM Refresh Control Register | |
524 | * | |
525 | * [32:26] 0 - reserved | |
526 | * [25] 0 - K2FREE: not free running | |
527 | * [24] 0 - K1FREE: not free running | |
528 | * [23] 0 - K0FREE: not free running | |
529 | * [22] 0 - SLFRSH: self refresh disabled | |
530 | * [21] 0 - reserved | |
531 | * [20] 1 - APD: auto power down | |
532 | * [19] 0 - K2DB2: SDCLK2 is MemClk | |
533 | * [18] 0 - K2RUN: disable SDCLK2 | |
534 | * [17] 0 - K1DB2: SDCLK1 is MemClk | |
535 | * [16] 1 - K1RUN: enable SDCLK1 | |
536 | * [15] 1 - E1PIN: SDRAM clock enable | |
537 | * [14] 0 - K0DB2: SDCLK0 is MemClk | |
538 | * [13] 0 - K0RUN: disable SDCLK0 | |
539 | * [12] 0 - E0PIN: disable SDCKE0 | |
540 | * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 | |
541 | */ | |
542 | #define CFG_MDREFR_VAL 0x00138018 /* mh: was 0x00118018 */ | |
543 | ||
544 | /* MDMRS: Mode Register Set Configuration Register | |
545 | * | |
546 | * [31] 0 - reserved | |
547 | * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) | |
548 | * [22:20] 011 - MDCL2: SDRAM2/3 Cas Latency. (not used) | |
549 | * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) | |
550 | * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) | |
551 | * [15] 0 - reserved | |
552 | * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. | |
553 | * [06:04] 011 - MDCL0: SDRAM0/1 Cas Latency. | |
554 | * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. | |
555 | * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. | |
556 | */ | |
557 | #define CFG_MDMRS_VAL 0x00320032 | |
558 | ||
559 | /* | |
560 | * PCMCIA and CF Interfaces | |
561 | */ | |
562 | #define CFG_MECR_VAL 0x00000000 | |
563 | #define CFG_MCMEM0_VAL 0x00010504 | |
564 | #define CFG_MCMEM1_VAL 0x00010504 | |
565 | #define CFG_MCATT0_VAL 0x00010504 | |
566 | #define CFG_MCATT1_VAL 0x00010504 | |
567 | #define CFG_MCIO0_VAL 0x00004715 | |
568 | #define CFG_MCIO1_VAL 0x00004715 | |
569 | ||
570 | ||
571 | #endif /* __CONFIG_H */ |