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Commit | Line | Data |
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0b54a9dd | 1 | /* |
d041e3e1 | 2 | * Configuration for Xilinx ZynqMP emulation platforms |
0b54a9dd SDPP |
3 | * |
4 | * (C) Copyright 2014 - 2015 Xilinx, Inc. | |
5 | * Michal Simek <michal.simek@xilinx.com> | |
6 | * Siva Durga Prasad Paladugu <sivadur@xilinx.com> | |
7 | * | |
8 | * Based on Configuration for Versatile Express | |
9 | * | |
10 | * SPDX-License-Identifier: GPL-2.0+ | |
11 | */ | |
12 | ||
13 | #ifndef __CONFIG_ZYNQMP_EP_H | |
14 | #define __CONFIG_ZYNQMP_EP_H | |
15 | ||
f3bd7280 | 16 | #define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000 |
c061d5b3 | 17 | #define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ << 9) |
0b54a9dd SDPP |
18 | #define CONFIG_ZYNQ_I2C0 |
19 | #define CONFIG_SYS_I2C_ZYNQ | |
20 | #define CONFIG_ZYNQ_EEPROM | |
6fe6f135 | 21 | #define CONFIG_AHCI |
f4dd69ca SDPP |
22 | #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ |
23 | ZYNQMP_USB1_XHCI_BASEADDR} | |
0b54a9dd | 24 | |
99cb9ce0 MS |
25 | /* Physical Memory Map */ |
26 | #define CONFIG_NR_DRAM_BANKS 1 | |
27 | #define CONFIG_SYS_SDRAM_BASE 0 | |
28 | #define CONFIG_SYS_SDRAM_SIZE 0x40000000 | |
29 | ||
713b6164 MS |
30 | #define COUNTER_FREQUENCY 4000000 |
31 | ||
0b54a9dd SDPP |
32 | #include <configs/xilinx_zynqmp.h> |
33 | ||
34 | #endif /* __CONFIG_ZYNQMP_EP_H */ |