[people/ms/u-boot.git] / include / configs / xm250.h

/*
 * (C) Copyright 2002
 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_PXA250	       1	/* This is an PXA250 CPU	*/
#define CONFIG_XM250	       1	/* on a MicroSys XM250 Board	*/
#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/

/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE

/*
 * Size of malloc() pool; this lives below the uppermost 128 KiB which are
 * used for the RAM copy of the uboot code
 *
 */
#define CONFIG_SYS_MALLOC_LEN		(256*1024)
#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */

/*
 * Hardware drivers
 */
#define CONFIG_NET_MULTI
#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE		0x04000300
#undef	CONFIG_SMC91111_EXT_PHY
#define CONFIG_SMC_USE_32_BIT
#undef	CONFIG_SHOW_ACTIVITY
#define CONFIG_NET_RETRY_COUNT		10	   /* # of retries		*/

/*
 * I2C bus
 */
#define CONFIG_HARD_I2C			1
#define CONFIG_SYS_I2C_SPEED			50000
#define CONFIG_SYS_I2C_SLAVE			0xfe

#define CONFIG_RTC_PCF8563		1
#define CONFIG_SYS_I2C_RTC_ADDR		0x51

#define CONFIG_SYS_I2C_EEPROM_ADDR		0x58	/* A0 = 0 (hardwired)		*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4	/* 4 bits = 16 octets		*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* between stop and start	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1	/* length of address		*/
#define CONFIG_SYS_EEPROM_SIZE			2048	/* size in bytes		*/
#undef	CONFIG_SYS_I2C_INIT_BOARD			/* board has no own init	*/

/*
 * select serial console configuration
 */
#define CONFIG_PXA_SERIAL
#define CONFIG_FFUART	       1       /* we use FFUART */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_BAUDRATE		115200


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ELF
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_DATE
#define CONFIG_CMD_I2C


#define CONFIG_BOOTDELAY	3

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM		*/

#define CONFIG_SYS_LOAD_ADDR		0xa3000000	/* default load address */

#define CONFIG_SYS_HZ			1000
#define CONFIG_SYS_CPUSPEED		0x161		/* set core clock to 400/400/100 MHz */

						/* valid baudrates */

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Definitions related to passing arguments to kernel.
 */
#define CONFIG_CMDLINE_TAG	 1	 /* send commandline to Kernel		*/
#define CONFIG_SETUP_MEMORY_TAGS 1	 /* send memory definition to kernel	*/
#define	CONFIG_INITRD_TAG	 1	 /* do not send initrd params		*/
#undef	CONFIG_VFD			 /* do not send framebuffer setup	*/

/*
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
#endif

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	4
#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1	*/
#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB		*/
#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2	*/
#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB		*/
#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3	*/
#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB		*/
#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4	*/
#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB		*/

#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1	*/
#define PHYS_FLASH_2		0x04000000 /* Flash Bank #1	*/
#define PHYS_FLASH_SIZE		0x01000000 /* 16 MB		*/
#define PHYS_FLASH_BANK_SIZE	0x01000000 /* 16 MB Banks	*/
#define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */

#define CONFIG_SYS_DRAM_BASE		0xa0000000
#define CONFIG_SYS_DRAM_SIZE		0x04000000

#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1

/*
 * FLASH and environment organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1     /* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	128   /* max number of sectors on one chip	*/

/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Erase	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Write	*/
#define CONFIG_SYS_FLASH_LOCK_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Set Lock Bit */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Clear Lock Bits */
#define CONFIG_SYS_FLASH_PROTECTION			/* "Real" (hardware) sectors protection */

#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + 0x40000)	/* Addr of Environment Sector	*/
#define CONFIG_ENV_SIZE		0x4000
#define CONFIG_ENV_SECT_SIZE	0x40000				/* Size of the Environment Sector	*/
#define CONFIG_SYS_MONITOR_LEN		0x20000				/* 128 KiB */

/******************************************************************************
 *
 * CPU specific defines
 *
 ******************************************************************************/

/*
 * GPIO settings
 *
 * GPIO pin assignments
 * GPIO	    Name	Dir Out AF
 * 0	    NC
 * 1	    NC
 * 2	    SIRQ1	I
 * 3	    SIRQ2	I
 * 4	    SIRQ3	I
 * 5	    DMAACK1	O   0
 * 6	    DMAACK2	O   0
 * 7	    DMAACK3	O   0
 * 8	    TC1		O   0
 * 9	    TC2		O   0
 * 10	    TC3		O   0
 * 11	    nDMAEN	O   1
 * 12	    AENCTRL	O   0
 * 13	    PLDTC	O   0
 * 14	    ETHIRQ	I
 * 15	    NC
 * 16	    NC
 * 17	    NC
 * 18	    RDY		I
 * 19	    DMASIO	I
 * 20	    ETHIRQ	NC
 * 21	    NC
 * 22	    PGMEN	O   1	 FIXME for debug only enable flash
 * 23	    NC
 * 24	    NC
 * 25	    NC
 * 26	    NC
 * 27	    NC
 * 28	    NC
 * 29	    NC
 * 30	    NC
 * 31	    NC
 * 32	    NC
 * 33	    NC
 * 34	    FFRXD	I	01
 * 35	    FFCTS	I	01
 * 36	    FFDCD	I	01
 * 37	    FFDSR	I	01
 * 38	    FFRI	I	01
 * 39	    FFTXD	O   1	10
 * 40	    FFDTR	O   0	10
 * 41	    FFRTS	O   0	10
 * 42	    RS232FOFF	O   0	00
 * 43	    NC
 * 44	    NC
 * 45	    IRSL0	O   0
 * 46	    IRRX0	I	01
 * 47	    IRTX0	O   0	10
 * 48	    NC
 * 49	    nIOWE	O   0
 * 50	    NC
 * 51	    NC
 * 52	    NC
 * 53	    NC
 * 54	    NC
 * 55	    NC
 * 56	    NC
 * 57	    NC
 * 58	    DKDIRQ	I
 * 59	    NC
 * 60	    NC
 * 61	    NC
 * 62	    NC
 * 63	    NC
 * 64	    COMLED	O   0
 * 65	    COMLED	O   0
 * 66	    COMLED	O   0
 * 67	    COMLED	O   0
 * 68	    COMLED	O   0
 * 69	    COMLED	O   0
 * 70	    COMLED	O   0
 * 71	    COMLED	O   0
 * 72	    NC
 * 73	    NC
 * 74	    NC
 * 75	    NC
 * 76	    NC
 * 77	    NC
 * 78	    CSIO	O   1
 * 79	    NC
 * 80	    CSETH	O   1
 *
 * NOTE: All NC's are defined to be outputs
 *
 */
/* Pin direction control */
#define CONFIG_SYS_GPDR0_VAL	    0xd3808000
#define CONFIG_SYS_GPDR1_VAL	    0xfcffab83
#define CONFIG_SYS_GPDR2_VAL	    0x0001ffff
/* Set and Clear registers */
#define CONFIG_SYS_GPSR0_VAL	    0x00008000
#define CONFIG_SYS_GPSR1_VAL	    0x00ff0002
#define CONFIG_SYS_GPSR2_VAL	    0x0001c000
#define CONFIG_SYS_GPCR0_VAL	    0x00000000
#define CONFIG_SYS_GPCR1_VAL	    0x00000000
#define CONFIG_SYS_GPCR2_VAL	    0x00000000
/* Edge detect registers (these are set by the kernel) */
#define CONFIG_SYS_GRER0_VAL	    0x00002180
#define CONFIG_SYS_GRER1_VAL	    0x00000000
#define CONFIG_SYS_GRER2_VAL	    0x00000000
#define CONFIG_SYS_GFER0_VAL	    0x000043e0
#define CONFIG_SYS_GFER1_VAL	    0x00000000
#define CONFIG_SYS_GFER2_VAL	    0x00000000
/* Alternate function registers */
#define CONFIG_SYS_GAFR0_L_VAL	    0x80000004
#define CONFIG_SYS_GAFR0_U_VAL	    0x595a8010
#define CONFIG_SYS_GAFR1_L_VAL	    0x699a9559
#define CONFIG_SYS_GAFR1_U_VAL	    0xaaa5aaaa
#define CONFIG_SYS_GAFR2_L_VAL	    0xaaaaaaaa
#define CONFIG_SYS_GAFR2_U_VAL	    0x00000002

/*
 * Clocks, power control and interrupts
 */
#define CONFIG_SYS_PSSR_VAL	    0x00000030
#define CONFIG_SYS_CCCR_VAL	    0x00000161	/* 100 MHz memory, 400 MHz CPU, 400 Turbo  */
#define CONFIG_SYS_CKEN_VAL	    0x000141ec	/* FFUART and STUART enabled	*/
#define CONFIG_SYS_ICMR_VAL	    0x00000000	/* No interrupts enabled	*/

/* FIXME
 *
 * RTC settings
 * Watchdog
 *
 */

/*
 * Memory settings
 *
 */
#define CONFIG_SYS_MSC0_VAL	    0x122423f0	/* FLASH   / LAN	    (cs0)/(cS1)	  */
#define CONFIG_SYS_MSC1_VAL	    0x35f4aa4c	/* USB	   / ST3+ST5	    (cs2)/(cS3)	  */
#define CONFIG_SYS_MSC2_VAL	    0x35f435fc	/* IDE	   / BCR + WatchDog (cs4)/(cS5)	  */
#define CONFIG_SYS_MDCNFG_VAL	    0x000009c9
#define CONFIG_SYS_MDMRS_VAL	    0x00220022
#define CONFIG_SYS_MDREFR_VAL	    0x000da018	/* Initial setting, individual bits set in lowlevel_init.S */

/*
 * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
 */
#define CONFIG_SYS_MECR_VAL	      0x00000000
#define CONFIG_SYS_MCMEM0_VAL	      0x00010504
#define CONFIG_SYS_MCMEM1_VAL	      0x00010504
#define CONFIG_SYS_MCATT0_VAL	      0x00010504
#define CONFIG_SYS_MCATT1_VAL	      0x00010504
#define CONFIG_SYS_MCIO0_VAL	      0x00004715
#define CONFIG_SYS_MCIO1_VAL	      0x00004715

/* Board specific defines */

#ifndef __ASSEMBLY__

/* global prototypes */
void led_code(int code, int color);

#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
efa329cb WD	1	/*
	2	* (C) Copyright 2002
	3	* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
	4	*
	5	* (C) Copyright 2002
	6	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	7	* Marius Groeger <mgroeger@sysgo.de>
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
efa329cb WD	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35	#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
	36	#define CONFIG_XM250 1 /* on a MicroSys XM250 Board */
	37	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	38
b3acb6cd JCPV	39	/* we will never enable dcache, because we have to setup MMU first */
	40	#define CONFIG_SYS_NO_DCACHE
	41
efa329cb WD	42	/*
	43	* Size of malloc() pool; this lives below the uppermost 128 KiB which are
	44	* used for the RAM copy of the uboot code
	45	*
	46	*/
6d0f6bcf JCPV	47	#define CONFIG_SYS_MALLOC_LEN (256*1024)
6d0f6bcf JCPV	48	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
efa329cb WD	49
	50	/*
	51	* Hardware drivers
	52	*/
7194ab80 BW	53	#define CONFIG_NET_MULTI
7194ab80 BW	54	#define CONFIG_SMC91111
efa329cb WD	55	#define CONFIG_SMC91111_BASE 0x04000300
	56	#undef CONFIG_SMC91111_EXT_PHY
	57	#define CONFIG_SMC_USE_32_BIT
	58	#undef CONFIG_SHOW_ACTIVITY
	59	#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
	60
	61	/*
	62	* I2C bus
	63	*/
	64	#define CONFIG_HARD_I2C 1
6d0f6bcf JCPV	65	#define CONFIG_SYS_I2C_SPEED 50000
6d0f6bcf JCPV	66	#define CONFIG_SYS_I2C_SLAVE 0xfe
efa329cb WD	67
efa329cb WD	68	#define CONFIG_RTC_PCF8563 1
6d0f6bcf	69	#define CONFIG_SYS_I2C_RTC_ADDR 0x51
efa329cb	70
6d0f6bcf JCPV	71	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* A0 = 0 (hardwired) */
	72	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 4 bits = 16 octets */
	73	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */
	74	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* length of address */
	75	#define CONFIG_SYS_EEPROM_SIZE 2048 /* size in bytes */
	76	#undef CONFIG_SYS_I2C_INIT_BOARD /* board has no own init */
efa329cb WD	77
	78	/*
	79	* select serial console configuration
	80	*/
379be585	81	#define CONFIG_PXA_SERIAL
efa329cb WD	82	#define CONFIG_FFUART 1 /* we use FFUART */
	83
	84	/* allow to overwrite serial and ethaddr */
	85	#define CONFIG_ENV_OVERWRITE
	86
	87	#define CONFIG_BAUDRATE 115200
	88
dca3b3d6	89
079a136c JL	90	/*
	91	* BOOTP options
	92	*/
	93	#define CONFIG_BOOTP_BOOTFILESIZE
	94	#define CONFIG_BOOTP_BOOTPATH
	95	#define CONFIG_BOOTP_GATEWAY
	96	#define CONFIG_BOOTP_HOSTNAME
	97
	98
dca3b3d6 JL	99	/*
	100	* Command line configuration.
	101	*/
	102	#include <config_cmd_default.h>
	103
	104	#define CONFIG_CMD_ELF
	105	#define CONFIG_CMD_EEPROM
	106	#define CONFIG_CMD_DATE
	107	#define CONFIG_CMD_I2C
	108
efa329cb WD	109
	110	#define CONFIG_BOOTDELAY 3
	111
	112	/*
	113	* Miscellaneous configurable options
	114	*/
6d0f6bcf JCPV	115	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	116	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
	117	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	118	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	119	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	120	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
efa329cb	121
6d0f6bcf JCPV	122	#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
6d0f6bcf JCPV	123	#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
efa329cb	124
6d0f6bcf	125	#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */
efa329cb	126
94a33129	127	#define CONFIG_SYS_HZ 1000
6d0f6bcf	128	#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/400/100 MHz */
efa329cb WD	129
	130	/* valid baudrates */
	131
6d0f6bcf	132	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
efa329cb WD	133
	134	/*
	135	* Definitions related to passing arguments to kernel.
	136	*/
2c33a38b WD	137	#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
	138	#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
	139	#define CONFIG_INITRD_TAG 1 /* do not send initrd params */
efa329cb WD	140	#undef CONFIG_VFD /* do not send framebuffer setup */
	141
	142	/*
	143	* Stack sizes
	144	*
	145	* The stack sizes are set up in start.S using the settings below
	146	*/
	147	#define CONFIG_STACKSIZE (1281024) / regular stack */
	148	#ifdef CONFIG_USE_IRQ
	149	#define CONFIG_STACKSIZE_IRQ (41024) / IRQ stack */
	150	#define CONFIG_STACKSIZE_FIQ (41024) / FIQ stack */
	151	#endif
	152
	153	/*
	154	* Physical Memory Map
	155	*/
	156	#define CONFIG_NR_DRAM_BANKS 4
	157	#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
	158	#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
	159	#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
	160	#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
	161	#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
	162	#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
	163	#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
	164	#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
	165
	166	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
	167	#define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */
	168	#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
	169	#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */
	170	#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
	171
6d0f6bcf JCPV	172	#define CONFIG_SYS_DRAM_BASE 0xa0000000
6d0f6bcf JCPV	173	#define CONFIG_SYS_DRAM_SIZE 0x04000000
efa329cb	174
6d0f6bcf	175	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
efa329cb WD	176
	177	/*
	178	* FLASH and environment organization
	179	*/
6d0f6bcf JCPV	180	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	181	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
efa329cb WD	182
efa329cb WD	183	/* timeout values are in ticks */
6d0f6bcf JCPV	184	#define CONFIG_SYS_FLASH_ERASE_TOUT (2CONFIG_SYS_HZ) / Timeout for Flash Erase */
	185	#define CONFIG_SYS_FLASH_WRITE_TOUT (2CONFIG_SYS_HZ) / Timeout for Flash Write */
	186	#define CONFIG_SYS_FLASH_LOCK_TOUT (2CONFIG_SYS_HZ) / Timeout for Flash Set Lock Bit */
	187	#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2CONFIG_SYS_HZ) / Timeout for Flash Clear Lock Bits */
	188	#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
efa329cb	189
5a1aceb0	190	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	191	#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector */
	192	#define CONFIG_ENV_SIZE 0x4000
	193	#define CONFIG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */
6d0f6bcf	194	#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */
efa329cb WD	195
	196	/******************************************************************************
	197	*
	198	* CPU specific defines
	199	*
	200	******************************************************************************/
	201
	202	/*
	203	* GPIO settings
	204	*
	205	* GPIO pin assignments
	206	* GPIO Name Dir Out AF
	207	* 0 NC
	208	* 1 NC
	209	* 2 SIRQ1 I
	210	* 3 SIRQ2 I
	211	* 4 SIRQ3 I
	212	* 5 DMAACK1 O 0
	213	* 6 DMAACK2 O 0
	214	* 7 DMAACK3 O 0
	215	* 8 TC1 O 0
	216	* 9 TC2 O 0
	217	* 10 TC3 O 0
	218	* 11 nDMAEN O 1
	219	* 12 AENCTRL O 0
	220	* 13 PLDTC O 0
	221	* 14 ETHIRQ I
	222	* 15 NC
	223	* 16 NC
	224	* 17 NC
	225	* 18 RDY I
	226	* 19 DMASIO I
	227	* 20 ETHIRQ NC
	228	* 21 NC
	229	* 22 PGMEN O 1 FIXME for debug only enable flash
	230	* 23 NC
	231	* 24 NC
	232	* 25 NC
	233	* 26 NC
	234	* 27 NC
	235	* 28 NC
	236	* 29 NC
	237	* 30 NC
	238	* 31 NC
	239	* 32 NC
	240	* 33 NC
	241	* 34 FFRXD I 01
	242	* 35 FFCTS I 01
	243	* 36 FFDCD I 01
	244	* 37 FFDSR I 01
	245	* 38 FFRI I 01
	246	* 39 FFTXD O 1 10
	247	* 40 FFDTR O 0 10
	248	* 41 FFRTS O 0 10
	249	* 42 RS232FOFF O 0 00
	250	* 43 NC
	251	* 44 NC
	252	* 45 IRSL0 O 0
	253	* 46 IRRX0 I 01
	254	* 47 IRTX0 O 0 10
	255	* 48 NC
	256	* 49 nIOWE O 0
	257	* 50 NC
	258	* 51 NC
259	* 52 NC
260	* 53 NC
261	* 54 NC
262	* 55 NC
263	* 56 NC
264	* 57 NC
265	* 58 DKDIRQ I
266	* 59 NC
267	* 60 NC
268	* 61 NC
269	* 62 NC
270	* 63 NC
271	* 64 COMLED O 0
272	* 65 COMLED O 0
273	* 66 COMLED O 0
274	* 67 COMLED O 0
275	* 68 COMLED O 0
276	* 69 COMLED O 0
277	* 70 COMLED O 0
278	* 71 COMLED O 0
279	* 72 NC
280	* 73 NC
281	* 74 NC
282	* 75 NC
283	* 76 NC
284	* 77 NC
285	* 78 CSIO O 1
286	* 79 NC
287	* 80 CSETH O 1
288	*
289	* NOTE: All NC's are defined to be outputs
290	*
291	*/
292	/* Pin direction control */
6d0f6bcf JCPV	293	#define CONFIG_SYS_GPDR0_VAL 0xd3808000
	294	#define CONFIG_SYS_GPDR1_VAL 0xfcffab83
	295	#define CONFIG_SYS_GPDR2_VAL 0x0001ffff
efa329cb	296	/* Set and Clear registers */
6d0f6bcf JCPV	297	#define CONFIG_SYS_GPSR0_VAL 0x00008000
	298	#define CONFIG_SYS_GPSR1_VAL 0x00ff0002
	299	#define CONFIG_SYS_GPSR2_VAL 0x0001c000
	300	#define CONFIG_SYS_GPCR0_VAL 0x00000000
	301	#define CONFIG_SYS_GPCR1_VAL 0x00000000
	302	#define CONFIG_SYS_GPCR2_VAL 0x00000000
efa329cb	303	/* Edge detect registers (these are set by the kernel) */
6d0f6bcf JCPV	304	#define CONFIG_SYS_GRER0_VAL 0x00002180
	305	#define CONFIG_SYS_GRER1_VAL 0x00000000
	306	#define CONFIG_SYS_GRER2_VAL 0x00000000
	307	#define CONFIG_SYS_GFER0_VAL 0x000043e0
	308	#define CONFIG_SYS_GFER1_VAL 0x00000000
	309	#define CONFIG_SYS_GFER2_VAL 0x00000000
efa329cb	310	/* Alternate function registers */
6d0f6bcf JCPV	311	#define CONFIG_SYS_GAFR0_L_VAL 0x80000004
	312	#define CONFIG_SYS_GAFR0_U_VAL 0x595a8010
	313	#define CONFIG_SYS_GAFR1_L_VAL 0x699a9559
	314	#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aaaa
	315	#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
	316	#define CONFIG_SYS_GAFR2_U_VAL 0x00000002
efa329cb WD	317
	318	/*
	319	* Clocks, power control and interrupts
	320	*/
6d0f6bcf JCPV	321	#define CONFIG_SYS_PSSR_VAL 0x00000030
	322	#define CONFIG_SYS_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU, 400 Turbo */
	323	#define CONFIG_SYS_CKEN_VAL 0x000141ec /* FFUART and STUART enabled */
	324	#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */
efa329cb WD	325
	326	/* FIXME
	327	*
	328	* RTC settings
	329	* Watchdog
	330	*
	331	*/
	332
	333	/*
	334	* Memory settings
	335	*
	336	*/
6d0f6bcf JCPV	337	#define CONFIG_SYS_MSC0_VAL 0x122423f0 /* FLASH / LAN (cs0)/(cS1) */
	338	#define CONFIG_SYS_MSC1_VAL 0x35f4aa4c /* USB / ST3+ST5 (cs2)/(cS3) */
	339	#define CONFIG_SYS_MSC2_VAL 0x35f435fc /* IDE / BCR + WatchDog (cs4)/(cS5) */
	340	#define CONFIG_SYS_MDCNFG_VAL 0x000009c9
	341	#define CONFIG_SYS_MDMRS_VAL 0x00220022
	342	#define CONFIG_SYS_MDREFR_VAL 0x000da018 /* Initial setting, individual bits set in lowlevel_init.S */
efa329cb WD	343
	344	/*
	345	* PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
	346	*/
6d0f6bcf JCPV	347	#define CONFIG_SYS_MECR_VAL 0x00000000
	348	#define CONFIG_SYS_MCMEM0_VAL 0x00010504
	349	#define CONFIG_SYS_MCMEM1_VAL 0x00010504
	350	#define CONFIG_SYS_MCATT0_VAL 0x00010504
	351	#define CONFIG_SYS_MCATT1_VAL 0x00010504
	352	#define CONFIG_SYS_MCIO0_VAL 0x00004715
	353	#define CONFIG_SYS_MCIO1_VAL 0x00004715
efa329cb WD	354
	355	/* Board specific defines */
	356
	357	#ifndef __ASSEMBLY__
	358
	359	/* global prototypes */
	360	void led_code(int code, int color);
	361
	362	#endif
	363
	364	#endif /* __CONFIG_H */