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1f03cbfa PT |
1 | /* |
2 | * Copyright 2008 Extreme Engineering Solutions, Inc. | |
3 | * Copyright 2004-2008 Freescale Semiconductor, Inc. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
1f03cbfa PT |
6 | */ |
7 | ||
8 | /* | |
c00ac259 | 9 | * xpedite520x board configuration file |
1f03cbfa PT |
10 | */ |
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | /* | |
15 | * High Level Configuration Options | |
16 | */ | |
1f03cbfa PT |
17 | #define CONFIG_XPEDITE5200 1 |
18 | #define CONFIG_SYS_BOARD_NAME "XPedite5200" | |
92af6549 | 19 | #define CONFIG_SYS_FORM_PMC_XMC 1 |
1f03cbfa | 20 | #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ |
1f03cbfa | 21 | |
2ae18241 WD |
22 | #ifndef CONFIG_SYS_TEXT_BASE |
23 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
24 | #endif | |
25 | ||
1f03cbfa PT |
26 | #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ |
27 | #define CONFIG_PCI1 1 /* PCI controller 1 */ | |
28 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
842033e6 | 29 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
1f03cbfa | 30 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
1f03cbfa PT |
31 | |
32 | /* | |
33 | * DDR config | |
34 | */ | |
1f03cbfa PT |
35 | #undef CONFIG_FSL_DDR_INTERACTIVE |
36 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
37 | #define CONFIG_DDR_SPD | |
38 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
39 | #define SPD_EEPROM_ADDRESS 0x54 | |
1f03cbfa PT |
40 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
41 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
42 | #define CONFIG_DDR_ECC | |
43 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
44 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
45 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
46 | #define CONFIG_VERY_BIG_RAM | |
47 | ||
48 | #define CONFIG_SYS_CLK_FREQ 66666666 | |
49 | ||
50 | /* | |
51 | * These can be toggled for performance analysis, otherwise use default. | |
52 | */ | |
53 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
54 | #define CONFIG_BTB /* toggle branch predition */ | |
55 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
56 | ||
e46fedfe TT |
57 | #define CONFIG_SYS_CCSRBAR 0xef000000 |
58 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
1f03cbfa PT |
59 | |
60 | /* | |
61 | * Diagnostics | |
62 | */ | |
63 | #define CONFIG_SYS_ALT_MEMTEST | |
64 | #define CONFIG_SYS_MEMTEST_START 0x10000000 | |
65 | #define CONFIG_SYS_MEMTEST_END 0x20000000 | |
66a8b440 PT |
66 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
67 | CONFIG_SYS_POST_I2C) | |
68 | #define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \ | |
69 | CONFIG_SYS_I2C_EEPROM_ADDR, \ | |
70 | CONFIG_SYS_I2C_PCA953X_ADDR0, \ | |
71 | CONFIG_SYS_I2C_PCA953X_ADDR1, \ | |
72 | CONFIG_SYS_I2C_RTC_ADDR} | |
1f03cbfa PT |
73 | |
74 | /* | |
75 | * Memory map | |
76 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
77 | * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable | |
78 | * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable | |
79 | * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable | |
80 | * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable | |
81 | * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable | |
82 | * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable | |
83 | * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable | |
84 | */ | |
85 | ||
202d9487 | 86 | #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) |
1f03cbfa PT |
87 | |
88 | /* | |
89 | * NAND flash configuration | |
90 | */ | |
91 | #define CONFIG_SYS_NAND_BASE 0xef800000 | |
92 | #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ | |
93 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
94 | #define CONFIG_NAND_ACTL | |
95 | #define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */ | |
96 | #define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */ | |
97 | #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */ | |
98 | #define CONFIG_SYS_NAND_ACTL_DELAY 25 | |
99 | ||
100 | /* | |
101 | * NOR flash configuration | |
102 | */ | |
103 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 | |
104 | #define CONFIG_SYS_FLASH_BASE2 0xf8000000 | |
105 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} | |
106 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
107 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
108 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
109 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
110 | #define CONFIG_FLASH_CFI_DRIVER | |
111 | #define CONFIG_SYS_FLASH_CFI | |
5ff82100 | 112 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
1f03cbfa PT |
113 | #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ |
114 | {0xfbf40000, 0xc0000} } | |
14d0a02a | 115 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
1f03cbfa PT |
116 | |
117 | /* | |
118 | * Chip select configuration | |
119 | */ | |
120 | /* NOR Flash 0 on CS0 */ | |
121 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ | |
122 | BR_PS_16 | \ | |
123 | BR_V) | |
124 | #define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \ | |
125 | OR_GPCM_ACS_DIV4 | \ | |
126 | OR_GPCM_SCY_8) | |
127 | ||
128 | /* NOR Flash 1 on CS1 */ | |
129 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ | |
130 | BR_PS_16 | \ | |
131 | BR_V) | |
132 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
133 | ||
134 | /* NAND flash on CS2 */ | |
135 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ | |
136 | BR_PS_8 | \ | |
137 | BR_V) | |
138 | ||
139 | /* NAND flash on CS2 */ | |
140 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ | |
141 | OR_GPCM_BCTLD | \ | |
142 | OR_GPCM_CSNT | \ | |
143 | OR_GPCM_ACS_DIV4 | \ | |
144 | OR_GPCM_SCY_4 | \ | |
145 | OR_GPCM_TRLX | \ | |
146 | OR_GPCM_EHTR) | |
147 | ||
148 | /* NAND flash on CS3 */ | |
149 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ | |
150 | BR_PS_8 | \ | |
151 | BR_V) | |
152 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM | |
153 | ||
154 | /* | |
155 | * Use L1 as initial stack | |
156 | */ | |
157 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
158 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 | |
553f0982 | 159 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 |
1f03cbfa | 160 | |
25ddd1fb | 161 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
1f03cbfa PT |
162 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
163 | ||
164 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ | |
165 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
166 | ||
167 | /* | |
168 | * Serial Port | |
169 | */ | |
170 | #define CONFIG_CONS_INDEX 1 | |
1f03cbfa PT |
171 | #define CONFIG_SYS_NS16550_SERIAL |
172 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
173 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
174 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
175 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
176 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
177 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} | |
1f03cbfa PT |
178 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
179 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
180 | ||
1f03cbfa PT |
181 | /* |
182 | * I2C | |
183 | */ | |
00f792e0 HS |
184 | #define CONFIG_SYS_I2C |
185 | #define CONFIG_SYS_I2C_FSL | |
186 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
187 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
188 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
189 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
190 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
191 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
1f03cbfa PT |
192 | |
193 | /* I2C EEPROM */ | |
194 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
195 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
196 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ | |
197 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ | |
198 | ||
199 | /* I2C RTC */ | |
200 | #define CONFIG_RTC_M41T11 1 | |
201 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
202 | #define CONFIG_SYS_M41T11_BASE_YEAR 2000 | |
203 | ||
204 | /* GPIO */ | |
205 | #define CONFIG_PCA953X | |
206 | #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 | |
207 | #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19 | |
208 | #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 | |
209 | ||
210 | /* PCA957 @ 0x18 */ | |
211 | #define CONFIG_SYS_PCA953X_BRD_CFG0 0x01 | |
212 | #define CONFIG_SYS_PCA953X_BRD_CFG1 0x02 | |
213 | #define CONFIG_SYS_PCA953X_BRD_CFG2 0x04 | |
214 | #define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08 | |
215 | #define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10 | |
72fb68d5 | 216 | #define CONFIG_SYS_PCA953X_NVM_WP 0x20 |
1f03cbfa PT |
217 | #define CONFIG_SYS_PCA953X_MONARCH 0x40 |
218 | #define CONFIG_SYS_PCA953X_EREADY 0x80 | |
219 | ||
220 | /* PCA957 @ 0x19 */ | |
221 | #define CONFIG_SYS_PCA953X_P14_IO0 0x01 | |
222 | #define CONFIG_SYS_PCA953X_P14_IO1 0x02 | |
223 | #define CONFIG_SYS_PCA953X_P14_IO2 0x04 | |
224 | #define CONFIG_SYS_PCA953X_P14_IO3 0x08 | |
225 | #define CONFIG_SYS_PCA953X_P14_IO4 0x10 | |
226 | #define CONFIG_SYS_PCA953X_P14_IO5 0x20 | |
227 | #define CONFIG_SYS_PCA953X_P14_IO6 0x40 | |
228 | #define CONFIG_SYS_PCA953X_P14_IO7 0x80 | |
229 | ||
66a8b440 PT |
230 | /* 12-bit ADC used to measure CPU diode */ |
231 | #define CONFIG_SYS_I2C_MAX1237_ADDR 0x34 | |
232 | ||
1f03cbfa PT |
233 | /* |
234 | * General PCI | |
235 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
236 | */ | |
9660c5de PT |
237 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
238 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS | |
1f03cbfa | 239 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */ |
9660c5de | 240 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
1f03cbfa PT |
241 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000 |
242 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */ | |
243 | ||
244 | /* | |
245 | * Networking options | |
246 | */ | |
247 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
1f03cbfa PT |
248 | #define CONFIG_MII 1 /* MII PHY management */ |
249 | #define CONFIG_ETHPRIME "eTSEC1" | |
250 | ||
251 | #define CONFIG_TSEC1 1 | |
252 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
253 | #define TSEC1_FLAGS TSEC_GIGABIT | |
254 | #define TSEC1_PHY_ADDR 1 | |
255 | #define TSEC1_PHYIDX 0 | |
256 | #define CONFIG_HAS_ETH0 | |
257 | ||
258 | #define CONFIG_TSEC2 1 | |
259 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
260 | #define TSEC2_FLAGS TSEC_GIGABIT | |
261 | #define TSEC2_PHY_ADDR 2 | |
262 | #define TSEC2_PHYIDX 0 | |
263 | #define CONFIG_HAS_ETH1 | |
264 | ||
265 | #define CONFIG_TSEC3 1 | |
266 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
267 | #define TSEC3_FLAGS TSEC_GIGABIT | |
268 | #define TSEC3_PHY_ADDR 3 | |
269 | #define TSEC3_PHYIDX 0 | |
270 | #define CONFIG_HAS_ETH2 | |
271 | ||
272 | #define CONFIG_TSEC4 1 | |
273 | #define CONFIG_TSEC4_NAME "eTSEC4" | |
274 | #define TSEC4_FLAGS TSEC_GIGABIT | |
275 | #define TSEC4_PHY_ADDR 4 | |
276 | #define TSEC4_PHYIDX 0 | |
277 | #define CONFIG_HAS_ETH3 | |
278 | ||
279 | /* | |
280 | * BOOTP options | |
281 | */ | |
282 | #define CONFIG_BOOTP_BOOTFILESIZE | |
283 | #define CONFIG_BOOTP_BOOTPATH | |
284 | #define CONFIG_BOOTP_GATEWAY | |
285 | ||
1f03cbfa PT |
286 | /* |
287 | * Miscellaneous configurable options | |
288 | */ | |
289 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
290 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
1f03cbfa | 291 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
5be58f5f | 292 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
1f03cbfa | 293 | #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ |
1f03cbfa PT |
294 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
295 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
1f03cbfa PT |
296 | #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ |
297 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ | |
298 | ||
299 | /* | |
300 | * For booting Linux, the board info and command line data | |
301 | * have to be in the first 16 MB of memory, since this is | |
302 | * the maximum mapped by the Linux kernel during initialization. | |
303 | */ | |
304 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ | |
39121c08 | 305 | #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ |
1f03cbfa | 306 | |
1f03cbfa PT |
307 | /* |
308 | * Environment Configuration | |
309 | */ | |
1f03cbfa PT |
310 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ |
311 | #define CONFIG_ENV_SIZE 0x8000 | |
312 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) | |
313 | ||
314 | /* | |
315 | * Flash memory map: | |
316 | * fff80000 - ffffffff Pri U-Boot (512 KB) | |
317 | * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) | |
318 | * fff00000 - fff3ffff Pri FDT (256KB) | |
319 | * fef00000 - ffefffff Pri OS image (16MB) | |
320 | * fc000000 - feefffff Pri OS Use/Filesystem (47MB) | |
321 | * | |
322 | * fbf80000 - fbffffff Sec U-Boot (512 KB) | |
323 | * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB) | |
324 | * fbf00000 - fbf3ffff Sec FDT (256KB) | |
325 | * faf00000 - fbefffff Sec OS image (16MB) | |
326 | * f8000000 - faefffff Sec OS Use/Filesystem (47MB) | |
327 | */ | |
5368c55d MV |
328 | #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) |
329 | #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000) | |
330 | #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) | |
331 | #define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000) | |
332 | #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) | |
333 | #define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000) | |
1f03cbfa PT |
334 | |
335 | #define CONFIG_PROG_UBOOT1 \ | |
336 | "$download_cmd $loadaddr $ubootfile; " \ | |
337 | "if test $? -eq 0; then " \ | |
338 | "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
339 | "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
340 | "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ | |
341 | "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
342 | "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ | |
343 | "if test $? -ne 0; then " \ | |
344 | "echo PROGRAM FAILED; " \ | |
345 | "else; " \ | |
346 | "echo PROGRAM SUCCEEDED; " \ | |
347 | "fi; " \ | |
348 | "else; " \ | |
349 | "echo DOWNLOAD FAILED; " \ | |
350 | "fi;" | |
351 | ||
352 | #define CONFIG_PROG_UBOOT2 \ | |
353 | "$download_cmd $loadaddr $ubootfile; " \ | |
354 | "if test $? -eq 0; then " \ | |
355 | "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
356 | "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
357 | "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ | |
358 | "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
359 | "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ | |
360 | "if test $? -ne 0; then " \ | |
361 | "echo PROGRAM FAILED; " \ | |
362 | "else; " \ | |
363 | "echo PROGRAM SUCCEEDED; " \ | |
364 | "fi; " \ | |
365 | "else; " \ | |
366 | "echo DOWNLOAD FAILED; " \ | |
367 | "fi;" | |
368 | ||
369 | #define CONFIG_BOOT_OS_NET \ | |
370 | "$download_cmd $osaddr $osfile; " \ | |
371 | "if test $? -eq 0; then " \ | |
372 | "if test -n $fdtaddr; then " \ | |
373 | "$download_cmd $fdtaddr $fdtfile; " \ | |
374 | "if test $? -eq 0; then " \ | |
375 | "bootm $osaddr - $fdtaddr; " \ | |
376 | "else; " \ | |
377 | "echo FDT DOWNLOAD FAILED; " \ | |
378 | "fi; " \ | |
379 | "else; " \ | |
380 | "bootm $osaddr; " \ | |
381 | "fi; " \ | |
382 | "else; " \ | |
383 | "echo OS DOWNLOAD FAILED; " \ | |
384 | "fi;" | |
385 | ||
386 | #define CONFIG_PROG_OS1 \ | |
387 | "$download_cmd $osaddr $osfile; " \ | |
388 | "if test $? -eq 0; then " \ | |
389 | "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ | |
390 | "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ | |
391 | "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ | |
392 | "if test $? -ne 0; then " \ | |
393 | "echo OS PROGRAM FAILED; " \ | |
394 | "else; " \ | |
395 | "echo OS PROGRAM SUCCEEDED; " \ | |
396 | "fi; " \ | |
397 | "else; " \ | |
398 | "echo OS DOWNLOAD FAILED; " \ | |
399 | "fi;" | |
400 | ||
401 | #define CONFIG_PROG_OS2 \ | |
402 | "$download_cmd $osaddr $osfile; " \ | |
403 | "if test $? -eq 0; then " \ | |
404 | "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ | |
405 | "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ | |
406 | "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ | |
407 | "if test $? -ne 0; then " \ | |
408 | "echo OS PROGRAM FAILED; " \ | |
409 | "else; " \ | |
410 | "echo OS PROGRAM SUCCEEDED; " \ | |
411 | "fi; " \ | |
412 | "else; " \ | |
413 | "echo OS DOWNLOAD FAILED; " \ | |
414 | "fi;" | |
415 | ||
416 | #define CONFIG_PROG_FDT1 \ | |
417 | "$download_cmd $fdtaddr $fdtfile; " \ | |
418 | "if test $? -eq 0; then " \ | |
419 | "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ | |
420 | "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ | |
421 | "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ | |
422 | "if test $? -ne 0; then " \ | |
423 | "echo FDT PROGRAM FAILED; " \ | |
424 | "else; " \ | |
425 | "echo FDT PROGRAM SUCCEEDED; " \ | |
426 | "fi; " \ | |
427 | "else; " \ | |
428 | "echo FDT DOWNLOAD FAILED; " \ | |
429 | "fi;" | |
430 | ||
431 | #define CONFIG_PROG_FDT2 \ | |
432 | "$download_cmd $fdtaddr $fdtfile; " \ | |
433 | "if test $? -eq 0; then " \ | |
434 | "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ | |
435 | "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ | |
436 | "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ | |
437 | "if test $? -ne 0; then " \ | |
438 | "echo FDT PROGRAM FAILED; " \ | |
439 | "else; " \ | |
440 | "echo FDT PROGRAM SUCCEEDED; " \ | |
441 | "fi; " \ | |
442 | "else; " \ | |
443 | "echo FDT DOWNLOAD FAILED; " \ | |
444 | "fi;" | |
445 | ||
446 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
447 | "autoload=yes\0" \ | |
448 | "download_cmd=tftp\0" \ | |
449 | "console_args=console=ttyS0,115200\0" \ | |
450 | "root_args=root=/dev/nfs rw\0" \ | |
451 | "misc_args=ip=on\0" \ | |
452 | "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ | |
453 | "bootfile=/home/user/file\0" \ | |
c00ac259 PT |
454 | "osfile=/home/user/board.uImage\0" \ |
455 | "fdtfile=/home/user/board.dtb\0" \ | |
1f03cbfa | 456 | "ubootfile=/home/user/u-boot.bin\0" \ |
b24a4f62 | 457 | "fdtaddr=0x1e00000\0" \ |
1f03cbfa PT |
458 | "osaddr=0x1000000\0" \ |
459 | "loadaddr=0x1000000\0" \ | |
460 | "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ | |
461 | "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ | |
462 | "prog_os1="CONFIG_PROG_OS1"\0" \ | |
463 | "prog_os2="CONFIG_PROG_OS2"\0" \ | |
464 | "prog_fdt1="CONFIG_PROG_FDT1"\0" \ | |
465 | "prog_fdt2="CONFIG_PROG_FDT2"\0" \ | |
466 | "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ | |
467 | "bootcmd_flash1=run set_bootargs; " \ | |
468 | "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ | |
469 | "bootcmd_flash2=run set_bootargs; " \ | |
470 | "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ | |
471 | "bootcmd=run bootcmd_flash1\0" | |
472 | #endif /* __CONFIG_H */ |