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ccf0fdd0 PT |
1 | /* |
2 | * Copyright 2008 Extreme Engineering Solutions, Inc. | |
3 | * Copyright 2007-2008 Freescale Semiconductor, Inc. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
ccf0fdd0 PT |
6 | */ |
7 | ||
8 | /* | |
c00ac259 | 9 | * xpedite537x board configuration file |
ccf0fdd0 PT |
10 | */ |
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | /* | |
15 | * High Level Configuration Options | |
16 | */ | |
17 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
18 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
ccf0fdd0 PT |
19 | #define CONFIG_MPC8572 1 |
20 | #define CONFIG_XPEDITE5370 1 | |
21 | #define CONFIG_SYS_BOARD_NAME "XPedite5370" | |
92af6549 | 22 | #define CONFIG_SYS_FORM_3U_VPX 1 |
ccf0fdd0 | 23 | #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ |
ccf0fdd0 | 24 | |
2ae18241 WD |
25 | #ifndef CONFIG_SYS_TEXT_BASE |
26 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
27 | #endif | |
28 | ||
ccf0fdd0 PT |
29 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
30 | #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ | |
31 | #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ | |
32 | #define CONFIG_PCIE1 1 /* PCIE controler 1 */ | |
33 | #define CONFIG_PCIE2 1 /* PCIE controler 2 */ | |
34 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
842033e6 | 35 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
ccf0fdd0 PT |
36 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
37 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ | |
38 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
0914f483 | 39 | #define CONFIG_FSL_ELBC 1 |
ccf0fdd0 | 40 | |
48618126 PT |
41 | /* |
42 | * Multicore config | |
43 | */ | |
44 | #define CONFIG_MP | |
45 | #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */ | |
46 | #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */ | |
47 | ||
ccf0fdd0 PT |
48 | /* |
49 | * DDR config | |
50 | */ | |
5614e71b | 51 | #define CONFIG_SYS_FSL_DDR2 |
ccf0fdd0 PT |
52 | #undef CONFIG_FSL_DDR_INTERACTIVE |
53 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
54 | #define CONFIG_DDR_SPD | |
55 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
56 | #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ | |
57 | #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ | |
58 | #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ | |
59 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
60 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
61 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
62 | #define CONFIG_DDR_ECC | |
63 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
64 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ | |
65 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
66 | #define CONFIG_VERY_BIG_RAM | |
67 | ||
68 | #ifndef __ASSEMBLY__ | |
69 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
70 | extern unsigned long get_board_ddr_clk(unsigned long dummy); | |
71 | #endif | |
72 | ||
73 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ | |
74 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ | |
75 | ||
76 | /* | |
77 | * These can be toggled for performance analysis, otherwise use default. | |
78 | */ | |
79 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
80 | #define CONFIG_BTB /* toggle branch predition */ | |
81 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
82 | ||
e46fedfe TT |
83 | #define CONFIG_SYS_CCSRBAR 0xef000000 |
84 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
ccf0fdd0 PT |
85 | |
86 | /* | |
87 | * Diagnostics | |
88 | */ | |
89 | #define CONFIG_SYS_ALT_MEMTEST | |
90 | #define CONFIG_SYS_MEMTEST_START 0x10000000 | |
91 | #define CONFIG_SYS_MEMTEST_END 0x20000000 | |
66a8b440 PT |
92 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
93 | CONFIG_SYS_POST_I2C) | |
94 | #define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \ | |
95 | CONFIG_SYS_I2C_DS4510_ADDR, \ | |
96 | CONFIG_SYS_I2C_EEPROM_ADDR, \ | |
97 | CONFIG_SYS_I2C_LM90_ADDR, \ | |
98 | CONFIG_SYS_I2C_PCA953X_ADDR0, \ | |
99 | CONFIG_SYS_I2C_PCA953X_ADDR1, \ | |
100 | CONFIG_SYS_I2C_PCA953X_ADDR2, \ | |
101 | CONFIG_SYS_I2C_PCA953X_ADDR3, \ | |
102 | CONFIG_SYS_I2C_PEX8518_ADDR, \ | |
103 | CONFIG_SYS_I2C_RTC_ADDR} | |
104 | /* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */ | |
105 | #define I2C_ADDR_IGNORE_LIST {0x50} | |
ccf0fdd0 PT |
106 | |
107 | /* | |
108 | * Memory map | |
109 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
110 | * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable | |
111 | * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable | |
112 | * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable | |
113 | * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable | |
114 | * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable | |
48618126 | 115 | * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable |
ccf0fdd0 PT |
116 | * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable |
117 | * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable | |
118 | * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable | |
119 | * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable | |
120 | */ | |
121 | ||
202d9487 | 122 | #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) |
ccf0fdd0 PT |
123 | |
124 | /* | |
125 | * NAND flash configuration | |
126 | */ | |
127 | #define CONFIG_SYS_NAND_BASE 0xef800000 | |
128 | #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ | |
0a6d0c63 PT |
129 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ |
130 | CONFIG_SYS_NAND_BASE2} | |
131 | #define CONFIG_SYS_MAX_NAND_DEVICE 2 | |
132 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
133 | #define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */ | |
134 | #define CONFIG_NAND_FSL_ELBC | |
ccf0fdd0 PT |
135 | |
136 | /* | |
137 | * NOR flash configuration | |
138 | */ | |
139 | #define CONFIG_SYS_FLASH_BASE 0xf8000000 | |
140 | #define CONFIG_SYS_FLASH_BASE2 0xf0000000 | |
141 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} | |
142 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
143 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
144 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
145 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
146 | #define CONFIG_FLASH_CFI_DRIVER | |
147 | #define CONFIG_SYS_FLASH_CFI | |
5ff82100 | 148 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
ccf0fdd0 PT |
149 | #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ |
150 | {0xf7f40000, 0xc0000} } | |
14d0a02a | 151 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
ccf0fdd0 PT |
152 | |
153 | /* | |
154 | * Chip select configuration | |
155 | */ | |
156 | /* NOR Flash 0 on CS0 */ | |
157 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ | |
158 | BR_PS_16 | \ | |
159 | BR_V) | |
160 | #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \ | |
161 | OR_GPCM_CSNT | \ | |
162 | OR_GPCM_XACS | \ | |
163 | OR_GPCM_ACS_DIV2 | \ | |
164 | OR_GPCM_SCY_8 | \ | |
165 | OR_GPCM_TRLX | \ | |
166 | OR_GPCM_EHTR | \ | |
167 | OR_GPCM_EAD) | |
168 | ||
169 | /* NOR Flash 1 on CS1 */ | |
170 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ | |
171 | BR_PS_16 | \ | |
172 | BR_V) | |
173 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
174 | ||
175 | /* NAND flash on CS2 */ | |
176 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ | |
177 | (2<<BR_DECC_SHIFT) | \ | |
178 | BR_PS_8 | \ | |
179 | BR_MS_FCM | \ | |
180 | BR_V) | |
181 | ||
182 | /* NAND flash on CS2 */ | |
183 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ | |
184 | OR_FCM_PGS | \ | |
185 | OR_FCM_CSCT | \ | |
186 | OR_FCM_CST | \ | |
187 | OR_FCM_CHT | \ | |
188 | OR_FCM_SCY_1 | \ | |
189 | OR_FCM_TRLX | \ | |
190 | OR_FCM_EHTR) | |
191 | ||
192 | /* NAND flash on CS3 */ | |
193 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ | |
194 | (2<<BR_DECC_SHIFT) | \ | |
195 | BR_PS_8 | \ | |
196 | BR_MS_FCM | \ | |
197 | BR_V) | |
198 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM | |
199 | ||
200 | /* | |
201 | * Use L1 as initial stack | |
202 | */ | |
203 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
204 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 | |
553f0982 | 205 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 |
ccf0fdd0 | 206 | |
25ddd1fb | 207 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
ccf0fdd0 PT |
208 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
209 | ||
210 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ | |
211 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
212 | ||
213 | /* | |
214 | * Serial Port | |
215 | */ | |
216 | #define CONFIG_CONS_INDEX 1 | |
217 | #define CONFIG_SYS_NS16550 | |
218 | #define CONFIG_SYS_NS16550_SERIAL | |
219 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
220 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
221 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
222 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
223 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
224 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} | |
225 | #define CONFIG_BAUDRATE 115200 | |
226 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
227 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
228 | ||
229 | /* | |
230 | * Use the HUSH parser | |
231 | */ | |
232 | #define CONFIG_SYS_HUSH_PARSER | |
ccf0fdd0 PT |
233 | |
234 | /* | |
235 | * Pass open firmware flat tree | |
236 | */ | |
237 | #define CONFIG_OF_LIBFDT 1 | |
238 | #define CONFIG_OF_BOARD_SETUP 1 | |
239 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
240 | ||
ccf0fdd0 PT |
241 | /* |
242 | * I2C | |
243 | */ | |
00f792e0 HS |
244 | #define CONFIG_SYS_I2C |
245 | #define CONFIG_SYS_I2C_FSL | |
246 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
247 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
248 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
249 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
250 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
251 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
252 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
ccf0fdd0 PT |
253 | |
254 | /* PEX8518 slave I2C interface */ | |
255 | #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 | |
256 | ||
257 | /* I2C DS1631 temperature sensor */ | |
258 | #define CONFIG_SYS_I2C_DS1621_ADDR 0x48 | |
259 | #define CONFIG_DTT_DS1621 | |
260 | #define CONFIG_DTT_SENSORS { 0 } | |
66a8b440 | 261 | #define CONFIG_SYS_I2C_LM90_ADDR 0x4c |
ccf0fdd0 PT |
262 | |
263 | /* I2C EEPROM - AT24C128B */ | |
264 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 | |
265 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
266 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ | |
267 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ | |
268 | ||
269 | /* I2C RTC */ | |
270 | #define CONFIG_RTC_M41T11 1 | |
271 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
272 | #define CONFIG_SYS_M41T11_BASE_YEAR 2000 | |
273 | ||
274 | /* GPIO/EEPROM/SRAM */ | |
275 | #define CONFIG_DS4510 | |
276 | #define CONFIG_SYS_I2C_DS4510_ADDR 0x51 | |
277 | ||
278 | /* GPIO */ | |
279 | #define CONFIG_PCA953X | |
280 | #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 | |
281 | #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c | |
282 | #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e | |
283 | #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f | |
284 | #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 | |
285 | ||
286 | /* | |
287 | * PU = pulled high, PD = pulled low | |
288 | * I = input, O = output, IO = input/output | |
289 | */ | |
290 | /* PCA9557 @ 0x18*/ | |
291 | #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ | |
292 | #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */ | |
293 | #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ | |
294 | #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */ | |
295 | #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ | |
296 | #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */ | |
297 | #define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */ | |
298 | #define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */ | |
299 | ||
300 | /* PCA9557 @ 0x1c*/ | |
301 | #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */ | |
302 | #define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */ | |
303 | #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */ | |
304 | #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */ | |
305 | #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */ | |
306 | #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */ | |
307 | #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */ | |
308 | #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */ | |
309 | ||
310 | /* PCA9557 @ 0x1e*/ | |
311 | #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */ | |
312 | #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */ | |
313 | #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */ | |
314 | #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */ | |
315 | #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */ | |
316 | #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */ | |
317 | #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */ | |
318 | ||
319 | /* PCA9557 @ 0x1f */ | |
320 | #define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */ | |
321 | #define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */ | |
322 | #define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */ | |
323 | #define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */ | |
324 | #define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */ | |
325 | ||
326 | /* | |
327 | * General PCI | |
328 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
329 | */ | |
330 | /* PCIE1 - VPX P1 */ | |
9660c5de PT |
331 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 |
332 | #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS | |
ccf0fdd0 | 333 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ |
9660c5de | 334 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
ccf0fdd0 PT |
335 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 |
336 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ | |
337 | ||
338 | /* PCIE2 - PEX8518 */ | |
9660c5de PT |
339 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 |
340 | #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS | |
ccf0fdd0 | 341 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ |
9660c5de | 342 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
ccf0fdd0 PT |
343 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 |
344 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ | |
345 | ||
346 | /* | |
347 | * Networking options | |
348 | */ | |
349 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
350 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
ccf0fdd0 PT |
351 | #define CONFIG_TSEC_TBI |
352 | #define CONFIG_MII 1 /* MII PHY management */ | |
353 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
354 | #define CONFIG_ETHPRIME "eTSEC2" | |
355 | ||
72c96a68 KG |
356 | /* |
357 | * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force | |
358 | * 1000mbps SGMII link | |
359 | */ | |
360 | #define CONFIG_TSEC_TBICR_SETTINGS ( \ | |
361 | TBICR_PHY_RESET \ | |
362 | | TBICR_FULL_DUPLEX \ | |
363 | | TBICR_SPEED1_SET \ | |
364 | ) | |
365 | ||
ccf0fdd0 PT |
366 | #define CONFIG_TSEC1 1 |
367 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
368 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
369 | #define TSEC1_PHY_ADDR 1 | |
370 | #define TSEC1_PHYIDX 0 | |
371 | #define CONFIG_HAS_ETH0 | |
372 | ||
373 | #define CONFIG_TSEC2 1 | |
374 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
375 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
376 | #define TSEC2_PHY_ADDR 2 | |
377 | #define TSEC2_PHYIDX 0 | |
378 | #define CONFIG_HAS_ETH1 | |
379 | ||
380 | /* | |
381 | * Command configuration. | |
382 | */ | |
383 | #include <config_cmd_default.h> | |
384 | ||
385 | #define CONFIG_CMD_ASKENV | |
386 | #define CONFIG_CMD_DATE | |
387 | #define CONFIG_CMD_DHCP | |
388 | #define CONFIG_CMD_DS4510 | |
389 | #define CONFIG_CMD_DS4510_INFO | |
390 | #define CONFIG_CMD_DTT | |
391 | #define CONFIG_CMD_EEPROM | |
392 | #define CONFIG_CMD_ELF | |
ccf0fdd0 PT |
393 | #define CONFIG_CMD_FLASH |
394 | #define CONFIG_CMD_I2C | |
395 | #define CONFIG_CMD_JFFS2 | |
396 | #define CONFIG_CMD_MII | |
0a6d0c63 | 397 | #define CONFIG_CMD_NAND |
ccf0fdd0 PT |
398 | #define CONFIG_CMD_NET |
399 | #define CONFIG_CMD_PCA953X | |
400 | #define CONFIG_CMD_PCA953X_INFO | |
401 | #define CONFIG_CMD_PCI | |
96d61603 | 402 | #define CONFIG_CMD_PCI_ENUM |
ccf0fdd0 | 403 | #define CONFIG_CMD_PING |
0a6d0c63 | 404 | #define CONFIG_CMD_SAVEENV |
ccf0fdd0 | 405 | #define CONFIG_CMD_SNTP |
199e262e | 406 | #define CONFIG_CMD_REGINFO |
ccf0fdd0 PT |
407 | |
408 | /* | |
409 | * Miscellaneous configurable options | |
410 | */ | |
411 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
412 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
ccf0fdd0 PT |
413 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
414 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
415 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
416 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
ccf0fdd0 | 417 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
5be58f5f | 418 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
ccf0fdd0 PT |
419 | #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ |
420 | #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ | |
421 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
422 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
423 | #define CONFIG_FIT 1 | |
424 | #define CONFIG_FIT_VERBOSE 1 | |
425 | #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ | |
426 | ||
427 | /* | |
428 | * For booting Linux, the board info and command line data | |
429 | * have to be in the first 16 MB of memory, since this is | |
430 | * the maximum mapped by the Linux kernel during initialization. | |
431 | */ | |
432 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ | |
39121c08 | 433 | #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ |
ccf0fdd0 | 434 | |
ccf0fdd0 PT |
435 | /* |
436 | * Environment Configuration | |
437 | */ | |
438 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
439 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ | |
440 | #define CONFIG_ENV_SIZE 0x8000 | |
441 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) | |
442 | ||
443 | /* | |
444 | * Flash memory map: | |
445 | * fff80000 - ffffffff Pri U-Boot (512 KB) | |
446 | * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) | |
447 | * fff00000 - fff3ffff Pri FDT (256KB) | |
448 | * fef00000 - ffefffff Pri OS image (16MB) | |
449 | * f8000000 - feefffff Pri OS Use/Filesystem (111MB) | |
450 | * | |
451 | * f7f80000 - f7ffffff Sec U-Boot (512 KB) | |
452 | * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB) | |
453 | * f7f00000 - f7f3ffff Sec FDT (256KB) | |
454 | * f6f00000 - f7efffff Sec OS image (16MB) | |
455 | * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) | |
456 | */ | |
5368c55d MV |
457 | #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) |
458 | #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000) | |
459 | #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) | |
460 | #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000) | |
461 | #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) | |
462 | #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000) | |
ccf0fdd0 PT |
463 | |
464 | #define CONFIG_PROG_UBOOT1 \ | |
465 | "$download_cmd $loadaddr $ubootfile; " \ | |
466 | "if test $? -eq 0; then " \ | |
467 | "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
468 | "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
469 | "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ | |
470 | "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
471 | "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ | |
472 | "if test $? -ne 0; then " \ | |
473 | "echo PROGRAM FAILED; " \ | |
474 | "else; " \ | |
475 | "echo PROGRAM SUCCEEDED; " \ | |
476 | "fi; " \ | |
477 | "else; " \ | |
478 | "echo DOWNLOAD FAILED; " \ | |
479 | "fi;" | |
480 | ||
481 | #define CONFIG_PROG_UBOOT2 \ | |
482 | "$download_cmd $loadaddr $ubootfile; " \ | |
483 | "if test $? -eq 0; then " \ | |
484 | "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
485 | "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
486 | "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ | |
487 | "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
488 | "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ | |
489 | "if test $? -ne 0; then " \ | |
490 | "echo PROGRAM FAILED; " \ | |
491 | "else; " \ | |
492 | "echo PROGRAM SUCCEEDED; " \ | |
493 | "fi; " \ | |
494 | "else; " \ | |
495 | "echo DOWNLOAD FAILED; " \ | |
496 | "fi;" | |
497 | ||
498 | #define CONFIG_BOOT_OS_NET \ | |
499 | "$download_cmd $osaddr $osfile; " \ | |
500 | "if test $? -eq 0; then " \ | |
501 | "if test -n $fdtaddr; then " \ | |
502 | "$download_cmd $fdtaddr $fdtfile; " \ | |
503 | "if test $? -eq 0; then " \ | |
504 | "bootm $osaddr - $fdtaddr; " \ | |
505 | "else; " \ | |
506 | "echo FDT DOWNLOAD FAILED; " \ | |
507 | "fi; " \ | |
508 | "else; " \ | |
509 | "bootm $osaddr; " \ | |
510 | "fi; " \ | |
511 | "else; " \ | |
512 | "echo OS DOWNLOAD FAILED; " \ | |
513 | "fi;" | |
514 | ||
515 | #define CONFIG_PROG_OS1 \ | |
516 | "$download_cmd $osaddr $osfile; " \ | |
517 | "if test $? -eq 0; then " \ | |
518 | "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ | |
519 | "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ | |
520 | "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ | |
521 | "if test $? -ne 0; then " \ | |
522 | "echo OS PROGRAM FAILED; " \ | |
523 | "else; " \ | |
524 | "echo OS PROGRAM SUCCEEDED; " \ | |
525 | "fi; " \ | |
526 | "else; " \ | |
527 | "echo OS DOWNLOAD FAILED; " \ | |
528 | "fi;" | |
529 | ||
530 | #define CONFIG_PROG_OS2 \ | |
531 | "$download_cmd $osaddr $osfile; " \ | |
532 | "if test $? -eq 0; then " \ | |
533 | "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ | |
534 | "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ | |
535 | "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ | |
536 | "if test $? -ne 0; then " \ | |
537 | "echo OS PROGRAM FAILED; " \ | |
538 | "else; " \ | |
539 | "echo OS PROGRAM SUCCEEDED; " \ | |
540 | "fi; " \ | |
541 | "else; " \ | |
542 | "echo OS DOWNLOAD FAILED; " \ | |
543 | "fi;" | |
544 | ||
545 | #define CONFIG_PROG_FDT1 \ | |
546 | "$download_cmd $fdtaddr $fdtfile; " \ | |
547 | "if test $? -eq 0; then " \ | |
548 | "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ | |
549 | "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ | |
550 | "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ | |
551 | "if test $? -ne 0; then " \ | |
552 | "echo FDT PROGRAM FAILED; " \ | |
553 | "else; " \ | |
554 | "echo FDT PROGRAM SUCCEEDED; " \ | |
555 | "fi; " \ | |
556 | "else; " \ | |
557 | "echo FDT DOWNLOAD FAILED; " \ | |
558 | "fi;" | |
559 | ||
560 | #define CONFIG_PROG_FDT2 \ | |
561 | "$download_cmd $fdtaddr $fdtfile; " \ | |
562 | "if test $? -eq 0; then " \ | |
563 | "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ | |
564 | "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ | |
565 | "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ | |
566 | "if test $? -ne 0; then " \ | |
567 | "echo FDT PROGRAM FAILED; " \ | |
568 | "else; " \ | |
569 | "echo FDT PROGRAM SUCCEEDED; " \ | |
570 | "fi; " \ | |
571 | "else; " \ | |
572 | "echo FDT DOWNLOAD FAILED; " \ | |
573 | "fi;" | |
574 | ||
575 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
576 | "autoload=yes\0" \ | |
577 | "download_cmd=tftp\0" \ | |
578 | "console_args=console=ttyS0,115200\0" \ | |
579 | "root_args=root=/dev/nfs rw\0" \ | |
580 | "misc_args=ip=on\0" \ | |
581 | "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ | |
582 | "bootfile=/home/user/file\0" \ | |
c00ac259 PT |
583 | "osfile=/home/user/board.uImage\0" \ |
584 | "fdtfile=/home/user/board.dtb\0" \ | |
ccf0fdd0 PT |
585 | "ubootfile=/home/user/u-boot.bin\0" \ |
586 | "fdtaddr=c00000\0" \ | |
587 | "osaddr=0x1000000\0" \ | |
588 | "loadaddr=0x1000000\0" \ | |
589 | "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ | |
590 | "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ | |
591 | "prog_os1="CONFIG_PROG_OS1"\0" \ | |
592 | "prog_os2="CONFIG_PROG_OS2"\0" \ | |
593 | "prog_fdt1="CONFIG_PROG_FDT1"\0" \ | |
594 | "prog_fdt2="CONFIG_PROG_FDT2"\0" \ | |
595 | "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ | |
596 | "bootcmd_flash1=run set_bootargs; " \ | |
597 | "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ | |
598 | "bootcmd_flash2=run set_bootargs; " \ | |
599 | "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ | |
600 | "bootcmd=run bootcmd_flash1\0" | |
601 | #endif /* __CONFIG_H */ |