[thirdparty/u-boot.git] / include / configs / xpedite537x.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2008 Extreme Engineering Solutions, Inc.
 * Copyright 2007-2008 Freescale Semiconductor, Inc.
 */

/*
 * xpedite537x board configuration file
 */
#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_SYS_BOARD_NAME	"XPedite5370"
#define CONFIG_SYS_FORM_3U_VPX	1

#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
#define CONFIG_PCIE1		1	/* PCIE controller 1 */
#define CONFIG_PCIE2		1	/* PCIE controller 2 */
#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */

/*
 * Multicore config
 */
#define CONFIG_BPTR_VIRT_ADDR	0xee000000	/* virt boot page address */
#define CONFIG_MPC8xxx_DISABLE_BPTR		/* Don't leave BPTR enabled */

/*
 * DDR config
 */
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
#define SPD_EEPROM_ADDRESS1		0x54	/* Both channels use the */
#define SPD_EEPROM_ADDRESS2		0x54	/* same SPD data         */
#define SPD_EEPROM_OFFSET		0x200	/* OFFSET of SPD in EEPROM */
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	1
#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM

#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(unsigned long dummy);
extern unsigned long get_board_ddr_clk(unsigned long dummy);
#endif

#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0) /* ddrclk for MPC85xx */

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */
#define CONFIG_ENABLE_36BIT_PHYS	1

#define CONFIG_SYS_CCSRBAR		0xef000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/*
 * Diagnostics
 */
#define CONFIG_POST			(CONFIG_SYS_POST_MEMORY | \
					 CONFIG_SYS_POST_I2C)
/* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
#define I2C_ADDR_IGNORE_LIST		{0x50}

/*
 * Memory map
 * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
 * 0x8000_0000	0xbfff_ffff	PCIe1 Mem		1G non-cacheable
 * 0xc000_0000	0xcfff_ffff	PCIe2 Mem		256M non-cacheable
 * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
 * 0xe800_0000	0xe87f_ffff	PCIe1 IO		8M non-cacheable
 * 0xe880_0000	0xe8ff_ffff	PCIe2 IO		8M non-cacheable
 * 0xee00_0000	0xee00_ffff	Boot page translation	4K non-cacheable
 * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
 * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
 * 0xf000_0000	0xf7ff_ffff	NOR Flash 2		128M non-cacheable
 * 0xf800_0000	0xffff_ffff	NOR Flash 1		128M non-cacheable
 */

#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_8 | LCRR_EADC_3)

/*
 * NAND flash configuration
 */
#define CONFIG_SYS_NAND_BASE		0xef800000
#define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
#define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE, \
					 CONFIG_SYS_NAND_BASE2}
#define CONFIG_SYS_MAX_NAND_DEVICE	2
#define CONFIG_NAND_FSL_ELBC

/*
 * NOR flash configuration
 */
#define CONFIG_SYS_FLASH_BASE		0xf8000000
#define CONFIG_SYS_FLASH_BASE2		0xf0000000
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
						  {0xf7f40000, 0xc0000} }
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

/*
 * Chip select configuration
 */
/* NOR Flash 0 on CS0 */
#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
				 BR_PS_16		| \
				 BR_V)
#define CONFIG_SYS_OR0_PRELIM	(OR_AM_128MB		| \
				 OR_GPCM_CSNT		| \
				 OR_GPCM_XACS		| \
				 OR_GPCM_ACS_DIV2	| \
				 OR_GPCM_SCY_8		| \
				 OR_GPCM_TRLX		| \
				 OR_GPCM_EHTR		| \
				 OR_GPCM_EAD)

/* NOR Flash 1 on CS1 */
#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
				 BR_PS_16		| \
				 BR_V)
#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM

/* NAND flash on CS2 */
#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
				 (2<<BR_DECC_SHIFT)	| \
				 BR_PS_8		| \
				 BR_MS_FCM		| \
				 BR_V)

/* NAND flash on CS2 */
#define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB	| \
				 OR_FCM_PGS	| \
				 OR_FCM_CSCT	| \
				 OR_FCM_CST	| \
				 OR_FCM_CHT	| \
				 OR_FCM_SCY_1	| \
				 OR_FCM_TRLX	| \
				 OR_FCM_EHTR)

/* NAND flash on CS3 */
#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
				 (2<<BR_DECC_SHIFT)	| \
				 BR_PS_8		| \
				 BR_MS_FCM		| \
				 BR_V)
#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM

/*
 * Use L1 as initial stack
 */
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */

/*
 * Serial Port
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }

/* PEX8518 slave I2C interface */
#define CONFIG_SYS_I2C_PEX8518_ADDR	0x70

/* I2C DS1631 temperature sensor */
#define CONFIG_SYS_I2C_LM90_ADDR	0x4c

/* I2C EEPROM - AT24C128B */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */

/* I2C RTC */
#define CONFIG_RTC_M41T11		1
#define CONFIG_SYS_I2C_RTC_ADDR		0x68
#define CONFIG_SYS_M41T11_BASE_YEAR	2000

/* GPIO */
#define CONFIG_PCA953X
#define CONFIG_SYS_I2C_PCA953X_ADDR0	0x18
#define CONFIG_SYS_I2C_PCA953X_ADDR1	0x1c
#define CONFIG_SYS_I2C_PCA953X_ADDR2	0x1e
#define CONFIG_SYS_I2C_PCA953X_ADDR3	0x1f
#define CONFIG_SYS_I2C_PCA953X_ADDR	CONFIG_SYS_I2C_PCA953X_ADDR0

/*
 * PU = pulled high, PD = pulled low
 * I = input, O = output, IO = input/output
 */
/* PCA9557 @ 0x18*/
#define CONFIG_SYS_PCA953X_C0_SER0_EN		0x01 /* PU; UART0 enable (1: enabled) */
#define CONFIG_SYS_PCA953X_C0_SER0_MODE		0x02 /* PU; UART0 serial mode select */
#define CONFIG_SYS_PCA953X_C0_SER1_EN		0x04 /* PU; UART1 enable (1: enabled) */
#define CONFIG_SYS_PCA953X_C0_SER1_MODE		0x08 /* PU; UART1 serial mode select */
#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS	0x10 /* PU; Boot flash CS select */
#define CONFIG_SYS_PCA953X_NVM_WP		0x20 /* PU; Set to 0 to enable NVM writing */
#define CONFIG_SYS_PCA953X_C0_VCORE_VID2	0x40 /* VID2 of ISL6262 */
#define CONFIG_SYS_PCA953X_C0_VCORE_VID3	0x80 /* VID3 of ISL6262 */

/* PCA9557 @ 0x1c*/
#define CONFIG_SYS_PCA953X_XMC0_ROOT0		0x01 /* PU; Low if XMC is RC */
#define CONFIG_SYS_PCA953X_XMC0_MVMR0		0x02 /* XMC EEPROM write protect */
#define CONFIG_SYS_PCA953X_XMC0_WAKE		0x04 /* PU; XMC wake */
#define CONFIG_SYS_PCA953X_XMC0_BIST		0x08 /* PU; XMC built in self test */
#define CONFIG_SYS_PCA953X_XMC_PRESENT		0x10 /* PU; Low if XMC module installed */
#define CONFIG_SYS_PCA953X_PMC_PRESENT		0x20 /* PU; Low if PMC module installed */
#define CONFIG_SYS_PCA953X_PMC0_MONARCH		0x40 /* PMC monarch mode enable */
#define CONFIG_SYS_PCA953X_PMC0_EREADY		0x80 /* PU; PMC PCI eready */

/* PCA9557 @ 0x1e*/
#define CONFIG_SYS_PCA953X_P0_GA0		0x01 /* PU; VPX Geographical address */
#define CONFIG_SYS_PCA953X_P0_GA1		0x02 /* PU; VPX Geographical address */
#define CONFIG_SYS_PCA953X_P0_GA2		0x04 /* PU; VPX Geographical address */
#define CONFIG_SYS_PCA953X_P0_GA3		0x08 /* PU; VPX Geographical address */
#define CONFIG_SYS_PCA953X_P0_GA4		0x10 /* PU; VPX Geographical address */
#define CONFIG_SYS_PCA953X_P0_GAP		0x20 /* PU; tied to VPX P0.GAP */
#define CONFIG_SYS_PCA953X_P1_SYSEN		0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */

/* PCA9557 @ 0x1f */
#define CONFIG_SYS_PCA953X_GPIO_VPX0		0x01 /* PU */
#define CONFIG_SYS_PCA953X_GPIO_VPX1		0x02 /* PU */
#define CONFIG_SYS_PCA953X_GPIO_VPX2		0x04 /* PU */
#define CONFIG_SYS_PCA953X_GPIO_VPX3		0x08 /* PU */
#define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL	0x10 /* PD; I2C master source for FRU SEEPROM */

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
/* PCIE1 - VPX P1 */
#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x40000000	/* 1G */
#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xe8000000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */

/* PCIE2 - PEX8518 */
#define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS	0xe8800000
#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000	/* 8M */

/*
 * Networking options
 */
#define CONFIG_TSEC_TBI
#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
#define CONFIG_ETHPRIME		"eTSEC2"

/*
 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
 * 1000mbps SGMII link
 */
#define CONFIG_TSEC_TBICR_SETTINGS ( \
		TBICR_PHY_RESET \
		| TBICR_FULL_DUPLEX \
		| TBICR_SPEED1_SET \
		)

#define CONFIG_TSEC1		1
#define CONFIG_TSEC1_NAME	"eTSEC1"
#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define CONFIG_HAS_ETH0

#define CONFIG_TSEC2		1
#define CONFIG_TSEC2_NAME	"eTSEC2"
#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_PHY_ADDR		2
#define TSEC2_PHYIDX		0
#define CONFIG_HAS_ETH1

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
#define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
#define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 16 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */

/*
 * Environment Configuration
 */

/*
 * Flash memory map:
 * fff80000 - ffffffff     Pri U-Boot (512 KB)
 * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
 * fff00000 - fff3ffff     Pri FDT (256KB)
 * fef00000 - ffefffff     Pri OS image (16MB)
 * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
 *
 * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
 * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
 * f7f00000 - f7f3ffff     Sec FDT (256KB)
 * f6f00000 - f7efffff     Sec OS image (16MB)
 * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
 */
#define CONFIG_UBOOT1_ENV_ADDR	__stringify(0xfff80000)
#define CONFIG_UBOOT2_ENV_ADDR	__stringify(0xf7f80000)
#define CONFIG_FDT1_ENV_ADDR	__stringify(0xfff00000)
#define CONFIG_FDT2_ENV_ADDR	__stringify(0xf7f00000)
#define CONFIG_OS1_ENV_ADDR	__stringify(0xfef00000)
#define CONFIG_OS2_ENV_ADDR	__stringify(0xf6f00000)

#define CONFIG_PROG_UBOOT1						\
	"$download_cmd $loadaddr $ubootfile; "				\
	"if test $? -eq 0; then "					\
		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
		"if test $? -ne 0; then "				\
			"echo PROGRAM FAILED; "				\
		"else; "						\
			"echo PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_UBOOT2						\
	"$download_cmd $loadaddr $ubootfile; "				\
	"if test $? -eq 0; then "					\
		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
		"if test $? -ne 0; then "				\
			"echo PROGRAM FAILED; "				\
		"else; "						\
			"echo PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_BOOT_OS_NET						\
	"$download_cmd $osaddr $osfile; "				\
	"if test $? -eq 0; then "					\
		"if test -n $fdtaddr; then "				\
			"$download_cmd $fdtaddr $fdtfile; "		\
			"if test $? -eq 0; then "			\
				"bootm $osaddr - $fdtaddr; "		\
			"else; "					\
				"echo FDT DOWNLOAD FAILED; "		\
			"fi; "						\
		"else; "						\
			"bootm $osaddr; "				\
		"fi; "							\
	"else; "							\
		"echo OS DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_OS1							\
	"$download_cmd $osaddr $osfile; "				\
	"if test $? -eq 0; then "					\
		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
		"if test $? -ne 0; then "				\
			"echo OS PROGRAM FAILED; "			\
		"else; "						\
			"echo OS PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo OS DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_OS2							\
	"$download_cmd $osaddr $osfile; "				\
	"if test $? -eq 0; then "					\
		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
		"if test $? -ne 0; then "				\
			"echo OS PROGRAM FAILED; "			\
		"else; "						\
			"echo OS PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo OS DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_FDT1						\
	"$download_cmd $fdtaddr $fdtfile; "				\
	"if test $? -eq 0; then "					\
		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
		"if test $? -ne 0; then "				\
			"echo FDT PROGRAM FAILED; "			\
		"else; "						\
			"echo FDT PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo FDT DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_FDT2						\
	"$download_cmd $fdtaddr $fdtfile; "				\
	"if test $? -eq 0; then "					\
		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
		"if test $? -ne 0; then "				\
			"echo FDT PROGRAM FAILED; "			\
		"else; "						\
			"echo FDT PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo FDT DOWNLOAD FAILED; "				\
	"fi;"

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"autoload=yes\0"						\
	"download_cmd=tftp\0"						\
	"console_args=console=ttyS0,115200\0"				\
	"root_args=root=/dev/nfs rw\0"					\
	"misc_args=ip=on\0"						\
	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
	"bootfile=/home/user/file\0"					\
	"osfile=/home/user/board.uImage\0"				\
	"fdtfile=/home/user/board.dtb\0"				\
	"ubootfile=/home/user/u-boot.bin\0"				\
	"fdtaddr=0x1e00000\0"						\
	"osaddr=0x1000000\0"						\
	"loadaddr=0x1000000\0"						\
	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
	"prog_os1="CONFIG_PROG_OS1"\0"					\
	"prog_os2="CONFIG_PROG_OS2"\0"					\
	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
	"bootcmd_flash1=run set_bootargs; "				\
		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
	"bootcmd_flash2=run set_bootargs; "				\
		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
	"bootcmd=run bootcmd_flash1\0"
#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
ccf0fdd0 PT	2	/*
	3	* Copyright 2008 Extreme Engineering Solutions, Inc.
	4	* Copyright 2007-2008 Freescale Semiconductor, Inc.
ccf0fdd0 PT	5	*/
	6
	7	/*
c00ac259	8	* xpedite537x board configuration file
ccf0fdd0 PT	9	*/
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
	13	/*
	14	* High Level Configuration Options
	15	*/
ccf0fdd0	16	#define CONFIG_SYS_BOARD_NAME "XPedite5370"
92af6549	17	#define CONFIG_SYS_FORM_3U_VPX 1
ccf0fdd0	18
ccf0fdd0	19	#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
b38eaec5 RD	20	#define CONFIG_PCIE1 1 /* PCIE controller 1 */
b38eaec5 RD	21	#define CONFIG_PCIE2 1 /* PCIE controller 2 */
ccf0fdd0	22	#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
842033e6	23	#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
ccf0fdd0	24	#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
ccf0fdd0	25
48618126 PT	26	/*
	27	* Multicore config
	28	*/
48618126 PT	29	#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
	30	#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
	31
ccf0fdd0 PT	32	/*
	33	* DDR config
	34	*/
ccf0fdd0 PT	35	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
	36	#define CONFIG_DDR_SPD
	37	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	38	#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
	39	#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
	40	#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
ccf0fdd0 PT	41	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	42	#define CONFIG_CHIP_SELECTS_PER_CTRL 1
	43	#define CONFIG_DDR_ECC
	44	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	45	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
	46	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	47	#define CONFIG_VERY_BIG_RAM
	48
	49	#ifndef __ASSEMBLY__
	50	extern unsigned long get_board_sys_clk(unsigned long dummy);
	51	extern unsigned long get_board_ddr_clk(unsigned long dummy);
	52	#endif
	53
	54	#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
	55	#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
	56
	57	/*
	58	* These can be toggled for performance analysis, otherwise use default.
	59	*/
	60	#define CONFIG_L2_CACHE /* toggle L2 cache */
	61	#define CONFIG_BTB /* toggle branch predition */
	62	#define CONFIG_ENABLE_36BIT_PHYS 1
	63
e46fedfe TT	64	#define CONFIG_SYS_CCSRBAR 0xef000000
e46fedfe TT	65	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
ccf0fdd0 PT	66
	67	/*
	68	* Diagnostics
	69	*/
66a8b440 PT	70	#define CONFIG_POST (CONFIG_SYS_POST_MEMORY \| \
66a8b440 PT	71	CONFIG_SYS_POST_I2C)
66a8b440 PT	72	/* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
66a8b440 PT	73	#define I2C_ADDR_IGNORE_LIST {0x50}
ccf0fdd0 PT	74
	75	/*
	76	* Memory map
	77	* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
	78	* 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
	79	* 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
	80	* 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
	81	* 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
	82	* 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
48618126	83	* 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
ccf0fdd0 PT	84	* 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
	85	* 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
	86	* 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
	87	* 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
	88	*/
	89
202d9487	90	#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 \| LCRR_EADC_3)
ccf0fdd0 PT	91
	92	/*
	93	* NAND flash configuration
	94	*/
	95	#define CONFIG_SYS_NAND_BASE 0xef800000
	96	#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
0a6d0c63 PT	97	#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
	98	CONFIG_SYS_NAND_BASE2}
	99	#define CONFIG_SYS_MAX_NAND_DEVICE 2
0a6d0c63	100	#define CONFIG_NAND_FSL_ELBC
ccf0fdd0 PT	101
	102	/*
	103	* NOR flash configuration
	104	*/
	105	#define CONFIG_SYS_FLASH_BASE 0xf8000000
	106	#define CONFIG_SYS_FLASH_BASE2 0xf0000000
	107	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
	108	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
	109	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	110	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	111	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
ccf0fdd0 PT	112	#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
ccf0fdd0 PT	113	{0xf7f40000, 0xc0000} }
14d0a02a	114	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
ccf0fdd0 PT	115
	116	/*
	117	* Chip select configuration
	118	*/
	119	/* NOR Flash 0 on CS0 */
	120	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \| \
	121	BR_PS_16 \| \
	122	BR_V)
	123	#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB \| \
	124	OR_GPCM_CSNT \| \
	125	OR_GPCM_XACS \| \
	126	OR_GPCM_ACS_DIV2 \| \
	127	OR_GPCM_SCY_8 \| \
	128	OR_GPCM_TRLX \| \
	129	OR_GPCM_EHTR \| \
	130	OR_GPCM_EAD)
	131
	132	/* NOR Flash 1 on CS1 */
	133	#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 \| \
	134	BR_PS_16 \| \
	135	BR_V)
	136	#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
	137
	138	/* NAND flash on CS2 */
	139	#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE \| \
	140	(2<<BR_DECC_SHIFT) \| \
	141	BR_PS_8 \| \
	142	BR_MS_FCM \| \
	143	BR_V)
	144
	145	/* NAND flash on CS2 */
	146	#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB \| \
	147	OR_FCM_PGS \| \
	148	OR_FCM_CSCT \| \
	149	OR_FCM_CST \| \
	150	OR_FCM_CHT \| \
	151	OR_FCM_SCY_1 \| \
	152	OR_FCM_TRLX \| \
	153	OR_FCM_EHTR)
	154
	155	/* NAND flash on CS3 */
	156	#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 \| \
	157	(2<<BR_DECC_SHIFT) \| \
	158	BR_PS_8 \| \
	159	BR_MS_FCM \| \
	160	BR_V)
	161	#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
	162
	163	/*
	164	* Use L1 as initial stack
	165	*/
	166	#define CONFIG_SYS_INIT_RAM_LOCK 1
	167	#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
553f0982	168	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
ccf0fdd0	169
25ddd1fb	170	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
ccf0fdd0 PT	171	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	172
	173	#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
	174	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
	175
	176	/*
	177	* Serial Port
	178	*/
ccf0fdd0 PT	179	#define CONFIG_SYS_NS16550_SERIAL
	180	#define CONFIG_SYS_NS16550_REG_SIZE 1
	181	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	182	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
	183	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
	184	#define CONFIG_SYS_BAUDRATE_TABLE \
	185	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
ccf0fdd0 PT	186	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	187	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	188
ccf0fdd0 PT	189	/*
	190	* I2C
	191	*/
00f792e0 HS	192	#define CONFIG_SYS_I2C
	193	#define CONFIG_SYS_I2C_FSL
	194	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	195	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	196	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	197	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	198	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	199	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
	200	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
ccf0fdd0 PT	201
	202	/* PEX8518 slave I2C interface */
	203	#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
	204
	205	/* I2C DS1631 temperature sensor */
66a8b440	206	#define CONFIG_SYS_I2C_LM90_ADDR 0x4c
ccf0fdd0 PT	207
	208	/* I2C EEPROM - AT24C128B */
	209	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
	210	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	211	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
	212	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
	213
	214	/* I2C RTC */
	215	#define CONFIG_RTC_M41T11 1
	216	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	217	#define CONFIG_SYS_M41T11_BASE_YEAR 2000
	218
ccf0fdd0 PT	219	/* GPIO */
	220	#define CONFIG_PCA953X
	221	#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
	222	#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
	223	#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
	224	#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
	225	#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
	226
	227	/*
	228	* PU = pulled high, PD = pulled low
	229	* I = input, O = output, IO = input/output
	230	*/
	231	/* PCA9557 @ 0x18*/
	232	#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
	233	#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
	234	#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
	235	#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
	236	#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
	237	#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
	238	#define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */
	239	#define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */
	240
	241	/* PCA9557 @ 0x1c*/
	242	#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
	243	#define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */
	244	#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
	245	#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
	246	#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
	247	#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
	248	#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
	249	#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
	250
	251	/* PCA9557 @ 0x1e*/
	252	#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
	253	#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
	254	#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
	255	#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
	256	#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
	257	#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */
	258	#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
	259
	260	/* PCA9557 @ 0x1f */
	261	#define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */
	262	#define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */
	263	#define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */
	264	#define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */
	265	#define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */
	266
	267	/*
	268	* General PCI
	269	* Memory space is mapped 1-1, but I/O space must start from 0.
	270	*/
	271	/* PCIE1 - VPX P1 */
9660c5de PT	272	#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
9660c5de PT	273	#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
ccf0fdd0	274	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
9660c5de	275	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
ccf0fdd0 PT	276	#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
	277	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
	278
	279	/* PCIE2 - PEX8518 */
9660c5de PT	280	#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
9660c5de PT	281	#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
ccf0fdd0	282	#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
9660c5de	283	#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
ccf0fdd0 PT	284	#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
	285	#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
	286
	287	/*
	288	* Networking options
	289	*/
ccf0fdd0	290	#define CONFIG_TSEC_TBI
ccf0fdd0 PT	291	#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
	292	#define CONFIG_ETHPRIME "eTSEC2"
	293
72c96a68 KG	294	/*
	295	* In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
	296	* 1000mbps SGMII link
	297	*/
	298	#define CONFIG_TSEC_TBICR_SETTINGS ( \
	299	TBICR_PHY_RESET \
	300	\| TBICR_FULL_DUPLEX \
	301	\| TBICR_SPEED1_SET \
	302	)
	303
ccf0fdd0 PT	304	#define CONFIG_TSEC1 1
	305	#define CONFIG_TSEC1_NAME "eTSEC1"
	306	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	307	#define TSEC1_PHY_ADDR 1
	308	#define TSEC1_PHYIDX 0
	309	#define CONFIG_HAS_ETH0
	310
	311	#define CONFIG_TSEC2 1
	312	#define CONFIG_TSEC2_NAME "eTSEC2"
	313	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	314	#define TSEC2_PHY_ADDR 2
	315	#define TSEC2_PHYIDX 0
	316	#define CONFIG_HAS_ETH1
	317
ccf0fdd0 PT	318	/*
	319	* Miscellaneous configurable options
	320	*/
ccf0fdd0	321	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
ccf0fdd0	322	#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
ccf0fdd0 PT	323	#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
	324
	325	/*
	326	* For booting Linux, the board info and command line data
	327	* have to be in the first 16 MB of memory, since this is
	328	* the maximum mapped by the Linux kernel during initialization.
	329	*/
	330	#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
39121c08	331	#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
ccf0fdd0	332
ccf0fdd0 PT	333	/*
	334	* Environment Configuration
	335	*/
ccf0fdd0 PT	336
	337	/*
	338	* Flash memory map:
	339	* fff80000 - ffffffff Pri U-Boot (512 KB)
	340	* fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
	341	* fff00000 - fff3ffff Pri FDT (256KB)
	342	* fef00000 - ffefffff Pri OS image (16MB)
	343	* f8000000 - feefffff Pri OS Use/Filesystem (111MB)
	344	*
	345	* f7f80000 - f7ffffff Sec U-Boot (512 KB)
	346	* f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
	347	* f7f00000 - f7f3ffff Sec FDT (256KB)
	348	* f6f00000 - f7efffff Sec OS image (16MB)
	349	* f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
	350	*/
5368c55d MV	351	#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
	352	#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
	353	#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
	354	#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
	355	#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
	356	#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
ccf0fdd0 PT	357
	358	#define CONFIG_PROG_UBOOT1 \
	359	"$download_cmd $loadaddr $ubootfile; " \
	360	"if test $? -eq 0; then " \
	361	"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
	362	"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
	363	"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
	364	"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
	365	"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
	366	"if test $? -ne 0; then " \
	367	"echo PROGRAM FAILED; " \
	368	"else; " \
	369	"echo PROGRAM SUCCEEDED; " \
	370	"fi; " \
	371	"else; " \
	372	"echo DOWNLOAD FAILED; " \
	373	"fi;"
	374
	375	#define CONFIG_PROG_UBOOT2 \
	376	"$download_cmd $loadaddr $ubootfile; " \
	377	"if test $? -eq 0; then " \
	378	"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
	379	"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
	380	"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
	381	"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
	382	"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
	383	"if test $? -ne 0; then " \
	384	"echo PROGRAM FAILED; " \
	385	"else; " \
	386	"echo PROGRAM SUCCEEDED; " \
	387	"fi; " \
	388	"else; " \
	389	"echo DOWNLOAD FAILED; " \
	390	"fi;"
	391
	392	#define CONFIG_BOOT_OS_NET \
	393	"$download_cmd $osaddr $osfile; " \
	394	"if test $? -eq 0; then " \
	395	"if test -n $fdtaddr; then " \
	396	"$download_cmd $fdtaddr $fdtfile; " \
	397	"if test $? -eq 0; then " \
	398	"bootm $osaddr - $fdtaddr; " \
	399	"else; " \
	400	"echo FDT DOWNLOAD FAILED; " \
	401	"fi; " \
	402	"else; " \
	403	"bootm $osaddr; " \
	404	"fi; " \
	405	"else; " \
	406	"echo OS DOWNLOAD FAILED; " \
	407	"fi;"
	408
	409	#define CONFIG_PROG_OS1 \
	410	"$download_cmd $osaddr $osfile; " \
	411	"if test $? -eq 0; then " \
	412	"erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
	413	"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
	414	"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
	415	"if test $? -ne 0; then " \
	416	"echo OS PROGRAM FAILED; " \
	417	"else; " \
	418	"echo OS PROGRAM SUCCEEDED; " \
	419	"fi; " \
	420	"else; " \
421	"echo OS DOWNLOAD FAILED; " \
422	"fi;"
423
424	#define CONFIG_PROG_OS2 \
425	"$download_cmd $osaddr $osfile; " \
426	"if test $? -eq 0; then " \
427	"erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
428	"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
429	"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
430	"if test $? -ne 0; then " \
431	"echo OS PROGRAM FAILED; " \
432	"else; " \
433	"echo OS PROGRAM SUCCEEDED; " \
434	"fi; " \
435	"else; " \
436	"echo OS DOWNLOAD FAILED; " \
437	"fi;"
438
439	#define CONFIG_PROG_FDT1 \
440	"$download_cmd $fdtaddr $fdtfile; " \
441	"if test $? -eq 0; then " \
442	"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
443	"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
444	"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
445	"if test $? -ne 0; then " \
446	"echo FDT PROGRAM FAILED; " \
447	"else; " \
448	"echo FDT PROGRAM SUCCEEDED; " \
449	"fi; " \
450	"else; " \
451	"echo FDT DOWNLOAD FAILED; " \
452	"fi;"
453
454	#define CONFIG_PROG_FDT2 \
455	"$download_cmd $fdtaddr $fdtfile; " \
456	"if test $? -eq 0; then " \
457	"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
458	"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
459	"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
460	"if test $? -ne 0; then " \
461	"echo FDT PROGRAM FAILED; " \
462	"else; " \
463	"echo FDT PROGRAM SUCCEEDED; " \
464	"fi; " \
465	"else; " \
466	"echo FDT DOWNLOAD FAILED; " \
467	"fi;"
468
469	#define CONFIG_EXTRA_ENV_SETTINGS \
470	"autoload=yes\0" \
471	"download_cmd=tftp\0" \
472	"console_args=console=ttyS0,115200\0" \
473	"root_args=root=/dev/nfs rw\0" \
474	"misc_args=ip=on\0" \
475	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
476	"bootfile=/home/user/file\0" \
c00ac259 PT	477	"osfile=/home/user/board.uImage\0" \
c00ac259 PT	478	"fdtfile=/home/user/board.dtb\0" \
ccf0fdd0	479	"ubootfile=/home/user/u-boot.bin\0" \
b24a4f62	480	"fdtaddr=0x1e00000\0" \
ccf0fdd0 PT	481	"osaddr=0x1000000\0" \
	482	"loadaddr=0x1000000\0" \
	483	"prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
	484	"prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
	485	"prog_os1="CONFIG_PROG_OS1"\0" \
	486	"prog_os2="CONFIG_PROG_OS2"\0" \
	487	"prog_fdt1="CONFIG_PROG_FDT1"\0" \
	488	"prog_fdt2="CONFIG_PROG_FDT2"\0" \
	489	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
	490	"bootcmd_flash1=run set_bootargs; " \
	491	"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
	492	"bootcmd_flash2=run set_bootargs; " \
	493	"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
	494	"bootcmd=run bootcmd_flash1\0"
	495	#endif /* __CONFIG_H */