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ca0e7748 WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net | |
4 | * | |
5 | * (C) Copyright 2002 | |
6 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
7 | * Marius Groeger <mgroeger@sysgo.de> | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
ca0e7748 WD |
31 | /* High Level Configuration Options */ |
32 | #define CONFIG_PXA250 1 /* This is an PXA250 CPU */ | |
33 | #define CONFIG_XSENGINE 1 | |
34 | #define CONFIG_MMC 1 | |
e78220f6 | 35 | #define CONFIG_DOS_PARTITION 1 |
4124382d | 36 | #define BOARD_LATE_INIT 1 |
ca0e7748 | 37 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
b3acb6cd JCPV |
38 | /* we will never enable dcache, because we have to setup MMU first */ |
39 | #define CONFIG_SYS_NO_DCACHE | |
40 | ||
94a33129 | 41 | #define CONFIG_SYS_HZ 1000 |
6d0f6bcf | 42 | #define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ |
ca0e7748 WD |
43 | |
44 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
45 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ | |
46 | #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ | |
47 | #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ | |
48 | #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ | |
49 | #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ | |
50 | #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ | |
51 | #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ | |
52 | #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ | |
6d0f6bcf JCPV |
53 | #define CONFIG_SYS_DRAM_BASE 0xa0000000 |
54 | #define CONFIG_SYS_DRAM_SIZE 0x04000000 | |
ca0e7748 WD |
55 | |
56 | /* FLASH organization */ | |
6d0f6bcf JCPV |
57 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
58 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ | |
ca0e7748 WD |
59 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
60 | #define PHYS_FLASH_2 0x00000000 /* Flash Bank #2 */ | |
61 | #define PHYS_FLASH_SECT_SIZE 0x00020000 /* 127 KB sectors */ | |
6d0f6bcf | 62 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
700a0c64 WD |
63 | |
64 | /* | |
65 | * JFFS2 partitions | |
66 | */ | |
67 | /* No command line, one static partition, whole device */ | |
68d7d651 | 68 | #undef CONFIG_CMD_MTDPARTS |
700a0c64 WD |
69 | #define CONFIG_JFFS2_DEV "nor0" |
70 | #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF | |
71 | #define CONFIG_JFFS2_PART_OFFSET 0x00000000 | |
72 | ||
73 | /* mtdparts command line support */ | |
74 | /* Note: fake mtd_id used, no linux mtd map file */ | |
75 | /* | |
68d7d651 | 76 | #define CONFIG_CMD_MTDPARTS |
700a0c64 WD |
77 | #define MTDIDS_DEFAULT "nor0=xsengine-0" |
78 | #define MTDPARTS_DEFAULT "mtdparts=xsengine-0:256k(uboot),1m(kernel1),8m(kernel2)" | |
79 | */ | |
ca0e7748 WD |
80 | |
81 | /* Environment settings */ | |
82 | #define CONFIG_ENV_OVERWRITE | |
5a1aceb0 | 83 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
84 | #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector (after monitor)*/ |
85 | #define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE /* Size of the Environment Sector */ | |
86 | #define CONFIG_ENV_SIZE 0x4000 /* 16kB Total Size of Environment Sector */ | |
ca0e7748 WD |
87 | |
88 | /* timeout values are in ticks */ | |
6d0f6bcf JCPV |
89 | #define CONFIG_SYS_FLASH_ERASE_TOUT (75*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
90 | #define CONFIG_SYS_FLASH_WRITE_TOUT (50*CONFIG_SYS_HZ) /* Timeout for Flash Write */ | |
ca0e7748 WD |
91 | |
92 | /* Size of malloc() pool */ | |
6d0f6bcf JCPV |
93 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) |
94 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
ca0e7748 WD |
95 | |
96 | /* Hardware drivers */ | |
7194ab80 BW |
97 | #define CONFIG_NET_MULTI |
98 | #define CONFIG_SMC91111 | |
ca0e7748 | 99 | #define CONFIG_SMC91111_BASE 0x04000300 |
4124382d | 100 | #define CONFIG_SMC_USE_32_BIT 1 |
ca0e7748 WD |
101 | |
102 | /* select serial console configuration */ | |
379be585 | 103 | #define CONFIG_PXA_SERIAL |
ca0e7748 WD |
104 | #define CONFIG_FFUART 1 |
105 | ||
106 | /* allow to overwrite serial and ethaddr */ | |
107 | #define CONFIG_BAUDRATE 115200 | |
ca0e7748 | 108 | |
079a136c JL |
109 | /* |
110 | * BOOTP options | |
111 | */ | |
112 | #define CONFIG_BOOTP_BOOTFILESIZE | |
113 | #define CONFIG_BOOTP_BOOTPATH | |
114 | #define CONFIG_BOOTP_GATEWAY | |
115 | #define CONFIG_BOOTP_HOSTNAME | |
116 | ||
117 | ||
dca3b3d6 JL |
118 | /* |
119 | * Command line configuration. | |
120 | */ | |
121 | #include <config_cmd_default.h> | |
122 | ||
dca3b3d6 JL |
123 | #define CONFIG_CMD_FAT |
124 | #define CONFIG_CMD_PING | |
125 | #define CONFIG_CMD_JFFS2 | |
126 | ||
ca0e7748 WD |
127 | |
128 | #define CONFIG_BOOTDELAY 3 | |
129 | #define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF | |
130 | #define CONFIG_NETMASK 255.255.255.0 | |
131 | #define CONFIG_IPADDR 192.168.1.50 | |
132 | #define CONFIG_SERVERIP 192.168.1.2 | |
133 | #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS1,115200" | |
134 | #define CONFIG_CMDLINE_TAG | |
135 | ||
136 | /* Miscellaneous configurable options */ | |
6d0f6bcf JCPV |
137 | #define CONFIG_SYS_HUSH_PARSER 1 |
138 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
139 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
140 | #define CONFIG_SYS_PROMPT "XS-Engine u-boot> " /* Monitor Command Prompt */ | |
141 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
142 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
143 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
144 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
145 | #define CONFIG_SYS_MEMTEST_START 0xA0400000 /* memtest works on */ | |
146 | #define CONFIG_SYS_MEMTEST_END 0xA0800000 /* 4 ... 8 MB in DRAM */ | |
6d0f6bcf | 147 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */ |
6d0f6bcf | 148 | #define CONFIG_SYS_LOAD_ADDR 0xA0000000 /* load kernel to this address */ |
ca0e7748 | 149 | |
b03d92e5 JCPV |
150 | #ifdef CONFIG_MMC |
151 | #define CONFIG_PXA_MMC | |
152 | #define CONFIG_CMD_MMC | |
153 | #define CONFIG_SYS_MMC_BASE 0xF0000000 | |
154 | #endif | |
155 | ||
ca0e7748 WD |
156 | /* Stack sizes - The stack sizes are set up in start.S using the settings below */ |
157 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
158 | #ifdef CONFIG_USE_IRQ | |
159 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
160 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
161 | #endif | |
162 | ||
163 | /* GP set register */ | |
6d0f6bcf JCPV |
164 | #define CONFIG_SYS_GPSR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */ |
165 | #define CONFIG_SYS_GPSR1_VAL 0x00020000 /* nPWE */ | |
166 | #define CONFIG_SYS_GPSR2_VAL 0x0000C000 /* CS2, CS3 */ | |
ca0e7748 WD |
167 | |
168 | /* GP clear register */ | |
6d0f6bcf JCPV |
169 | #define CONFIG_SYS_GPCR0_VAL 0x00000000 |
170 | #define CONFIG_SYS_GPCR1_VAL 0x00000000 | |
171 | #define CONFIG_SYS_GPCR2_VAL 0x00000000 | |
ca0e7748 WD |
172 | |
173 | /* GP direction register */ | |
6d0f6bcf JCPV |
174 | #define CONFIG_SYS_GPDR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */ |
175 | #define CONFIG_SYS_GPDR1_VAL 0x00022A80 /* nPWE, FFUART + BTUART pins */ | |
176 | #define CONFIG_SYS_GPDR2_VAL 0x0000C000 /* CS2, CS3 */ | |
ca0e7748 WD |
177 | |
178 | /* GP rising edge detect register */ | |
6d0f6bcf JCPV |
179 | #define CONFIG_SYS_GRER0_VAL 0x00000000 |
180 | #define CONFIG_SYS_GRER1_VAL 0x00000000 | |
181 | #define CONFIG_SYS_GRER2_VAL 0x00000000 | |
ca0e7748 WD |
182 | |
183 | /* GP falling edge detect register */ | |
6d0f6bcf JCPV |
184 | #define CONFIG_SYS_GFER0_VAL 0x00000000 |
185 | #define CONFIG_SYS_GFER1_VAL 0x00000000 | |
186 | #define CONFIG_SYS_GFER2_VAL 0x00000000 | |
ca0e7748 WD |
187 | |
188 | /* GP alternate function register */ | |
6d0f6bcf JCPV |
189 | #define CONFIG_SYS_GAFR0_L_VAL 0x80000000 /* CS1 */ |
190 | #define CONFIG_SYS_GAFR0_U_VAL 0x00000010 /* RDY */ | |
191 | #define CONFIG_SYS_GAFR1_L_VAL 0x09988050 /* FFUART + BTUART pins */ | |
192 | #define CONFIG_SYS_GAFR1_U_VAL 0x00000008 /* nPWE */ | |
193 | #define CONFIG_SYS_GAFR2_L_VAL 0xA0000000 /* CS2, CS3 */ | |
194 | #define CONFIG_SYS_GAFR2_U_VAL 0x00000000 | |
195 | ||
196 | #define CONFIG_SYS_PSSR_VAL 0x00000020 /* Power manager sleep status */ | |
197 | #define CONFIG_SYS_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU */ | |
198 | #define CONFIG_SYS_CKEN_VAL 0x000000C0 /* BTUART and FFUART enabled */ | |
199 | #define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */ | |
ca0e7748 WD |
200 | |
201 | /* Memory settings */ | |
6d0f6bcf | 202 | #define CONFIG_SYS_MSC0_VAL 0x25F425F0 |
ca0e7748 WD |
203 | |
204 | /* MDCNFG: SDRAM Configuration Register */ | |
6d0f6bcf | 205 | #define CONFIG_SYS_MDCNFG_VAL 0x000009C9 |
ca0e7748 WD |
206 | |
207 | /* MDREFR: SDRAM Refresh Control Register */ | |
6d0f6bcf | 208 | #define CONFIG_SYS_MDREFR_VAL 0x00018018 |
ca0e7748 WD |
209 | |
210 | /* MDMRS: Mode Register Set Configuration Register */ | |
6d0f6bcf | 211 | #define CONFIG_SYS_MDMRS_VAL 0x00220022 |
ca0e7748 WD |
212 | |
213 | #endif /* __CONFIG_H */ |