[people/ms/u-boot.git] / include / configs / xsengine.h

/*
 * (C) Copyright 2002
 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_PXA250			1		/* This is an PXA250 CPU    */
#define CONFIG_XSENGINE			1
#define CONFIG_MMC			1
#define CONFIG_DOS_PARTITION		1
#define OARD_LATE_INIT			1
#undef  CONFIG_USE_IRQ					/* we don't need IRQ/FIQ stuff */
#define CFG_HZ				3686400		/* incrementer freq: 3.6864 MHz */

#undef  CONFIG_USE_IRQ					/* we don't need IRQ/FIQ stuff */
#define CFG_HZ				3686400		/* incrementer freq: 3.6864 MHz */
#define CFG_CPUSPEED			0x161           /* set core clock to 400/200/100 MHz */

#define CONFIG_NR_DRAM_BANKS		1		/* we have 1 bank of DRAM */
#define PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE		0x04000000	/* 64 MB */
#define PHYS_SDRAM_2			0xa4000000	/* SDRAM Bank #2 */
#define PHYS_SDRAM_2_SIZE		0x00000000	/* 0 MB */
#define PHYS_SDRAM_3			0xa8000000	/* SDRAM Bank #3 */
#define PHYS_SDRAM_3_SIZE		0x00000000	/* 0 MB */
#define PHYS_SDRAM_4			0xac000000	/* SDRAM Bank #4 */
#define PHYS_SDRAM_4_SIZE		0x00000000	/* 0 MB */
#define CFG_DRAM_BASE			0xa0000000
#define CFG_DRAM_SIZE			0x04000000

/* FLASH organization */
#define CFG_MAX_FLASH_BANKS		1		/* max number of memory banks           */
#define CFG_MAX_FLASH_SECT		128		/* max number of sectors on one chip    */
#define PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
#define PHYS_FLASH_2			0x00000000	/* Flash Bank #2 */
#define PHYS_FLASH_SECT_SIZE		0x00020000	/* 127 KB sectors */
#define CFG_FLASH_BASE			PHYS_FLASH_1

/*
 * JFFS2 partitions
 */
/* No command line, one static partition, whole device */
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV		"nor0"
#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET	0x00000000

/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT		"nor0=xsengine-0"
#define MTDPARTS_DEFAULT	"mtdparts=xsengine-0:256k(uboot),1m(kernel1),8m(kernel2)"
*/

/* Environment settings */
#define CONFIG_ENV_OVERWRITE
#define CFG_ENV_IS_IN_FLASH             1
#define CFG_ENV_ADDR                    (PHYS_FLASH_1 + 0x40000)	/* Addr of Environment Sector (after monitor)*/
#define CFG_ENV_SECT_SIZE               PHYS_FLASH_SECT_SIZE		/* Size of the Environment Sector */
#define CFG_ENV_SIZE                    0x4000				/* 16kB Total Size of Environment Sector */

/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT		(75*CFG_HZ) 	/* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT		(50*CFG_HZ) 	/* Timeout for Flash Write */

/* Size of malloc() pool */
#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 256*1024)
#define CFG_GBL_DATA_SIZE		128		/* size in bytes reserved for initial data */

/* Hardware drivers */
#define CONFIG_DRIVER_SMC91111
#define CONFIG_SMC91111_BASE		0x04000300
#define CONFIG_SMC_USE_32_BIT 		1

/* select serial console configuration */
#define CONFIG_FFUART			1

/* allow to overwrite serial and ethaddr */
#define CONFIG_BAUDRATE			115200

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_MMC
#define CONFIG_CMD_FAT
#define CONFIG_CMD_PING
#define CONFIG_CMD_JFFS2


#define CONFIG_BOOTDELAY		3
#define CONFIG_ETHADDR			FF:FF:FF:FF:FF:FF
#define CONFIG_NETMASK			255.255.255.0
#define CONFIG_IPADDR			192.168.1.50
#define CONFIG_SERVERIP			192.168.1.2
#define CONFIG_BOOTARGS			"root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS1,115200"
#define CONFIG_CMDLINE_TAG

/* Miscellaneous configurable options */
#define CFG_HUSH_PARSER			1
#define CFG_PROMPT_HUSH_PS2		"> "
#define CFG_LONGHELP								/* undef to save memory	*/
#define CFG_PROMPT			"XS-Engine u-boot> "			/* Monitor Command Prompt */
#define CFG_CBSIZE			256					/* Console I/O Buffer Size */
#define CFG_PBSIZE			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) 	/* Print Buffer Size */
#define CFG_MAXARGS			16					/* max number of command args */
#define CFG_BARGSIZE			CFG_CBSIZE				/* Boot Argument Buffer Size */
#define CFG_MEMTEST_START		0xA0400000				/* memtest works on     */
#define CFG_MEMTEST_END			0xA0800000				/* 4 ... 8 MB in DRAM   */
#undef  CFG_CLKS_IN_HZ          						/* everything, incl board info, in Hz */
#define CFG_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200 }	/* valid baudrates */
#define CFG_MMC_BASE			0xF0000000
#define CFG_LOAD_ADDR           	0xA0000000				/* load kernel to this address   */

/* Stack sizes - The stack sizes are set up in start.S using the settings below */
#define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
#ifdef  CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ		(4*1024)	/* IRQ stack */
#define CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */
#endif

/* GP set register */
#define CFG_GPSR0_VAL			0x0000A000	/* CS1, PROG(FPGA) */
#define CFG_GPSR1_VAL			0x00020000	/* nPWE */
#define CFG_GPSR2_VAL			0x0000C000	/* CS2, CS3 */

/* GP clear register */
#define CFG_GPCR0_VAL			0x00000000
#define CFG_GPCR1_VAL			0x00000000
#define CFG_GPCR2_VAL			0x00000000

/* GP direction register */
#define CFG_GPDR0_VAL			0x0000A000	/* CS1, PROG(FPGA) */
#define CFG_GPDR1_VAL			0x00022A80	/* nPWE, FFUART + BTUART pins */
#define CFG_GPDR2_VAL			0x0000C000  	/* CS2, CS3 */

/* GP rising edge detect register */
#define CFG_GRER0_VAL			0x00000000
#define CFG_GRER1_VAL			0x00000000
#define CFG_GRER2_VAL			0x00000000

/* GP falling edge detect register */
#define CFG_GFER0_VAL			0x00000000
#define CFG_GFER1_VAL			0x00000000
#define CFG_GFER2_VAL			0x00000000

/* GP alternate function register */
#define CFG_GAFR0_L_VAL			0x80000000	/* CS1 */
#define CFG_GAFR0_U_VAL			0x00000010	/* RDY */
#define CFG_GAFR1_L_VAL			0x09988050	/* FFUART + BTUART pins */
#define CFG_GAFR1_U_VAL			0x00000008	/* nPWE */
#define CFG_GAFR2_L_VAL			0xA0000000  	/* CS2, CS3 */
#define CFG_GAFR2_U_VAL			0x00000000

#define CFG_PSSR_VAL			0x00000020	/* Power manager sleep status */
#define CFG_CCCR_VAL			0x00000161	/* 100 MHz memory, 400 MHz CPU  */
#define CFG_CKEN_VAL			0x000000C0	/* BTUART and FFUART enabled    */
#define CFG_ICMR_VAL			0x00000000	/* No interrupts enabled        */

/* Memory settings */
#define CFG_MSC0_VAL			0x25F425F0

/* MDCNFG: SDRAM Configuration Register */
#define CFG_MDCNFG_VAL			0x000009C9

/* MDREFR: SDRAM Refresh Control Register */
#define CFG_MDREFR_VAL			0x00018018

/* MDMRS: Mode Register Set Configuration Register */
#define CFG_MDMRS_VAL			0x00220022

#endif	/* __CONFIG_H */
Commit	Line	Data
ca0e7748 WD	1	/*
	2	* (C) Copyright 2002
	3	* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
	4	*
	5	* (C) Copyright 2002
	6	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	7	* Marius Groeger <mgroeger@sysgo.de>
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
ca0e7748 WD	31	/* High Level Configuration Options */
	32	#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
	33	#define CONFIG_XSENGINE 1
	34	#define CONFIG_MMC 1
e78220f6	35	#define CONFIG_DOS_PARTITION 1
cd9cb62f	36	#define OARD_LATE_INIT 1
ca0e7748 WD	37	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	38	#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
	39
	40	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	41	#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
	42	#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
	43
	44	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
	45	#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
	46	#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
	47	#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
	48	#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
	49	#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
	50	#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
	51	#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
	52	#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
	53	#define CFG_DRAM_BASE 0xa0000000
	54	#define CFG_DRAM_SIZE 0x04000000
	55
	56	/* FLASH organization */
	57	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	58	#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
	59	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
	60	#define PHYS_FLASH_2 0x00000000 /* Flash Bank #2 */
	61	#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 127 KB sectors */
	62	#define CFG_FLASH_BASE PHYS_FLASH_1
700a0c64 WD	63
	64	/*
	65	* JFFS2 partitions
	66	*/
	67	/* No command line, one static partition, whole device */
	68	#undef CONFIG_JFFS2_CMDLINE
	69	#define CONFIG_JFFS2_DEV "nor0"
	70	#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
	71	#define CONFIG_JFFS2_PART_OFFSET 0x00000000
	72
	73	/* mtdparts command line support */
	74	/* Note: fake mtd_id used, no linux mtd map file */
	75	/*
	76	#define CONFIG_JFFS2_CMDLINE
	77	#define MTDIDS_DEFAULT "nor0=xsengine-0"
	78	#define MTDPARTS_DEFAULT "mtdparts=xsengine-0:256k(uboot),1m(kernel1),8m(kernel2)"
	79	*/
ca0e7748 WD	80
	81	/* Environment settings */
	82	#define CONFIG_ENV_OVERWRITE
	83	#define CFG_ENV_IS_IN_FLASH 1
	84	#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector (after monitor)*/
	85	#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE /* Size of the Environment Sector */
	86	#define CFG_ENV_SIZE 0x4000 /* 16kB Total Size of Environment Sector */
	87
	88	/* timeout values are in ticks */
	89	#define CFG_FLASH_ERASE_TOUT (75CFG_HZ) / Timeout for Flash Erase */
	90	#define CFG_FLASH_WRITE_TOUT (50CFG_HZ) / Timeout for Flash Write */
	91
	92	/* Size of malloc() pool */
	93	#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024)
	94	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	95
	96	/* Hardware drivers */
	97	#define CONFIG_DRIVER_SMC91111
	98	#define CONFIG_SMC91111_BASE 0x04000300
	99	#define CONFIG_SMC_USE_32_BIT 1
	100
	101	/* select serial console configuration */
	102	#define CONFIG_FFUART 1
	103
	104	/* allow to overwrite serial and ethaddr */
	105	#define CONFIG_BAUDRATE 115200
ca0e7748	106
079a136c JL	107	/*
	108	* BOOTP options
	109	*/
	110	#define CONFIG_BOOTP_BOOTFILESIZE
	111	#define CONFIG_BOOTP_BOOTPATH
	112	#define CONFIG_BOOTP_GATEWAY
	113	#define CONFIG_BOOTP_HOSTNAME
	114
	115
dca3b3d6 JL	116	/*
	117	* Command line configuration.
	118	*/
	119	#include <config_cmd_default.h>
	120
	121	#define CONFIG_CMD_MMC
	122	#define CONFIG_CMD_FAT
	123	#define CONFIG_CMD_PING
	124	#define CONFIG_CMD_JFFS2
	125
ca0e7748 WD	126
	127	#define CONFIG_BOOTDELAY 3
	128	#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
	129	#define CONFIG_NETMASK 255.255.255.0
	130	#define CONFIG_IPADDR 192.168.1.50
	131	#define CONFIG_SERVERIP 192.168.1.2
	132	#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS1,115200"
	133	#define CONFIG_CMDLINE_TAG
	134
	135	/* Miscellaneous configurable options */
	136	#define CFG_HUSH_PARSER 1
	137	#define CFG_PROMPT_HUSH_PS2 "> "
	138	#define CFG_LONGHELP /* undef to save memory */
	139	#define CFG_PROMPT "XS-Engine u-boot> " /* Monitor Command Prompt */
	140	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	141	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	142	#define CFG_MAXARGS 16 /* max number of command args */
	143	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	144	#define CFG_MEMTEST_START 0xA0400000 /* memtest works on */
	145	#define CFG_MEMTEST_END 0xA0800000 /* 4 ... 8 MB in DRAM */
	146	#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
	147	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */
	148	#define CFG_MMC_BASE 0xF0000000
	149	#define CFG_LOAD_ADDR 0xA0000000 /* load kernel to this address */
	150
	151	/* Stack sizes - The stack sizes are set up in start.S using the settings below */
	152	#define CONFIG_STACKSIZE (1281024) / regular stack */
	153	#ifdef CONFIG_USE_IRQ
	154	#define CONFIG_STACKSIZE_IRQ (41024) / IRQ stack */
	155	#define CONFIG_STACKSIZE_FIQ (41024) / FIQ stack */
	156	#endif
	157
	158	/* GP set register */
	159	#define CFG_GPSR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */
	160	#define CFG_GPSR1_VAL 0x00020000 /* nPWE */
	161	#define CFG_GPSR2_VAL 0x0000C000 /* CS2, CS3 */
	162
	163	/* GP clear register */
	164	#define CFG_GPCR0_VAL 0x00000000
	165	#define CFG_GPCR1_VAL 0x00000000
	166	#define CFG_GPCR2_VAL 0x00000000
	167
	168	/* GP direction register */
	169	#define CFG_GPDR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */
	170	#define CFG_GPDR1_VAL 0x00022A80 /* nPWE, FFUART + BTUART pins */
	171	#define CFG_GPDR2_VAL 0x0000C000 /* CS2, CS3 */
	172
	173	/* GP rising edge detect register */
	174	#define CFG_GRER0_VAL 0x00000000
	175	#define CFG_GRER1_VAL 0x00000000
	176	#define CFG_GRER2_VAL 0x00000000
	177
	178	/* GP falling edge detect register */
	179	#define CFG_GFER0_VAL 0x00000000
	180	#define CFG_GFER1_VAL 0x00000000
	181	#define CFG_GFER2_VAL 0x00000000
	182
	183	/* GP alternate function register */
	184	#define CFG_GAFR0_L_VAL 0x80000000 /* CS1 */
	185	#define CFG_GAFR0_U_VAL 0x00000010 /* RDY */
	186	#define CFG_GAFR1_L_VAL 0x09988050 /* FFUART + BTUART pins */
	187	#define CFG_GAFR1_U_VAL 0x00000008 /* nPWE */
	188	#define CFG_GAFR2_L_VAL 0xA0000000 /* CS2, CS3 */
	189	#define CFG_GAFR2_U_VAL 0x00000000
190
191	#define CFG_PSSR_VAL 0x00000020 /* Power manager sleep status */
192	#define CFG_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU */
193	#define CFG_CKEN_VAL 0x000000C0 /* BTUART and FFUART enabled */
194	#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */
195
196	/* Memory settings */
197	#define CFG_MSC0_VAL 0x25F425F0
198
199	/* MDCNFG: SDRAM Configuration Register */
200	#define CFG_MDCNFG_VAL 0x000009C9
201
202	/* MDREFR: SDRAM Refresh Control Register */
203	#define CFG_MDREFR_VAL 0x00018018
204
205	/* MDMRS: Mode Register Set Configuration Register */
206	#define CFG_MDMRS_VAL 0x00220022
207
208	#endif /* __CONFIG_H */