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7e270ec3 CZ |
1 | /* |
2 | * Copyright (C) 2007-2013 Tensilica, Inc. | |
3 | * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
11 | #include <asm/arch/core.h> | |
12 | #include <asm/addrspace.h> | |
13 | #include <asm/config.h> | |
14 | ||
15 | /* | |
16 | * The 'xtfpga' board describes a set of very similar boards with only minimal | |
17 | * differences. | |
18 | */ | |
19 | ||
20 | /*=====================*/ | |
21 | /* Board and Processor */ | |
22 | /*=====================*/ | |
23 | ||
24 | #define CONFIG_XTFPGA | |
25 | ||
26 | /* FPGA CPU freq after init */ | |
27 | #define CONFIG_SYS_CLK_FREQ (gd->cpu_clk) | |
28 | ||
29 | /*===================*/ | |
30 | /* RAM Layout */ | |
31 | /*===================*/ | |
32 | ||
33 | #if XCHAL_HAVE_PTP_MMU | |
34 | #define CONFIG_SYS_MEMORY_BASE \ | |
35 | (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR) | |
36 | #define CONFIG_SYS_IO_BASE 0xf0000000 | |
37 | #else | |
38 | #define CONFIG_SYS_MEMORY_BASE 0x60000000 | |
39 | #define CONFIG_SYS_IO_BASE 0x90000000 | |
40 | #define CONFIG_MAX_MEM_MAPPED 0x10000000 | |
41 | #endif | |
42 | ||
43 | /* Onboard RAM sizes: | |
44 | * | |
45 | * LX60 0x04000000 64 MB | |
46 | * LX110 0x03000000 48 MB | |
47 | * LX200 0x06000000 96 MB | |
48 | * ML605 0x18000000 384 MB | |
49 | * KC705 0x38000000 896 MB | |
50 | * | |
51 | * noMMU configurations can only see first 256MB of onboard memory. | |
52 | */ | |
53 | ||
54 | #if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000 | |
55 | #define CONFIG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE | |
56 | #else | |
57 | #define CONFIG_SYS_SDRAM_SIZE 0x10000000 | |
58 | #endif | |
59 | ||
60 | #define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000) | |
61 | ||
62 | /* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */ | |
63 | #ifdef CONFIG_XTFPGA_LX60 | |
64 | # define CONFIG_SYS_MONITOR_LEN 0x00020000 /* 128KB */ | |
65 | #else | |
66 | # define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */ | |
67 | #endif | |
68 | ||
69 | #define CONFIG_SYS_STACKSIZE (512 << 10) /* stack 512KB */ | |
70 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* heap 256KB */ | |
71 | ||
72 | /* Linux boot param area in RAM (used only when booting linux) */ | |
73 | #define CONFIG_SYS_BOOTPARAMS_LEN (64 << 10) | |
74 | ||
75 | /* Memory test is destructive so default must not overlap vectors or U-Boot*/ | |
76 | #define CONFIG_SYS_MEMTEST_START MEMADDR(0x01000000) | |
77 | #define CONFIG_SYS_MEMTEST_END MEMADDR(0x02000000) | |
78 | ||
79 | /* Load address for stand-alone applications. | |
80 | * MEMADDR cannot be used here, because the definition needs to be | |
81 | * a plain number as it's used as -Ttext argument for ld in standalone | |
82 | * example makefile. | |
83 | * Handle noMMU vs MMUv2 vs MMUv3 distinction here manually. | |
84 | */ | |
85 | #if XCHAL_HAVE_PTP_MMU | |
86 | #if XCHAL_VECBASE_RESET_VADDR == XCHAL_VECBASE_RESET_PADDR | |
87 | #define CONFIG_STANDALONE_LOAD_ADDR 0x00800000 | |
88 | #else | |
89 | #define CONFIG_STANDALONE_LOAD_ADDR 0xd0800000 | |
90 | #endif | |
91 | #else | |
92 | #define CONFIG_STANDALONE_LOAD_ADDR 0x60800000 | |
93 | #endif | |
94 | ||
95 | #if defined(CONFIG_MAX_MEM_MAPPED) && \ | |
96 | CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE | |
97 | #define CONFIG_SYS_MEMORY_SIZE CONFIG_MAX_MEM_MAPPED | |
98 | #else | |
99 | #define CONFIG_SYS_MEMORY_SIZE CONFIG_SYS_SDRAM_SIZE | |
100 | #endif | |
101 | ||
102 | #define CONFIG_SYS_MEMORY_TOP MEMADDR(CONFIG_SYS_MEMORY_SIZE) | |
103 | #define CONFIG_SYS_TEXT_ADDR \ | |
104 | (CONFIG_SYS_MEMORY_TOP - CONFIG_SYS_MONITOR_LEN) | |
105 | ||
106 | /* Used by tftpboot; env var 'loadaddr' */ | |
107 | #define CONFIG_SYS_LOAD_ADDR MEMADDR(0x02000000) | |
108 | ||
109 | /*==============================*/ | |
110 | /* U-Boot general configuration */ | |
111 | /*==============================*/ | |
112 | ||
113 | #undef CONFIG_USE_IRQ /* Keep it simple, poll only */ | |
114 | #define CONFIG_BOARD_POSTCLK_INIT | |
115 | #define CONFIG_DISPLAY_CPUINFO | |
116 | #define CONFIG_DISPLAY_BOARDINFO | |
117 | #define CONFIG_MISC_INIT_R | |
118 | ||
119 | #define CONFIG_BOOTFILE "uImage" | |
120 | /* Console I/O Buffer Size */ | |
121 | #define CONFIG_SYS_CBSIZE 1024 | |
122 | /* Prt buf */ | |
123 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
124 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
125 | /* max number of command args */ | |
126 | #define CONFIG_SYS_MAXARGS 16 | |
127 | /* Boot Argument Buffer Size */ | |
128 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
129 | ||
130 | /*=================*/ | |
131 | /* U-Boot commands */ | |
132 | /*=================*/ | |
133 | ||
134 | #define CONFIG_CMD_DIAG | |
135 | #define CONFIG_CMD_SAVES | |
136 | ||
137 | /*==============================*/ | |
138 | /* U-Boot autoboot configuration */ | |
139 | /*==============================*/ | |
140 | ||
141 | #define CONFIG_BOOT_RETRY_TIME 60 /* retry after 60 secs */ | |
142 | ||
7e270ec3 CZ |
143 | #define CONFIG_AUTO_COMPLETE /* Support tab autocompletion */ |
144 | #define CONFIG_CMDLINE_EDITING | |
145 | #define CONFIG_SYS_LONGHELP | |
146 | #define CONFIG_CRC32_VERIFY | |
147 | #define CONFIG_MX_CYCLIC | |
148 | #define CONFIG_SHOW_BOOT_PROGRESS | |
149 | ||
150 | #ifdef DEBUG | |
151 | #define CONFIG_PANIC_HANG 1 /* Require manual reboot */ | |
152 | #endif | |
153 | ||
154 | ||
155 | /*=========================================*/ | |
156 | /* FPGA Registers (board info and control) */ | |
157 | /*=========================================*/ | |
158 | ||
159 | /* | |
160 | * These assume FPGA bitstreams from Tensilica release RB and up. Earlier | |
161 | * releases may not provide any/all of these registers or at these offsets. | |
162 | * Some of the FPGA registers are broken down into bitfields described by | |
163 | * SHIFT left amount and field WIDTH (bits), and also by a bitMASK. | |
164 | */ | |
165 | ||
166 | /* Date of FPGA bitstream build in binary coded decimal (BCD) */ | |
167 | #define CONFIG_SYS_FPGAREG_DATE IOADDR(0x0D020000) | |
168 | #define FPGAREG_MTH_SHIFT 24 /* BCD month 1..12 */ | |
169 | #define FPGAREG_MTH_WIDTH 8 | |
170 | #define FPGAREG_MTH_MASK 0xFF000000 | |
171 | #define FPGAREG_DAY_SHIFT 16 /* BCD day 1..31 */ | |
172 | #define FPGAREG_DAY_WIDTH 8 | |
173 | #define FPGAREG_DAY_MASK 0x00FF0000 | |
174 | #define FPGAREG_YEAR_SHIFT 0 /* BCD year 2001..9999*/ | |
175 | #define FPGAREG_YEAR_WIDTH 16 | |
176 | #define FPGAREG_YEAR_MASK 0x0000FFFF | |
177 | ||
178 | /* FPGA core clock frequency in Hz (also input to UART) */ | |
179 | #define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/ | |
180 | ||
181 | /* | |
182 | * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1): | |
183 | * Bits 0..5 set the lower 6 bits of the default ethernet MAC. | |
184 | * Bit 6 is reserved for future use by Tensilica. | |
185 | * Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to | |
186 | * the base of flash * (when on/1) or to the base of RAM (when off/0). | |
187 | */ | |
188 | #define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C) | |
189 | #define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */ | |
190 | #define FPGAREG_MAC_WIDTH 6 | |
191 | #define FPGAREG_MAC_MASK 0x3f | |
192 | #define FPGAREG_BOOT_SHIFT 7 /* Boot ROM addr mapping */ | |
193 | #define FPGAREG_BOOT_WIDTH 1 | |
194 | #define FPGAREG_BOOT_MASK 0x80 | |
195 | #define FPGAREG_BOOT_RAM 0 | |
196 | #define FPGAREG_BOOT_FLASH (1<<FPGAREG_BOOT_SHIFT) | |
197 | ||
198 | /* Force hard reset of board by writing a code to this register */ | |
199 | #define CONFIG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */ | |
200 | #define CONFIG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */ | |
201 | ||
202 | /*====================*/ | |
203 | /* Serial Driver Info */ | |
204 | /*====================*/ | |
205 | ||
206 | #define CONFIG_SYS_NS16550_SERIAL | |
207 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
208 | #define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */ | |
209 | ||
210 | /* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */ | |
211 | #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ | |
212 | #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ | |
213 | #define CONFIG_BAUDRATE 115200 /* Default baud rate */ | |
214 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
215 | ||
216 | /*======================*/ | |
217 | /* Ethernet Driver Info */ | |
218 | /*======================*/ | |
219 | ||
220 | #define CONFIG_ETHBASE 00:50:C2:13:6f:00 | |
221 | #define CONFIG_SYS_ETHOC_BASE IOADDR(0x0d030000) | |
222 | #define CONFIG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000) | |
223 | ||
224 | /*=====================*/ | |
225 | /* Flash & Environment */ | |
226 | /*=====================*/ | |
227 | ||
228 | #define CONFIG_SYS_FLASH_CFI | |
229 | #define CONFIG_FLASH_CFI_DRIVER /* use generic CFI driver */ | |
230 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
231 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
232 | #ifdef CONFIG_XTFPGA_LX60 | |
233 | # define CONFIG_SYS_FLASH_SIZE 0x0040000 /* 4MB */ | |
234 | # define CONFIG_SYS_FLASH_SECT_SZ 0x10000 /* block size 64KB */ | |
235 | # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */ | |
236 | # define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000) | |
237 | # define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
238 | #elif defined(CONFIG_XTFPGA_KC705) | |
239 | # define CONFIG_SYS_FLASH_SIZE 0x8000000 /* 128MB */ | |
240 | # define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */ | |
241 | # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ | |
242 | # define CONFIG_SYS_FLASH_BASE IOADDR(0x00000000) | |
243 | # define CONFIG_SYS_MONITOR_BASE IOADDR(0x06000000) | |
244 | #else | |
245 | # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* 16MB */ | |
246 | # define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */ | |
247 | # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ | |
248 | # define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000) | |
249 | # define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
250 | #endif | |
251 | #define CONFIG_SYS_MAX_FLASH_SECT \ | |
252 | (CONFIG_SYS_FLASH_SECT_SZ/CONFIG_SYS_FLASH_PARMSECT_SZ + \ | |
253 | CONFIG_SYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ - 1) | |
254 | #define CONFIG_SYS_FLASH_PROTECTION /* hw flash protection */ | |
255 | ||
256 | /* | |
257 | * Put environment in top block (64kB) | |
258 | * Another option would be to put env. in 2nd param block offs 8KB, size 8KB | |
259 | */ | |
260 | #define CONFIG_ENV_IS_IN_FLASH | |
261 | #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SIZE - CONFIG_SYS_FLASH_SECT_SZ) | |
262 | #define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SZ | |
263 | ||
264 | /* print 'E' for empty sector on flinfo */ | |
265 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
266 | ||
267 | #endif /* __CONFIG_H */ |