[people/ms/u-boot.git] / include / configs / xupv2p.h

/*
 * (C) Copyright 2007 Michal Simek
 *
 * Michal SIMEK <monstr@monstr.eu>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include "../board/xilinx/xupv2p/xparameters.h"

#define	CONFIG_MICROBLAZE	1	/* MicroBlaze CPU */
#define	CONFIG_XUPV2P		1

/* uart */
#define CONFIG_XILINX_UARTLITE
#define	CONFIG_SERIAL_BASE	XILINX_UART_BASEADDR
#define	CONFIG_BAUDRATE		XILINX_UART_BAUDRATE
#define	CFG_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }

/* ethernet */
#define CONFIG_EMAC	1
#define XPAR_EMAC_0_DEVICE_ID	XPAR_XEMAC_NUM_INSTANCES

/*
 * setting reset address
 *
 * TEXT_BASE is set to place, where the U-BOOT run in RAM, but
 * if you want to store U-BOOT in flash, set CFG_RESET_ADDRESS
 * to FLASH memory and after loading bitstream jump to FLASH.
 * U-BOOT auto-relocate to TEXT_BASE. After RESET command Microblaze
 * jump to CFG_RESET_ADDRESS where is the original U-BOOT code.
 */
#define	CFG_RESET_ADDRESS	0x36000000

/* gpio */
#define	CFG_GPIO_0		1
#define	CFG_GPIO_0_ADDR		XILINX_GPIO_BASEADDR

/* interrupt controller */
#define	CFG_INTC_0		1
#define	CFG_INTC_0_ADDR		XILINX_INTC_BASEADDR
#define	CFG_INTC_0_NUM		XILINX_INTC_NUM_INTR_INPUTS

/* timer */
#define	CFG_TIMER_0		1
#define	CFG_TIMER_0_ADDR	XILINX_TIMER_BASEADDR
#define	CFG_TIMER_0_IRQ		XILINX_TIMER_IRQ
#define	FREQUENCE		XILINX_CLOCK_FREQ
#define	CFG_TIMER_0_PRELOAD	( FREQUENCE/1000 )

/*
 * memory layout - Example
 * TEXT_BASE = 0x3600_0000;
 * CFG_SRAM_BASE = 0x3000_0000;
 * CFG_SRAM_SIZE = 0x1000_0000;
 *
 * CFG_GBL_DATA_OFFSET = 0x3000_0000 + 0x1000_0000 - 0x1000 = 0x3FFF_F000
 * CFG_MONITOR_BASE = 0x3FFF_F000 - 0x40000 = 0x3FFB_F000
 * CFG_MALLOC_BASE = 0x3FFB_F000 - 0x40000 = 0x3FF7_F000
 *
 * 0x3000_0000	CFG_SDRAM_BASE
 *					FREE
 * 0x3600_0000	TEXT_BASE
 *		U-BOOT code
 * 0x3602_0000
 *					FREE
 *
 *					STACK
 * 0x3FF7_F000	CFG_MALLOC_BASE
 *					MALLOC_AREA	256kB	Alloc
 * 0x3FFB_F000	CFG_MONITOR_BASE
 *					MONITOR_CODE	256kB	Env
 * 0x3FFF_F000	CFG_GBL_DATA_OFFSET
 * 					GLOBAL_DATA	4kB	bd, gd
 * 0x4000_0000	CFG_SDRAM_BASE + CFG_SDRAM_SIZE
 */

/* ddr sdram - main memory */
#define	CFG_SDRAM_BASE		XILINX_RAM_START
#define	CFG_SDRAM_SIZE		XILINX_RAM_SIZE
#define	CFG_MEMTEST_START	CFG_SDRAM_BASE
#define	CFG_MEMTEST_END		(CFG_SDRAM_BASE + 0x1000)

/* global pointer */
#define	CFG_GBL_DATA_SIZE	0x1000	/* size of global data */
#define	CFG_GBL_DATA_OFFSET     (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */

/* monitor code */
#define	SIZE			0x40000
#define	CFG_MONITOR_LEN		SIZE
#define	CFG_MONITOR_BASE	(CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN)
#define	CFG_MONITOR_END		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define	CFG_MALLOC_LEN		SIZE
#define	CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)

/* stack */
#define	CFG_INIT_SP_OFFSET	CFG_MALLOC_BASE

#define	CFG_NO_FLASH		1
#define	CFG_ENV_IS_NOWHERE	1
#define	CFG_ENV_SIZE		0x1000
#define	CFG_ENV_ADDR		(CFG_MONITOR_BASE - CFG_ENV_SIZE)


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_BDI
#define CONFIG_CMD_NET
#define CONFIG_CMD_IMI
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_RUN
#define CONFIG_CMD_AUTOSCRIPT
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MISC
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_PING


/* Miscellaneous configurable options */
#define	CFG_PROMPT	"U-Boot-mONStR> "
#define	CFG_CBSIZE	512	/* size of console buffer */
#define	CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */
#define	CFG_MAXARGS	15	/* max number of command args */
#define	CFG_LONGHELP
#define	CFG_LOAD_ADDR	0x12000000 /* default load address */

#define	CONFIG_BOOTDELAY 	30
#define	CONFIG_BOOTARGS		"root=romfs"
#define	CONFIG_HOSTNAME		"ml401"
#define	CONFIG_BOOTCOMMAND 	"base 0;tftp 11000000 image.img;bootm"
#define	CONFIG_IPADDR		192.168.0.3
#define	CONFIG_SERVERIP 	192.168.0.5
#define	CONFIG_GATEWAYIP 	192.168.0.1
#define	CONFIG_ETHADDR		00:E0:0C:00:00:FD

/* architecture dependent code */
#define	CFG_USR_EXCEP	/* user exception */
#define CFG_HZ	1000

#define CONFIG_PREBOOT	"echo U-BOOT by mONStR;"	\
	"base 0;" \
	"echo"

/* system ace */
#define	CONFIG_SYSTEMACE
/* #define DEBUG_SYSTEMACE */
#define	SYSTEMACE_CONFIG_FPGA
#define	CFG_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
#define	CFG_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
#define	CONFIG_DOS_PARTITION

#endif	/* __CONFIG_H */
Commit	Line	Data
17980495	1	/*
cb1bc63b	2	* (C) Copyright 2007 Michal Simek
17980495 MS	3	*
	4	* Michal SIMEK <monstr@monstr.eu>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
	28	#include "../board/xilinx/xupv2p/xparameters.h"
	29
	30	#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */
	31	#define CONFIG_XUPV2P 1
	32
	33	/* uart */
0731cbae	34	#define CONFIG_XILINX_UARTLITE
b90c045f MS	35	#define CONFIG_SERIAL_BASE XILINX_UART_BASEADDR
b90c045f MS	36	#define CONFIG_BAUDRATE XILINX_UART_BAUDRATE
17980495 MS	37	#define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE }
	38
	39	/* ethernet */
b90c045f MS	40	#define CONFIG_EMAC 1
b90c045f MS	41	#define XPAR_EMAC_0_DEVICE_ID XPAR_XEMAC_NUM_INSTANCES
17980495 MS	42
	43	/*
	44	* setting reset address
31c98a88	45	*
17980495 MS	46	* TEXT_BASE is set to place, where the U-BOOT run in RAM, but
	47	* if you want to store U-BOOT in flash, set CFG_RESET_ADDRESS
	48	* to FLASH memory and after loading bitstream jump to FLASH.
	49	* U-BOOT auto-relocate to TEXT_BASE. After RESET command Microblaze
	50	* jump to CFG_RESET_ADDRESS where is the original U-BOOT code.
	51	*/
b90c045f	52	#define CFG_RESET_ADDRESS 0x36000000
17980495 MS	53
	54	/* gpio */
	55	#define CFG_GPIO_0 1
	56	#define CFG_GPIO_0_ADDR XILINX_GPIO_BASEADDR
	57
	58	/* interrupt controller */
	59	#define CFG_INTC_0 1
	60	#define CFG_INTC_0_ADDR XILINX_INTC_BASEADDR
	61	#define CFG_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
	62
	63	/* timer */
	64	#define CFG_TIMER_0 1
	65	#define CFG_TIMER_0_ADDR XILINX_TIMER_BASEADDR
	66	#define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ
	67	#define FREQUENCE XILINX_CLOCK_FREQ
	68	#define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 )
	69
	70	/*
	71	* memory layout - Example
	72	* TEXT_BASE = 0x3600_0000;
	73	* CFG_SRAM_BASE = 0x3000_0000;
	74	* CFG_SRAM_SIZE = 0x1000_0000;
	75	*
	76	* CFG_GBL_DATA_OFFSET = 0x3000_0000 + 0x1000_0000 - 0x1000 = 0x3FFF_F000
	77	* CFG_MONITOR_BASE = 0x3FFF_F000 - 0x40000 = 0x3FFB_F000
	78	* CFG_MALLOC_BASE = 0x3FFB_F000 - 0x40000 = 0x3FF7_F000
	79	*
	80	* 0x3000_0000 CFG_SDRAM_BASE
	81	* FREE
	82	* 0x3600_0000 TEXT_BASE
	83	* U-BOOT code
	84	* 0x3602_0000
	85	* FREE
	86	*
	87	* STACK
	88	* 0x3FF7_F000 CFG_MALLOC_BASE
	89	* MALLOC_AREA 256kB Alloc
	90	* 0x3FFB_F000 CFG_MONITOR_BASE
	91	* MONITOR_CODE 256kB Env
	92	* 0x3FFF_F000 CFG_GBL_DATA_OFFSET
	93	* GLOBAL_DATA 4kB bd, gd
	94	* 0x4000_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE
	95	*/
	96
	97	/* ddr sdram - main memory */
	98	#define CFG_SDRAM_BASE XILINX_RAM_START
	99	#define CFG_SDRAM_SIZE XILINX_RAM_SIZE
	100	#define CFG_MEMTEST_START CFG_SDRAM_BASE
	101	#define CFG_MEMTEST_END (CFG_SDRAM_BASE + 0x1000)
	102
	103	/* global pointer */
	104	#define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */
	105	#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */
	106
	107	/* monitor code */
	108	#define SIZE 0x40000
	109	#define CFG_MONITOR_LEN SIZE
	110	#define CFG_MONITOR_BASE (CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN)
	111	#define CFG_MONITOR_END (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
	112	#define CFG_MALLOC_LEN SIZE
	113	#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
	114
	115	/* stack */
	116	#define CFG_INIT_SP_OFFSET CFG_MALLOC_BASE
117
118	#define CFG_NO_FLASH 1
119	#define CFG_ENV_IS_NOWHERE 1
120	#define CFG_ENV_SIZE 0x1000
121	#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
17980495	122
b90c045f	123
079a136c JL	124	/*
	125	* BOOTP options
	126	*/
	127	#define CONFIG_BOOTP_BOOTFILESIZE
	128	#define CONFIG_BOOTP_BOOTPATH
	129	#define CONFIG_BOOTP_GATEWAY
	130	#define CONFIG_BOOTP_HOSTNAME
	131
b90c045f	132
dca3b3d6 JL	133	/*
	134	* Command line configuration.
	135	*/
	136	#include <config_cmd_default.h>
	137
b90c045f	138	#define CONFIG_CMD_MEMORY
d1ed28cf	139	#define CONFIG_CMD_IRQ
b90c045f MS	140	#define CONFIG_CMD_BDI
	141	#define CONFIG_CMD_NET
	142	#define CONFIG_CMD_IMI
	143	#define CONFIG_CMD_ECHO
	144	#define CONFIG_CMD_CACHE
	145	#define CONFIG_CMD_RUN
	146	#define CONFIG_CMD_AUTOSCRIPT
	147	#define CONFIG_CMD_ASKENV
	148	#define CONFIG_CMD_LOADS
	149	#define CONFIG_CMD_LOADB
	150	#define CONFIG_CMD_MISC
	151	#define CONFIG_CMD_FAT
	152	#define CONFIG_CMD_EXT2
d1ed28cf	153	#define CONFIG_CMD_PING
dca3b3d6	154
17980495 MS	155
	156	/* Miscellaneous configurable options */
	157	#define CFG_PROMPT "U-Boot-mONStR> "
	158	#define CFG_CBSIZE 512 /* size of console buffer */
	159	#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */
	160	#define CFG_MAXARGS 15 /* max number of command args */
	161	#define CFG_LONGHELP
	162	#define CFG_LOAD_ADDR 0x12000000 /* default load address */
	163
	164	#define CONFIG_BOOTDELAY 30
	165	#define CONFIG_BOOTARGS "root=romfs"
b90c045f	166	#define CONFIG_HOSTNAME "ml401"
17980495 MS	167	#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
	168	#define CONFIG_IPADDR 192.168.0.3
	169	#define CONFIG_SERVERIP 192.168.0.5
	170	#define CONFIG_GATEWAYIP 192.168.0.1
	171	#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
	172
	173	/* architecture dependent code */
	174	#define CFG_USR_EXCEP /* user exception */
	175	#define CFG_HZ 1000
	176
	177	#define CONFIG_PREBOOT "echo U-BOOT by mONStR;" \
	178	"base 0;" \
	179	"echo"
	180
17980495	181	/* system ace */
32556443 MS	182	#define CONFIG_SYSTEMACE
	183	/* #define DEBUG_SYSTEMACE */
	184	#define SYSTEMACE_CONFIG_FPGA
	185	#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
	186	#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
	187	#define CONFIG_DOS_PARTITION
17980495 MS	188
17980495 MS	189	#endif /* __CONFIG_H */