projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 6c5879f3 MB |
1 | /* |
| 2 | * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com> | |
| 3 | * | |
| 4 | * See file CREDITS for list of people who contributed to this | |
| 5 | * project. | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or | |
| 8 | * modify it under the terms of the GNU General Public License as | |
| 9 | * published by the Free Software Foundation; either version 2 of | |
| 10 | * the License, or (at your option) any later version. | |
| 11 | * | |
| 12 | * This program is distributed in the hope that it will be useful, | |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | * GNU General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public License | |
| 18 | * along with this program; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 20 | * MA 02111-1307 USA | |
| 21 | */ | |
| 22 | ||
| 23 | /************************************************************************ | |
| 24 | * 1 january 2005 Alain Saurel <asaurel@amcc.com> | |
| 25 | * Adapted to current Das U-Boot source | |
| 26 | ***********************************************************************/ | |
| 27 | /************************************************************************ | |
| 28 | * yucca.h - configuration for AMCC 440SPe Ref (yucca) | |
| 29 | ***********************************************************************/ | |
| 30 | ||
| 31 | #ifndef __CONFIG_H | |
| 32 | #define __CONFIG_H | |
| 33 | ||
| 6c5879f3 MB |
34 | /*----------------------------------------------------------------------- |
| 35 | * High Level Configuration Options | |
| 36 | *----------------------------------------------------------------------*/ | |
| 37 | #define CONFIG_4xx 1 /* ... PPC4xx family */ | |
| 38 | #define CONFIG_440 1 /* ... PPC440 family */ | |
| 39 | #define CONFIG_440SPE 1 /* Specifc SPe support */ | |
| 40 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
| 41 | #undef CFG_DRAM_TEST /* Disable-takes long time */ | |
| 42 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ | |
| 43 | #define EXTCLK_33_33 33333333 | |
| 44 | #define EXTCLK_66_66 66666666 | |
| 45 | #define EXTCLK_50 50000000 | |
| 46 | #define EXTCLK_83 83333333 | |
| 47 | ||
| 2f5df473 | 48 | #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ |
| 6c5879f3 MB |
49 | #undef CONFIG_SHOW_BOOT_PROGRESS |
| 50 | #undef CONFIG_STRESS | |
| 2f5df473 | 51 | |
| 6c5879f3 MB |
52 | /*----------------------------------------------------------------------- |
| 53 | * Base addresses -- Note these are effective addresses where the | |
| 54 | * actual resources get mapped (not physical addresses) | |
| 55 | *----------------------------------------------------------------------*/ | |
| 56 | #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ | |
| 57 | #define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */ | |
| 58 | #define CFG_MONITOR_BASE 0xfffb0000 /* start of monitor */ | |
| 59 | #define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ | |
| 60 | #define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */ | |
| 61 | ||
| 692519b1 | 62 | #define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ |
| 6c5879f3 | 63 | #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ |
| 692519b1 RJ |
64 | #define CFG_PCI_TARGBASE CFG_PCI_MEMBASE |
| 65 | ||
| 36b904a7 | 66 | #define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ |
| 4dbee8a9 | 67 | #define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */ |
| 36b904a7 | 68 | #define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ |
| 6c5879f3 | 69 | |
| 692519b1 | 70 | #define CFG_PCIE0_CFGBASE 0xc0000000 |
| 7f191393 GB |
71 | #define CFG_PCIE1_CFGBASE 0xc1000000 |
| 72 | #define CFG_PCIE2_CFGBASE 0xc2000000 | |
| 73 | #define CFG_PCIE0_XCFGBASE 0xc3000000 | |
| 74 | #define CFG_PCIE1_XCFGBASE 0xc3001000 | |
| 75 | #define CFG_PCIE2_XCFGBASE 0xc3002000 | |
| 692519b1 | 76 | |
| 97923770 SR |
77 | /* base address of inbound PCIe window */ |
| 78 | #define CFG_PCIE_INBOUND_BASE 0x0000000400000000ULL | |
| 79 | ||
| fbb0b559 MB |
80 | /* System RAM mapped to PCI space */ |
| 81 | #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE | |
| 82 | #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE | |
| 83 | #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) | |
| 84 | ||
| 6c5879f3 MB |
85 | #define CFG_FPGA_BASE 0xe2000000 /* epld */ |
| 86 | #define CFG_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */ | |
| 87 | ||
| 88 | /* #define CFG_NVRAM_BASE_ADDR 0x08000000 */ | |
| 89 | /*----------------------------------------------------------------------- | |
| 90 | * Initial RAM & stack pointer (placed in internal SRAM) | |
| 91 | *----------------------------------------------------------------------*/ | |
| 92 | #define CFG_TEMP_STACK_OCM 1 | |
| 93 | #define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE | |
| 94 | #define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ | |
| 95 | #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ | |
| 96 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
| 97 | ||
| 98 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
| 99 | #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) | |
| 100 | #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR | |
| 101 | ||
| 102 | #define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Mon */ | |
| 103 | #define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */ | |
| 104 | ||
| 105 | /*----------------------------------------------------------------------- | |
| 106 | * Serial Port | |
| 107 | *----------------------------------------------------------------------*/ | |
| 108 | #define CONFIG_SERIAL_MULTI 1 | |
| 109 | #undef CONFIG_UART1_CONSOLE | |
| 110 | ||
| 111 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
| 112 | #undef CFG_EXT_SERIAL_CLOCK | |
| 113 | /* #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) */ /* Ext clk @ 11.059 MHz */ | |
| 114 | ||
| 115 | #define CONFIG_BAUDRATE 115200 | |
| 116 | ||
| 117 | #define CFG_BAUDRATE_TABLE \ | |
| 118 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
| 119 | ||
| 120 | /*----------------------------------------------------------------------- | |
| 121 | * DDR SDRAM | |
| 122 | *----------------------------------------------------------------------*/ | |
| 2f5df473 SR |
123 | #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ |
| 124 | #define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/ | |
| 60723803 | 125 | #define CONFIG_DDR_ECC 1 /* with ECC support */ |
| 6c5879f3 MB |
126 | |
| 127 | /*----------------------------------------------------------------------- | |
| 128 | * I2C | |
| 129 | *----------------------------------------------------------------------*/ | |
| 130 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
| 131 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| 132 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
| 133 | #define CFG_I2C_SLAVE 0x7F | |
| 134 | ||
| 135 | #define IIC0_BOOTPROM_ADDR 0x50 | |
| 136 | #define IIC0_ALT_BOOTPROM_ADDR 0x54 | |
| 137 | ||
| 138 | /* Don't probe these addrs */ | |
| 139 | #define CFG_I2C_NOPROBES {0x50, 0x52, 0x53, 0x54} | |
| 140 | ||
| dca3b3d6 | 141 | /* #if defined(CONFIG_CMD_EEPROM) */ |
| 6c5879f3 MB |
142 | /* #define CFG_I2C_EEPROM_ADDR 0x50 */ /* I2C boot EEPROM */ |
| 143 | #define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ | |
| 144 | /* #endif */ | |
| 145 | ||
| 146 | /*----------------------------------------------------------------------- | |
| 147 | * Environment | |
| 148 | *----------------------------------------------------------------------*/ | |
| 149 | /* #define CFG_NVRAM_SIZE (0x2000 - 8) */ /* NVRAM size(8k)- RTC regs */ | |
| 150 | ||
| 151 | #undef CFG_ENV_IS_IN_NVRAM /* ... not in NVRAM */ | |
| 152 | #define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ | |
| 153 | #undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ | |
| 154 | #define CONFIG_ENV_OVERWRITE 1 | |
| 155 | ||
| caaeaf92 WD |
156 | #define CONFIG_PREBOOT "echo;" \ |
| 157 | "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ | |
| 158 | "echo" | |
| 6c5879f3 | 159 | |
| caaeaf92 | 160 | #undef CONFIG_BOOTARGS |
| 6c5879f3 MB |
161 | |
| 162 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 6c5879f3 MB |
163 | "netdev=eth0\0" \ |
| 164 | "hostname=yucca\0" \ | |
| 165 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
| 166 | "nfsroot=${serverip}:${rootpath}\0" \ | |
| 167 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
| 168 | "addip=setenv bootargs ${bootargs} " \ | |
| 169 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
| 170 | ":${hostname}:${netdev}:off panic=1\0" \ | |
| 171 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
| 172 | "flash_nfs=run nfsargs addip addtty;" \ | |
| 173 | "bootm ${kernel_addr}\0" \ | |
| 174 | "flash_self=run ramargs addip addtty;" \ | |
| 175 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
| 176 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
| 177 | "bootm\0" \ | |
| caaeaf92 | 178 | "rootpath=/opt/eldk/ppc_4xx\0" \ |
| 6c5879f3 MB |
179 | "bootfile=yucca/uImage\0" \ |
| 180 | "kernel_addr=E7F10000\0" \ | |
| 181 | "ramdisk_addr=E7F20000\0" \ | |
| 5a753f98 | 182 | "initrd_high=30000000\0" \ |
| 6c5879f3 MB |
183 | "load=tftp 100000 yuca/u-boot.bin\0" \ |
| 184 | "update=protect off 2:4-7;era 2:4-7;" \ | |
| fe84b48a | 185 | "cp.b ${fileaddr} FFFB0000 ${filesize};" \ |
| 6c5879f3 MB |
186 | "setenv filesize;saveenv\0" \ |
| 187 | "upd=run load;run update\0" \ | |
| 6efc1fc0 | 188 | "pciconfighost=1\0" \ |
| d4cb2d17 | 189 | "pcie_mode=RP:EP:EP\0" \ |
| 6c5879f3 | 190 | "" |
| caaeaf92 | 191 | #define CONFIG_BOOTCOMMAND "run flash_self" |
| 6c5879f3 | 192 | |
| caaeaf92 WD |
193 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
| 194 | ||
| 195 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 196 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
| 197 | ||
| dca3b3d6 | 198 | |
| 079a136c JL |
199 | /* |
| 200 | * BOOTP options | |
| 201 | */ | |
| 202 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 203 | #define CONFIG_BOOTP_BOOTPATH | |
| 204 | #define CONFIG_BOOTP_GATEWAY | |
| 205 | #define CONFIG_BOOTP_HOSTNAME | |
| 206 | ||
| 207 | ||
| dca3b3d6 JL |
208 | /* |
| 209 | * Command line configuration. | |
| 210 | */ | |
| 211 | #include <config_cmd_default.h> | |
| 212 | ||
| 213 | #define CONFIG_CMD_ASKENV | |
| 214 | #define CONFIG_CMD_EEPROM | |
| 215 | #define CONFIG_CMD_DHCP | |
| 216 | #define CONFIG_CMD_DIAG | |
| 217 | #define CONFIG_CMD_ELF | |
| 218 | #define CONFIG_CMD_I2C | |
| 219 | #define CONFIG_CMD_IRQ | |
| 220 | #define CONFIG_CMD_MII | |
| 221 | #define CONFIG_CMD_NET | |
| 222 | #define CONFIG_CMD_NFS | |
| 223 | #define CONFIG_CMD_PCI | |
| 224 | #define CONFIG_CMD_PING | |
| 225 | #define CONFIG_CMD_REGINFO | |
| 226 | #define CONFIG_CMD_SDRAM | |
| 227 | ||
| 6c5879f3 | 228 | |
| 2f5df473 | 229 | #define CONFIG_IBM_EMAC4_V4 1 |
| caaeaf92 WD |
230 | #define CONFIG_MII 1 /* MII PHY management */ |
| 231 | #undef CONFIG_NET_MULTI | |
| 232 | #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ | |
| 233 | #define CONFIG_HAS_ETH0 | |
| 234 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ | |
| 235 | #define CONFIG_PHY_RESET_DELAY 1000 | |
| 236 | #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ | |
| 237 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
| 238 | #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ | |
| 239 | ||
| 4f92ed5f SR |
240 | #define CONFIG_NETCONSOLE /* include NetConsole support */ |
| 241 | #define CONFIG_NET_MULTI /* needed for NetConsole */ | |
| 242 | ||
| 6c5879f3 MB |
243 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 244 | ||
| 245 | /* | |
| 246 | * Miscellaneous configurable options | |
| 247 | */ | |
| 248 | #define CFG_LONGHELP /* undef to save memory */ | |
| 249 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
| 250 | ||
| dca3b3d6 | 251 | #if defined(CONFIG_CMD_KGDB) |
| 6c5879f3 MB |
252 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 253 | #else | |
| 254 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 255 | #endif | |
| 256 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
| 257 | #define CFG_MAXARGS 16 /* max number of command args */ | |
| 258 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
| 259 | ||
| 260 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
| 261 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
| 262 | ||
| 263 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
| 264 | #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
| 265 | ||
| edd6cf20 | 266 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
| 6c5879f3 | 267 | |
| 4f92ed5f SR |
268 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
| 269 | #define CONFIG_LOOPW 1 /* enable loopw command */ | |
| 270 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ | |
| 271 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
| 272 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ | |
| 273 | ||
| 6c5879f3 MB |
274 | /*----------------------------------------------------------------------- |
| 275 | * FLASH related | |
| 276 | *----------------------------------------------------------------------*/ | |
| 277 | #define CFG_MAX_FLASH_BANKS 3 /* number of banks */ | |
| 278 | #define CFG_MAX_FLASH_SECT 256 /* sectors per device */ | |
| 279 | ||
| 280 | #undef CFG_FLASH_CHECKSUM | |
| 281 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
| 282 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
| 283 | ||
| 284 | #define CFG_FLASH_ADDR0 0x5555 | |
| 285 | #define CFG_FLASH_ADDR1 0x2aaa | |
| 286 | #define CFG_FLASH_WORD_SIZE unsigned char | |
| 287 | ||
| 288 | #define CFG_FLASH_2ND_16BIT_DEV 1 /* evb440SPe has 8 and 16bit device */ | |
| 289 | #define CFG_FLASH_2ND_ADDR 0xe7c00000 /* evb440SPe has 8 and 16bit device*/ | |
| 290 | ||
| 291 | #ifdef CFG_ENV_IS_IN_FLASH | |
| 292 | #define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ | |
| 293 | #define CFG_ENV_ADDR 0xfffa0000 | |
| 294 | /* #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) */ | |
| 295 | #define CFG_ENV_SIZE 0x10000 /* Size of Environment vars */ | |
| 296 | #endif /* CFG_ENV_IS_IN_FLASH */ | |
| 297 | /*----------------------------------------------------------------------- | |
| 298 | * PCI stuff | |
| 299 | *----------------------------------------------------------------------- | |
| 300 | */ | |
| 301 | /* General PCI */ | |
| 302 | #define CONFIG_PCI /* include pci support */ | |
| 303 | #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ | |
| fe84b48a | 304 | #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ |
| 6efc1fc0 | 305 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE |
| 6c5879f3 MB |
306 | |
| 307 | /* Board-specific PCI */ | |
| 6c5879f3 MB |
308 | #define CFG_PCI_TARGET_INIT /* let board init pci target */ |
| 309 | #undef CFG_PCI_MASTER_INIT | |
| 310 | ||
| 311 | #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ | |
| 312 | #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ | |
| 313 | /* #define CFG_PCI_SUBSYS_ID CFG_PCI_SUBSYS_DEVICEID */ | |
| 314 | ||
| 315 | /* | |
| 316 | * NETWORK Support (PCI): | |
| 317 | */ | |
| 318 | /* Support for Intel 82557/82559/82559ER chips. */ | |
| 319 | #define CONFIG_EEPRO100 | |
| 692519b1 | 320 | |
| 6c5879f3 MB |
321 | /* |
| 322 | * For booting Linux, the board info and command line data | |
| 323 | * have to be in the first 8 MB of memory, since this is | |
| 324 | * the maximum mapped by the Linux kernel during initialization. | |
| 325 | */ | |
| 326 | #define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/ | |
| 6c5879f3 MB |
327 | |
| 328 | /* | |
| 329 | * Internal Definitions | |
| 330 | * | |
| 331 | * Boot Flags | |
| 332 | */ | |
| 333 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 334 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 335 | ||
| dca3b3d6 | 336 | #if defined(CONFIG_CMD_KGDB) |
| 6c5879f3 MB |
337 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 338 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 339 | #endif | |
| 340 | ||
| 341 | /* FB Divisor selection */ | |
| 342 | #define FPGA_FB_DIV_6 6 | |
| 343 | #define FPGA_FB_DIV_10 10 | |
| 344 | #define FPGA_FB_DIV_12 12 | |
| 345 | #define FPGA_FB_DIV_20 20 | |
| 346 | ||
| 347 | /* VCO Divisor selection */ | |
| 348 | #define FPGA_VCO_DIV_4 4 | |
| 349 | #define FPGA_VCO_DIV_6 6 | |
| 350 | #define FPGA_VCO_DIV_8 8 | |
| 351 | #define FPGA_VCO_DIV_10 10 | |
| 352 | ||
| 353 | /*----------------------------------------------------------------------------+ | |
| 354 | | FPGA registers and bit definitions | |
| 355 | +----------------------------------------------------------------------------*/ | |
| 356 | /* PowerPC 440SPe Board FPGA is reached with physical address 0x1 E2000000. */ | |
| 357 | /* TLB initialization makes it correspond to logical address 0xE2000000. */ | |
| 358 | /* => Done init_chip.s in bootlib */ | |
| 359 | #define FPGA_REG_BASE_ADDR 0xE2000000 | |
| 360 | #define FPGA_GPIO_BASE_ADDR 0xE2010000 | |
| 361 | #define FPGA_INT_BASE_ADDR 0xE2020000 | |
| 362 | ||
| 363 | /*----------------------------------------------------------------------------+ | |
| 364 | | Display | |
| 365 | +----------------------------------------------------------------------------*/ | |
| 366 | #define PPC440SPE_DISPLAY FPGA_REG_BASE_ADDR | |
| 367 | ||
| 368 | #define PPC440SPE_DISPLAY_D8 (FPGA_REG_BASE_ADDR+0x06) | |
| 369 | #define PPC440SPE_DISPLAY_D4 (FPGA_REG_BASE_ADDR+0x04) | |
| 370 | #define PPC440SPE_DISPLAY_D2 (FPGA_REG_BASE_ADDR+0x02) | |
| 371 | #define PPC440SPE_DISPLAY_D1 (FPGA_REG_BASE_ADDR+0x00) | |
| 372 | /*define WRITE_DISPLAY_DIGIT(n) IOREG8(FPGA_REG_BASE_ADDR + (2*n))*/ | |
| 373 | /*#define IOREG8(addr) *((volatile unsigned char *)(addr))*/ | |
| 374 | ||
| 375 | /*----------------------------------------------------------------------------+ | |
| 376 | | ethernet/reset/boot Register 1 | |
| 377 | +----------------------------------------------------------------------------*/ | |
| 378 | #define FPGA_REG10 (FPGA_REG_BASE_ADDR+0x10) | |
| 379 | ||
| 380 | #define FPGA_REG10_10MHZ_ENABLE 0x8000 | |
| 381 | #define FPGA_REG10_100MHZ_ENABLE 0x4000 | |
| 382 | #define FPGA_REG10_GIGABIT_ENABLE 0x2000 | |
| 383 | #define FPGA_REG10_FULL_DUPLEX 0x1000 /* force Full Duplex*/ | |
| 384 | #define FPGA_REG10_RESET_ETH 0x0800 | |
| 385 | #define FPGA_REG10_AUTO_NEG_DIS 0x0400 | |
| 386 | #define FPGA_REG10_INTP_ETH 0x0200 | |
| 387 | ||
| 388 | #define FPGA_REG10_RESET_HISR 0x0080 | |
| 389 | #define FPGA_REG10_ENABLE_DISPLAY 0x0040 | |
| 390 | #define FPGA_REG10_RESET_SDRAM 0x0020 | |
| 391 | #define FPGA_REG10_OPER_BOOT 0x0010 | |
| 392 | #define FPGA_REG10_SRAM_BOOT 0x0008 | |
| 393 | #define FPGA_REG10_SMALL_BOOT 0x0004 | |
| 394 | #define FPGA_REG10_FORCE_COLA 0x0002 | |
| 395 | #define FPGA_REG10_COLA_MANUAL 0x0001 | |
| 396 | ||
| 397 | #define FPGA_REG10_SDRAM_ENABLE 0x0020 | |
| 398 | ||
| 399 | #define FPGA_REG10_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*from ocotea ?*/ | |
| 400 | #define FPGA_REG10_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*from ocotea ?*/ | |
| 401 | ||
| 402 | /*----------------------------------------------------------------------------+ | |
| 403 | | MUX control | |
| 404 | +----------------------------------------------------------------------------*/ | |
| 405 | #define FPGA_REG12 (FPGA_REG_BASE_ADDR+0x12) | |
| 406 | ||
| 407 | #define FPGA_REG12_EBC_CTL 0x8000 | |
| 408 | #define FPGA_REG12_UART1_CTS_RTS 0x4000 | |
| 409 | #define FPGA_REG12_UART0_RX_ENABLE 0x2000 | |
| 410 | #define FPGA_REG12_UART1_RX_ENABLE 0x1000 | |
| 411 | #define FPGA_REG12_UART2_RX_ENABLE 0x0800 | |
| 412 | #define FPGA_REG12_EBC_OUT_ENABLE 0x0400 | |
| 413 | #define FPGA_REG12_GPIO0_OUT_ENABLE 0x0200 | |
| 414 | #define FPGA_REG12_GPIO1_OUT_ENABLE 0x0100 | |
| 415 | #define FPGA_REG12_GPIO_SELECT 0x0010 | |
| 416 | #define FPGA_REG12_GPIO_CHREG 0x0008 | |
| 417 | #define FPGA_REG12_GPIO_CLK_CHREG 0x0004 | |
| 418 | #define FPGA_REG12_GPIO_OETRI 0x0002 | |
| 419 | #define FPGA_REG12_EBC_ERROR 0x0001 | |
| 420 | ||
| 421 | /*----------------------------------------------------------------------------+ | |
| 422 | | PCI Clock control | |
| 423 | +----------------------------------------------------------------------------*/ | |
| 424 | #define FPGA_REG16 (FPGA_REG_BASE_ADDR+0x16) | |
| 425 | ||
| 426 | #define FPGA_REG16_PCI_CLK_CTL0 0x8000 | |
| 427 | #define FPGA_REG16_PCI_CLK_CTL1 0x4000 | |
| 428 | #define FPGA_REG16_PCI_CLK_CTL2 0x2000 | |
| 429 | #define FPGA_REG16_PCI_CLK_CTL3 0x1000 | |
| 430 | #define FPGA_REG16_PCI_CLK_CTL4 0x0800 | |
| 431 | #define FPGA_REG16_PCI_CLK_CTL5 0x0400 | |
| 432 | #define FPGA_REG16_PCI_CLK_CTL6 0x0200 | |
| 433 | #define FPGA_REG16_PCI_CLK_CTL7 0x0100 | |
| 434 | #define FPGA_REG16_PCI_CLK_CTL8 0x0080 | |
| 435 | #define FPGA_REG16_PCI_CLK_CTL9 0x0040 | |
| 436 | #define FPGA_REG16_PCI_EXT_ARB0 0x0020 | |
| 437 | #define FPGA_REG16_PCI_MODE_1 0x0010 | |
| 438 | #define FPGA_REG16_PCI_TARGET_MODE 0x0008 | |
| 439 | #define FPGA_REG16_PCI_INTP_MODE 0x0004 | |
| 440 | ||
| 441 | /* FB1 Divisor selection */ | |
| 442 | #define FPGA_REG16_FB2_DIV_MASK 0x1000 | |
| 443 | #define FPGA_REG16_FB2_DIV_LOW 0x0000 | |
| 444 | #define FPGA_REG16_FB2_DIV_HIGH 0x1000 | |
| 445 | /* FB2 Divisor selection */ | |
| 446 | /* S3 switch on Board */ | |
| 447 | #define FPGA_REG16_FB1_DIV_MASK 0x2000 | |
| 448 | #define FPGA_REG16_FB1_DIV_LOW 0x0000 | |
| 449 | #define FPGA_REG16_FB1_DIV_HIGH 0x2000 | |
| 450 | /* PCI0 Clock Selection */ | |
| 451 | /* S3 switch on Board */ | |
| 452 | #define FPGA_REG16_PCI0_CLK_MASK 0x0c00 | |
| 453 | #define FPGA_REG16_PCI0_CLK_33_33 0x0000 | |
| 454 | #define FPGA_REG16_PCI0_CLK_66_66 0x0800 | |
| 455 | #define FPGA_REG16_PCI0_CLK_100 0x0400 | |
| 456 | #define FPGA_REG16_PCI0_CLK_133_33 0x0c00 | |
| 457 | /* VCO Divisor selection */ | |
| 458 | /* S3 switch on Board */ | |
| 459 | #define FPGA_REG16_VCO_DIV_MASK 0xc000 | |
| 460 | #define FPGA_REG16_VCO_DIV_4 0x0000 | |
| 461 | #define FPGA_REG16_VCO_DIV_8 0x4000 | |
| 462 | #define FPGA_REG16_VCO_DIV_6 0x8000 | |
| 463 | #define FPGA_REG16_VCO_DIV_10 0xc000 | |
| 464 | /* Master Clock Selection */ | |
| 465 | /* S3, S4 switches on Board */ | |
| 466 | #define FPGA_REG16_MASTER_CLK_MASK 0x01c0 | |
| 467 | #define FPGA_REG16_MASTER_CLK_EXT 0x0000 | |
| 468 | #define FPGA_REG16_MASTER_CLK_66_66 0x0040 | |
| 469 | #define FPGA_REG16_MASTER_CLK_50 0x0080 | |
| 470 | #define FPGA_REG16_MASTER_CLK_33_33 0x00c0 | |
| 471 | #define FPGA_REG16_MASTER_CLK_25 0x0100 | |
| 472 | ||
| 473 | /*----------------------------------------------------------------------------+ | |
| 474 | | PCI Miscellaneous | |
| 475 | +----------------------------------------------------------------------------*/ | |
| 476 | #define FPGA_REG18 (FPGA_REG_BASE_ADDR+0x18) | |
| 477 | ||
| 478 | #define FPGA_REG18_PCI_PRSNT1 0x8000 | |
| 479 | #define FPGA_REG18_PCI_PRSNT2 0x4000 | |
| 480 | #define FPGA_REG18_PCI_INTA 0x2000 | |
| 481 | #define FPGA_REG18_PCI_SLOT0_INTP 0x1000 | |
| 482 | #define FPGA_REG18_PCI_SLOT1_INTP 0x0800 | |
| 483 | #define FPGA_REG18_PCI_SLOT2_INTP 0x0400 | |
| 484 | #define FPGA_REG18_PCI_SLOT3_INTP 0x0200 | |
| 485 | #define FPGA_REG18_PCI_PCI0_VC 0x0100 | |
| 486 | #define FPGA_REG18_PCI_PCI0_VTH1 0x0080 | |
| 487 | #define FPGA_REG18_PCI_PCI0_VTH2 0x0040 | |
| 488 | #define FPGA_REG18_PCI_PCI0_VTH3 0x0020 | |
| 489 | ||
| 490 | /*----------------------------------------------------------------------------+ | |
| 491 | | PCIe Miscellaneous | |
| 492 | +----------------------------------------------------------------------------*/ | |
| 493 | #define FPGA_REG1A (FPGA_REG_BASE_ADDR+0x1A) | |
| 494 | ||
| 495 | #define FPGA_REG1A_PE0_GLED 0x8000 | |
| 496 | #define FPGA_REG1A_PE1_GLED 0x4000 | |
| 497 | #define FPGA_REG1A_PE2_GLED 0x2000 | |
| 498 | #define FPGA_REG1A_PE0_YLED 0x1000 | |
| 499 | #define FPGA_REG1A_PE1_YLED 0x0800 | |
| 500 | #define FPGA_REG1A_PE2_YLED 0x0400 | |
| 501 | #define FPGA_REG1A_PE0_PWRON 0x0200 | |
| 502 | #define FPGA_REG1A_PE1_PWRON 0x0100 | |
| 503 | #define FPGA_REG1A_PE2_PWRON 0x0080 | |
| 504 | #define FPGA_REG1A_PE0_REFCLK_ENABLE 0x0040 | |
| 505 | #define FPGA_REG1A_PE1_REFCLK_ENABLE 0x0020 | |
| 506 | #define FPGA_REG1A_PE2_REFCLK_ENABLE 0x0010 | |
| 507 | #define FPGA_REG1A_PE_SPREAD0 0x0008 | |
| 508 | #define FPGA_REG1A_PE_SPREAD1 0x0004 | |
| 509 | #define FPGA_REG1A_PE_SELSOURCE_0 0x0002 | |
| 510 | #define FPGA_REG1A_PE_SELSOURCE_1 0x0001 | |
| 511 | ||
| 512 | /*----------------------------------------------------------------------------+ | |
| 513 | | PCIe Miscellaneous | |
| 514 | +----------------------------------------------------------------------------*/ | |
| 515 | #define FPGA_REG1C (FPGA_REG_BASE_ADDR+0x1C) | |
| 516 | ||
| 517 | #define FPGA_REG1C_PE0_ROOTPOINT 0x8000 | |
| 518 | #define FPGA_REG1C_PE1_ENDPOINT 0x4000 | |
| 519 | #define FPGA_REG1C_PE2_ENDPOINT 0x2000 | |
| 520 | #define FPGA_REG1C_PE0_PRSNT 0x1000 | |
| 521 | #define FPGA_REG1C_PE1_PRSNT 0x0800 | |
| 522 | #define FPGA_REG1C_PE2_PRSNT 0x0400 | |
| 523 | #define FPGA_REG1C_PE0_WAKE 0x0080 | |
| 524 | #define FPGA_REG1C_PE1_WAKE 0x0040 | |
| 525 | #define FPGA_REG1C_PE2_WAKE 0x0020 | |
| 526 | #define FPGA_REG1C_PE0_PERST 0x0010 | |
| 692519b1 RJ |
527 | #define FPGA_REG1C_PE1_PERST 0x0008 |
| 528 | #define FPGA_REG1C_PE2_PERST 0x0004 | |
| 6c5879f3 MB |
529 | |
| 530 | /*----------------------------------------------------------------------------+ | |
| 531 | | Defines | |
| 532 | +----------------------------------------------------------------------------*/ | |
| 533 | #define PERIOD_133_33MHZ 7500 /* 7,5ns */ | |
| 534 | #define PERIOD_100_00MHZ 10000 /* 10ns */ | |
| 535 | #define PERIOD_83_33MHZ 12000 /* 12ns */ | |
| 536 | #define PERIOD_75_00MHZ 13333 /* 13,333ns */ | |
| 537 | #define PERIOD_66_66MHZ 15000 /* 15ns */ | |
| 538 | #define PERIOD_50_00MHZ 20000 /* 20ns */ | |
| 539 | #define PERIOD_33_33MHZ 30000 /* 30ns */ | |
| 540 | #define PERIOD_25_00MHZ 40000 /* 40ns */ | |
| 541 | ||
| 542 | /*---------------------------------------------------------------------------*/ | |
| 543 | ||
| 544 | #endif /* __CONFIG_H */ |